diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests')
89 files changed, 43891 insertions, 43912 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 8de825134..353384b9f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903702 # Number of seconds simulated -sim_ticks 1903702212500 # Number of ticks simulated -final_tick 1903702212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.904274 # Number of seconds simulated +sim_ticks 1904273734500 # Number of ticks simulated +final_tick 1904273734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94355 # Simulator instruction rate (inst/s) -host_op_rate 94355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3162860632 # Simulator tick rate (ticks/s) -host_mem_usage 314400 # Number of bytes of host memory used -host_seconds 601.89 # Real time elapsed on the host -sim_insts 56791782 # Number of instructions simulated -sim_ops 56791782 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 898816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24768192 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 430592 # Number of bytes read from this memory -system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 898816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7790720 # Number of bytes written to this memory -system.physmem.bytes_written::total 7790720 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387003 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6728 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121730 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121730 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 472141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13010539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1391814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 226187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15141931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 472141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41250 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4092405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4092405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4092405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 472141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13010539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1391814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 226187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19234336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450402 # Total number of read requests seen -system.physmem.writeReqs 121730 # Total number of write requests seen -system.physmem.cpureqs 577215 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28825728 # Total number of bytes read from memory -system.physmem.bytesWritten 7790720 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7790720 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 5081 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28459 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27727 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28209 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28620 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7522 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7644 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6897 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7004 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7923 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8079 # Track writes on a per bank basis +host_inst_rate 95291 # Simulator instruction rate (inst/s) +host_op_rate 95291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3200085877 # Simulator tick rate (ticks/s) +host_mem_usage 314408 # Number of bytes of host memory used +host_seconds 595.07 # Real time elapsed on the host +sim_insts 56704659 # Number of instructions simulated +sim_ops 56704659 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 939456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24909888 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 36288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 341184 # Number of bytes read from this memory +system.physmem.bytes_read::total 28877632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 939456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 36288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 975744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7866880 # Number of bytes written to this memory +system.physmem.bytes_written::total 7866880 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14679 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389217 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 567 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5331 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451213 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122920 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122920 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 493341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13081044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1392035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 19056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 179168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15164643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 493341 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 19056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4131171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4131171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4131171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 493341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13081044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1392035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 19056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 179168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19295814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451213 # Total number of read requests seen +system.physmem.writeReqs 122920 # Total number of write requests seen +system.physmem.cpureqs 579004 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28877632 # Total number of bytes read from memory +system.physmem.bytesWritten 7866880 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28877632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7866880 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4871 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28452 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27988 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28154 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28095 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28334 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27691 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7738 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7420 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7615 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7448 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8007 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7267 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7422 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7442 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7742 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7420 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8140 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8013 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7323 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry -system.physmem.totGap 1903701167000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1904269209000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450402 # Categorize read packet sizes +system.physmem.readPktSize::6 451213 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121730 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1498 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122920 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1488 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -138,395 +138,398 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 910.430717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 224.153261 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2362.806871 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14303 35.57% 35.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6082 15.12% 50.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3751 9.33% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2511 6.24% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1745 4.34% 70.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1426 3.55% 74.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1071 2.66% 76.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 838 2.08% 78.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 669 1.66% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 518 1.29% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 558 1.39% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 522 1.30% 84.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 270 0.67% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 231 0.57% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 190 0.47% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 283 0.70% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 119 0.30% 87.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 115 0.29% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 106 0.26% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 202 0.50% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 170 0.42% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 105 0.26% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 478 1.19% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 629 1.56% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 105 0.26% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 36 0.09% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 35 0.09% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 97 0.24% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 7 0.02% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 13 0.03% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 52 0.13% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 1 0.00% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 19 0.05% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 6 0.01% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 5 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 6 0.01% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 9 0.02% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 8 0.02% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 10 0.02% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 7 0.02% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 9 0.02% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 3 0.01% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 4 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 3 0.01% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 4 0.01% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 2 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 4 0.01% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 3 0.01% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2430 6.04% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 3741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5344 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 904.415372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.615874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2354.830128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14269 35.13% 35.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6234 15.35% 50.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3791 9.33% 59.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2540 6.25% 66.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1773 4.36% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1547 3.81% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1102 2.71% 76.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 849 2.09% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 692 1.70% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 549 1.35% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 540 1.33% 83.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 500 1.23% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 249 0.61% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 230 0.57% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 188 0.46% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 304 0.75% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 110 0.27% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 108 0.27% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 118 0.29% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 201 0.49% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 117 0.29% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 501 1.23% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 643 1.58% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 97 0.24% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 31 0.08% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 107 0.26% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 9 0.02% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 14 0.03% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 38 0.09% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 3 0.01% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 4 0.01% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 21 0.05% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 11 0.03% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 2 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.01% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 3 0.01% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 5 0.01% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.01% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 1 0.00% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 1 0.00% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 2 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 3 0.01% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2429 5.98% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 3 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 10 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.03% 99.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 251 0.62% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 5 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 8 0.02% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 248 0.61% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 5 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 7 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 6 0.01% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17219 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40212 # Bytes accessed per row activation -system.physmem.totQLat 6402871500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13861687750 # Sum of mem lat for all requests -system.physmem.totBusLat 2251705000 # Total cycles spent in databus access -system.physmem.totBankLat 5207111250 # Total cycles spent in bank access -system.physmem.avgQLat 14217.83 # Average queueing delay per request -system.physmem.avgBankLat 11562.60 # Average bank access latency per request +system.physmem.bytesPerActivate::17408-17411 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40619 # Bytes accessed per row activation +system.physmem.totQLat 6391304750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13854944750 # Sum of mem lat for all requests +system.physmem.totBusLat 2255690000 # Total cycles spent in databus access +system.physmem.totBankLat 5207950000 # Total cycles spent in bank access +system.physmem.avgQLat 14167.07 # Average queueing delay per request +system.physmem.avgBankLat 11544.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30780.43 # Average memory access latency -system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30711.10 # Average memory access latency +system.physmem.avgRdBW 15.16 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.13 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.16 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.13 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.34 # Average write queue length over time -system.physmem.readRowHits 434557 # Number of row buffer hits during reads -system.physmem.writeRowHits 97288 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.92 # Row buffer hit rate for writes -system.physmem.avgGap 3327381.04 # Average gap between requests -system.membus.throughput 19293384 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296598 # Transaction distribution -system.membus.trans_dist::ReadResp 296521 # Transaction distribution -system.membus.trans_dist::WriteReq 13135 # Transaction distribution -system.membus.trans_dist::WriteResp 13135 # Transaction distribution -system.membus.trans_dist::Writeback 121730 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10421 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6167 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5084 # Transaction distribution -system.membus.trans_dist::ReadExReq 162105 # Transaction distribution -system.membus.trans_dist::ReadExResp 161668 # Transaction distribution +system.physmem.avgWrQLen 14.33 # Average write queue length over time +system.physmem.readRowHits 435283 # Number of row buffer hits during reads +system.physmem.writeRowHits 98148 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.85 # Row buffer hit rate for writes +system.physmem.avgGap 3316773.66 # Average gap between requests +system.membus.throughput 19353836 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296513 # Transaction distribution +system.membus.trans_dist::ReadResp 296436 # Transaction distribution +system.membus.trans_dist::WriteReq 13046 # Transaction distribution +system.membus.trans_dist::WriteResp 13046 # Transaction distribution +system.membus.trans_dist::Writeback 122920 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9558 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5502 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4874 # Transaction distribution +system.membus.trans_dist::ReadExReq 162935 # Transaction distribution +system.membus.trans_dist::ReadExResp 162546 # Transaction distribution system.membus.trans_dist::BadAddressError 77 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921574 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 154 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 961398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 40658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1045233 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 962210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 40482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1046240 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.membus.badaddr_responder.pio 154 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1086045 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 74458 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31309568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31384026 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 74458 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36616448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36690906 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36690906 # Total data (bytes) -system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 38097999 # Layer occupancy (ticks) +system.membus.pkt_count::total 1086876 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73754 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31436416 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31510170 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 73754 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 36744512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36818266 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36818266 # Total data (bytes) +system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 37871498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1605971749 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1615737499 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 99000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3826622399 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3831920118 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376246245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376228744 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.replacements 343505 # number of replacements -system.l2c.tagsinuse 65255.093992 # Cycle average of tags in use -system.l2c.total_refs 2579423 # Total number of references to valid blocks. -system.l2c.sampled_refs 408514 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.314161 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6822436750 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53604.114045 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5280.498450 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6105.169912 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 200.990170 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 64.321415 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.817934 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080574 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093157 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003067 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000981 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995714 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 854455 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 729616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 224847 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 72618 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1881536 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 819443 # number of Writeback hits -system.l2c.Writeback_hits::total 819443 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 170 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 291 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 461 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 69 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 152110 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 27598 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179708 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 854455 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 881726 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 224847 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 100216 # number of demand (read+write) hits -system.l2c.demand_hits::total 2061244 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 854455 # number of overall hits -system.l2c.overall_hits::cpu0.data 881726 # number of overall hits -system.l2c.overall_hits::cpu1.inst 224847 # number of overall hits -system.l2c.overall_hits::cpu1.data 100216 # number of overall hits -system.l2c.overall_hits::total 2061244 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14046 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273516 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1243 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 442 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289247 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2692 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1131 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3823 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 459 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 486 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 945 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114088 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6344 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120432 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 14046 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387604 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1243 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6786 # number of demand (read+write) misses -system.l2c.demand_misses::total 409679 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 14046 # number of overall misses -system.l2c.overall_misses::cpu0.data 387604 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1243 # number of overall misses -system.l2c.overall_misses::cpu1.data 6786 # number of overall misses -system.l2c.overall_misses::total 409679 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1212902500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17141442000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 111720500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 37403000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18503468000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 969500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 5036492 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 6005992 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 803000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 136500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 939500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9233070997 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 696312000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9929382997 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1212902500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26374512997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 111720500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 733715000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 28432850997 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1212902500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26374512997 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 111720500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 733715000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 28432850997 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 868501 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1003132 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 226090 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 73060 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2170783 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 819443 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 819443 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2862 # 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average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -664,15 +667,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41695 # number of replacements -system.iocache.tagsinuse 0.492474 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1710349466000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.492474 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.030780 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.030780 # Average percentage of cache occupancy +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.488928 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.488928 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030558 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030558 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -681,14 +684,14 @@ system.iocache.demand_misses::tsunami.ide 41727 # n system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21568883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21568883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10518241771 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10518241771 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10539810654 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10539810654 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10539810654 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10539810654 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21574383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21574383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10460928278 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10460928278 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10482502661 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10482502661 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10482502661 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10482502661 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -705,19 +708,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123250.760000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123250.760000 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 253134.428451 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 253134.428451 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 252589.705802 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 252589.705802 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 276539 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123282.188571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123282.188571 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251755.108731 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 251755.108731 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 251216.302658 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 251216.302658 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 251216.302658 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 251216.302658 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 272971 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27281 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27017 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.136689 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.103675 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -731,14 +734,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41727 system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12468133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8356835276 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8356835276 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8369303409 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8369303409 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8369303409 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8369303409 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12472883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12472883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8298854290 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8298854290 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8311327173 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8311327173 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8311327173 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8311327173 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -747,14 +750,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71246.474286 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71246.474286 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 201117.522045 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 201117.522045 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71273.617143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71273.617143 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199722.138285 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199722.138285 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -768,35 +771,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12372167 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10430268 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 327512 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8051050 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5251093 # Number of BTB hits +system.cpu0.branchPred.lookups 12622908 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10616030 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 342195 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8196943 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5349460 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.222462 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 787082 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28165 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.261647 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 815211 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29656 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8811099 # DTB read hits -system.cpu0.dtb.read_misses 30390 # DTB read misses -system.cpu0.dtb.read_acv 555 # DTB read access violations -system.cpu0.dtb.read_accesses 626499 # DTB read accesses -system.cpu0.dtb.write_hits 5759352 # DTB write hits -system.cpu0.dtb.write_misses 7345 # DTB write misses -system.cpu0.dtb.write_acv 331 # DTB write access violations -system.cpu0.dtb.write_accesses 208988 # DTB write accesses -system.cpu0.dtb.data_hits 14570451 # DTB hits -system.cpu0.dtb.data_misses 37735 # DTB misses -system.cpu0.dtb.data_acv 886 # DTB access violations -system.cpu0.dtb.data_accesses 835487 # DTB accesses -system.cpu0.itb.fetch_hits 988720 # ITB hits -system.cpu0.itb.fetch_misses 28459 # ITB misses -system.cpu0.itb.fetch_acv 940 # ITB acv -system.cpu0.itb.fetch_accesses 1017179 # ITB accesses +system.cpu0.dtb.read_hits 9003860 # DTB read hits +system.cpu0.dtb.read_misses 33263 # DTB read misses +system.cpu0.dtb.read_acv 538 # DTB read access violations +system.cpu0.dtb.read_accesses 672573 # DTB read accesses +system.cpu0.dtb.write_hits 5893133 # DTB write hits +system.cpu0.dtb.write_misses 8284 # DTB write misses +system.cpu0.dtb.write_acv 368 # DTB write access violations +system.cpu0.dtb.write_accesses 235576 # DTB write accesses +system.cpu0.dtb.data_hits 14896993 # DTB hits +system.cpu0.dtb.data_misses 41547 # DTB misses +system.cpu0.dtb.data_acv 906 # DTB access violations +system.cpu0.dtb.data_accesses 908149 # DTB accesses +system.cpu0.itb.fetch_hits 1042149 # ITB hits +system.cpu0.itb.fetch_misses 31540 # ITB misses +system.cpu0.itb.fetch_acv 1064 # ITB acv +system.cpu0.itb.fetch_accesses 1073689 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -809,269 +812,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 113576100 # number of cpu cycles simulated +system.cpu0.numCycles 115698572 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24795587 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63494847 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12372167 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6038175 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11937811 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1694344 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37245698 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31806 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 195246 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 359396 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7671411 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 221670 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 75653727 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.839282 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.177028 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25430461 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 64765722 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12622908 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6164671 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12173111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1754282 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37681561 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 33129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 206182 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 360791 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 463 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7843120 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 229143 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 77014869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.840951 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.178782 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63715916 84.22% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 763032 1.01% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1559362 2.06% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 696709 0.92% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2577784 3.41% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 516509 0.68% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 573501 0.76% 93.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 819035 1.08% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4431879 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64841758 84.19% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 778083 1.01% 85.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1579221 2.05% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 722075 0.94% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2615191 3.40% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 535253 0.69% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 589170 0.77% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 842021 1.09% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4512097 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 75653727 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.108933 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.559051 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26076145 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36746783 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10850479 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 927296 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1053023 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 507905 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35356 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62314637 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 105308 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1053023 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27090322 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 15013520 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18214120 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10165522 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4117218 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58954969 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7221 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 636497 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1465868 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39489312 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71817747 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71438623 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 379124 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34689683 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4799621 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1442009 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 210125 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11209509 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9215492 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6028586 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1140138 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 729797 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52283270 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1794569 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51124724 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87475 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5854476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3047065 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1215266 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 75653727 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.675773 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.327184 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77014869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109102 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.559780 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26714732 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 37197398 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11068686 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 941364 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1092688 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 522796 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 36882 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 63559406 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 110759 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1092688 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27743135 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15107351 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18539290 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10375436 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4156967 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 60135459 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7108 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 639244 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1468640 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 40265671 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 73230382 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72843642 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 386740 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 35289688 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4975975 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1473731 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 214800 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11344202 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9431276 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6179329 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1162337 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 768163 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53333771 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1831002 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52106137 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 101747 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6058761 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3179609 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1240264 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77014869 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.676572 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.327910 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52928215 69.96% 69.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10364815 13.70% 83.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4648030 6.14% 89.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3048990 4.03% 93.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2439160 3.22% 97.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1210231 1.60% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 645067 0.85% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 315070 0.42% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54149 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 53895136 69.98% 69.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10485242 13.61% 83.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4754218 6.17% 89.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3135006 4.07% 93.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2479570 3.22% 97.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1230098 1.60% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 664050 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 318021 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53528 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 75653727 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77014869 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82277 12.13% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 315255 46.46% 58.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 280962 41.41% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 83201 11.94% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 325493 46.71% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 288201 41.36% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35245093 68.94% 68.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56186 0.11% 69.06% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15594 0.03% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9165347 17.93% 87.02% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5826893 11.40% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 809947 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35867732 68.84% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57468 0.11% 68.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.95% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15763 0.03% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9368607 17.98% 86.97% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5962928 11.44% 98.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 827971 1.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51124724 # Type of FU issued -system.cpu0.iq.rate 0.450136 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 678494 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 178124739 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59681238 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50082929 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 544404 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 263662 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 256861 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51514533 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 284900 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 542155 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52106137 # Type of FU issued +system.cpu0.iq.rate 0.450361 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 696895 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013375 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 181470771 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60967498 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51029740 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 555013 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 268874 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 261978 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52508945 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 290302 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 547963 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1111126 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3856 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12844 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 447697 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1165767 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4234 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13137 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 465736 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 153340 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18478 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 155290 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1053023 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10729289 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 792549 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57283617 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 622169 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9215492 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6028586 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1581349 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 577410 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6280 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12844 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 162347 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 348099 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 510446 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50735914 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8864635 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 388809 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1092688 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10796951 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 798319 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58424017 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 633798 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9431276 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6179329 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1612922 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 582630 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5498 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13137 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 168729 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 358890 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 527619 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51705429 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9061014 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 400707 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3205778 # number of nop insts executed -system.cpu0.iew.exec_refs 14644864 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8078425 # Number of branches executed -system.cpu0.iew.exec_stores 5780229 # Number of stores executed -system.cpu0.iew.exec_rate 0.446713 # Inst execution rate -system.cpu0.iew.wb_sent 50428595 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50339790 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25084021 # num instructions producing a value -system.cpu0.iew.wb_consumers 33790368 # num instructions consuming a value +system.cpu0.iew.exec_nop 3259244 # number of nop insts executed +system.cpu0.iew.exec_refs 14976241 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8231181 # Number of branches executed +system.cpu0.iew.exec_stores 5915227 # Number of stores executed +system.cpu0.iew.exec_rate 0.446898 # Inst execution rate +system.cpu0.iew.wb_sent 51387761 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51291718 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25550537 # num instructions producing a value +system.cpu0.iew.wb_consumers 34415470 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.443225 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742342 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.443322 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742414 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6311482 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 579303 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 475138 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 74600704 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.681919 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.596319 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6546847 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 590738 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 492268 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75922181 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.681996 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.596696 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55419889 74.29% 74.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8033545 10.77% 85.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4371447 5.86% 90.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2356278 3.16% 94.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1324268 1.78% 95.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 555518 0.74% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 469565 0.63% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 427219 0.57% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1642975 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56427011 74.32% 74.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8133810 10.71% 85.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4455745 5.87% 90.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2411043 3.18% 94.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1335893 1.76% 95.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 570067 0.75% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 478554 0.63% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 445477 0.59% 97.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1664581 2.19% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 74600704 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50871658 # Number of instructions committed -system.cpu0.commit.committedOps 50871658 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75922181 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51778647 # Number of instructions committed +system.cpu0.commit.committedOps 51778647 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13685255 # Number of memory references committed -system.cpu0.commit.loads 8104366 # Number of loads committed -system.cpu0.commit.membars 196950 # Number of memory barriers committed -system.cpu0.commit.branches 7686240 # Number of branches committed -system.cpu0.commit.fp_insts 254806 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47114322 # Number of committed integer instructions. -system.cpu0.commit.function_calls 650737 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1642975 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13979102 # Number of memory references committed +system.cpu0.commit.loads 8265509 # Number of loads committed +system.cpu0.commit.membars 200777 # Number of memory barriers committed +system.cpu0.commit.branches 7822311 # Number of branches committed +system.cpu0.commit.fp_insts 259967 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47959803 # Number of committed integer instructions. +system.cpu0.commit.function_calls 666551 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1664581 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 129943858 # The number of ROB reads -system.cpu0.rob.rob_writes 115419344 # The number of ROB writes -system.cpu0.timesIdled 1091777 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 37922373 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693821721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47948786 # Number of Instructions Simulated -system.cpu0.committedOps 47948786 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47948786 # Number of Instructions Simulated -system.cpu0.cpi 2.368696 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.368696 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.422173 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.422173 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66777793 # number of integer regfile reads -system.cpu0.int_regfile_writes 36448823 # number of integer regfile writes -system.cpu0.fp_regfile_reads 126128 # number of floating regfile reads -system.cpu0.fp_regfile_writes 127569 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1693303 # number of misc regfile reads -system.cpu0.misc_regfile_writes 810480 # number of misc regfile writes +system.cpu0.rob.rob_reads 132380203 # The number of ROB reads +system.cpu0.rob.rob_writes 117743806 # The number of ROB writes +system.cpu0.timesIdled 1106178 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38683703 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3692842270 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48811521 # Number of Instructions Simulated +system.cpu0.committedOps 48811521 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 48811521 # Number of Instructions Simulated +system.cpu0.cpi 2.370313 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.370313 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.421885 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.421885 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68020458 # number of integer regfile reads +system.cpu0.int_regfile_writes 37124303 # number of integer regfile writes +system.cpu0.fp_regfile_reads 128594 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130201 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1727987 # number of misc regfile reads +system.cpu0.misc_regfile_writes 827975 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1103,49 +1106,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111431458 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2199741 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2199647 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13135 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13135 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 819443 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10566 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6236 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16802 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 343057 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301508 # Transaction distribution +system.toL2Bus.throughput 111303171 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2194950 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2194857 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13046 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13046 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 821103 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9701 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5568 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15269 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 343378 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301828 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 77 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1737096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3343563 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 452207 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 314296 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5847162 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 55584064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 129094452 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 14469760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 11514982 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 210663258 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 210652954 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1479360 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4959879460 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1783020 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3388598 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 397843 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 270349 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5839810 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 57053376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 131002064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 12730112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 9815754 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 210601306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 210591002 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1360704 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964254488 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3910967404 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4017252621 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5778463419 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5927096055 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1017961113 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 540290711 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 895637092 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 468506529 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1437243 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 54687 # Transaction distribution -system.iobus.trans_dist::WriteResp 54687 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1436442 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7370 # Transaction distribution +system.iobus.trans_dist::ReadResp 7370 # Transaction distribution +system.iobus.trans_dist::WriteReq 54598 # Transaction distribution +system.iobus.trans_dist::WriteResp 54598 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1156,11 +1159,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40658 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40482 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1172,9 +1175,9 @@ system.iobus.pkt_count::system.tsunami.ethernet.pio 102 system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 124112 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123936 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1185,11 +1188,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 74458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 73754 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1201,11 +1204,11 @@ system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2736082 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2736082 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11417000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2735378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2735378 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11237000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1225,253 +1228,253 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378279654 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 378252917 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27523000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27436000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43098256 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.replacements 867916 # number of replacements -system.cpu0.icache.tagsinuse 509.785268 # Cycle average of tags in use -system.cpu0.icache.total_refs 6758563 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 868427 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.782534 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 25769681000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.785268 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995674 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995674 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6758564 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6758564 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6758564 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6758564 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6758564 # number of overall hits -system.cpu0.icache.overall_hits::total 6758564 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 912847 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 912847 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 912847 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 912847 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 912847 # number of overall misses -system.cpu0.icache.overall_misses::total 912847 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13149310993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13149310993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13149310993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13149310993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13149310993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13149310993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7671411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7671411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7671411 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7671411 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7671411 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7671411 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118993 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118993 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118993 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118993 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118993 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118993 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14404.726086 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14404.726086 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14404.726086 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14404.726086 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3418 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 152 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.486842 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 890887 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.759385 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6905559 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 891396 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.746904 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.759385 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995624 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995624 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6905559 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6905559 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6905559 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6905559 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6905559 # number of overall hits +system.cpu0.icache.overall_hits::total 6905559 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 937559 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 937559 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 937559 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 937559 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 937559 # number of overall misses +system.cpu0.icache.overall_misses::total 937559 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13556216106 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13556216106 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13556216106 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13556216106 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13556216106 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13556216106 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7843118 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7843118 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7843118 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7843118 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7843118 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7843118 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119539 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.119539 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119539 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.119539 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119539 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.119539 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14459.053890 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14459.053890 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14459.053890 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14459.053890 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14459.053890 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14459.053890 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6417 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1109 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 220 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.168182 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 554.500000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44252 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 44252 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 44252 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 44252 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 44252 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 44252 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868595 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 868595 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 868595 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 868595 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 868595 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 868595 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814937089 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814937089 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814937089 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10814937089 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814937089 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10814937089 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113225 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113225 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113225 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12451.069934 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45998 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45998 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45998 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45998 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45998 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45998 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 891561 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 891561 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 891561 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 891561 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 891561 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 891561 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11118457121 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11118457121 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11118457121 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11118457121 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11118457121 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11118457121 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113674 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113674 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113674 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12470.775551 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12470.775551 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12470.775551 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1271376 # number of replacements -system.cpu0.dcache.tagsinuse 505.686526 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10390956 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1271888 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.169710 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 25830000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.686526 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987669 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987669 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6393137 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6393137 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3639350 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3639350 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 161427 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 161427 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185616 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 185616 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10032487 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10032487 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10032487 # number of overall hits -system.cpu0.dcache.overall_hits::total 10032487 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1573505 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1573505 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1738147 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1738147 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20045 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20045 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3020 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3020 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3311652 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3311652 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3311652 # number of overall misses -system.cpu0.dcache.overall_misses::total 3311652 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39654304500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39654304500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77521243901 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77521243901 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 292960500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 292960500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 22204000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 22204000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117175548401 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117175548401 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117175548401 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117175548401 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7966642 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7966642 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5377497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5377497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181472 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 181472 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188636 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 188636 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13344139 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13344139 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13344139 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13344139 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197512 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197512 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323226 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323226 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110458 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110458 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248173 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248173 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248173 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248173 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25201.257384 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25201.257384 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44599.935392 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44599.935392 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14615.140933 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14615.140933 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7352.317881 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7352.317881 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35382.808460 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35382.808460 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2842539 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 840 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 51698 # number of cycles access was blocked +system.cpu0.dcache.tags.replacements 1288020 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.688069 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10644807 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1288532 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.261189 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.688069 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987672 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.987672 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6550900 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6550900 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3728429 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3728429 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165070 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 165070 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189835 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 189835 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10279329 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10279329 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10279329 # number of overall hits +system.cpu0.dcache.overall_hits::total 10279329 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1597921 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1597921 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1777729 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1777729 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20672 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20672 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2669 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2669 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3375650 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3375650 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3375650 # number of overall misses +system.cpu0.dcache.overall_misses::total 3375650 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40268021859 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40268021859 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79880065793 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 79880065793 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301767496 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 301767496 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20162915 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20162915 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 120148087652 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 120148087652 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 120148087652 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 120148087652 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8148821 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8148821 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5506158 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5506158 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185742 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 185742 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13654979 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13654979 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13654979 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13654979 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.196092 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.196092 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322862 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.322862 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111294 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111294 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013865 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013865 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247210 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.247210 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247210 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.247210 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25200.258247 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25200.258247 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44933.769879 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44933.769879 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14597.885836 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14597.885836 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7554.482952 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7554.482952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35592.578511 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35592.578511 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35592.578511 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35592.578511 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2948269 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1258 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 52342 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 54.983539 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 120 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 56.327022 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 179.714286 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 746874 # number of writebacks -system.cpu0.dcache.writebacks::total 746874 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 575080 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 575080 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465992 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1465992 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4461 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4461 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2041072 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2041072 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2041072 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2041072 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 998425 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 998425 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272155 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 272155 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15584 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15584 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3020 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3020 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1270580 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1270580 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1270580 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1270580 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26454916051 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26454916051 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11388682739 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11388682739 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172348003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172348003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 16164000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 16164000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 37843598790 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 37843598790 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 37843598790 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 37843598790 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459347502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459347502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2156087498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2156087498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3615435000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3615435000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125326 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125326 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050610 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050610 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085876 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085876 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095216 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095216 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26496.648272 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26496.648272 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41846.310885 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41846.310885 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11059.291774 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11059.291774 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5352.317881 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5352.317881 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 760237 # number of writebacks +system.cpu0.dcache.writebacks::total 760237 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 590547 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 590547 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1499620 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1499620 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4585 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4585 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2090167 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2090167 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2090167 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2090167 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1007374 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1007374 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 278109 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 278109 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16087 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16087 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2668 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2668 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1285483 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1285483 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1285483 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1285483 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26624787726 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26624787726 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11708735082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11708735082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178034254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178034254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14826085 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14826085 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38333522808 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38333522808 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38333522808 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38333522808 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465041000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465041000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2164117998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2164117998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3629158998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3629158998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123622 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123622 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050509 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050509 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086609 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086609 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013859 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013859 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094140 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094140 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26429.893690 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26429.893690 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42101.244771 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42101.244771 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11066.964257 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11066.964257 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5557.003373 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5557.003373 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1479,35 +1482,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2604526 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2153409 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 75247 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1513707 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 876072 # Number of BTB hits +system.cpu1.branchPred.lookups 2340238 # Number of BP lookups +system.cpu1.branchPred.condPredicted 1946356 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 62804 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1358794 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 776922 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.875930 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 179167 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7740 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.177320 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 157214 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 6628 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1932131 # DTB read hits -system.cpu1.dtb.read_misses 10237 # DTB read misses -system.cpu1.dtb.read_acv 25 # DTB read access violations -system.cpu1.dtb.read_accesses 320506 # DTB read accesses -system.cpu1.dtb.write_hits 1251341 # DTB write hits -system.cpu1.dtb.write_misses 1962 # DTB write misses -system.cpu1.dtb.write_acv 65 # DTB write access violations -system.cpu1.dtb.write_accesses 130037 # DTB write accesses -system.cpu1.dtb.data_hits 3183472 # DTB hits -system.cpu1.dtb.data_misses 12199 # DTB misses -system.cpu1.dtb.data_acv 90 # DTB access violations -system.cpu1.dtb.data_accesses 450543 # DTB accesses -system.cpu1.itb.fetch_hits 430844 # ITB hits -system.cpu1.itb.fetch_misses 6753 # ITB misses -system.cpu1.itb.fetch_acv 212 # ITB acv -system.cpu1.itb.fetch_accesses 437597 # ITB accesses +system.cpu1.dtb.read_hits 1733483 # DTB read hits +system.cpu1.dtb.read_misses 9288 # DTB read misses +system.cpu1.dtb.read_acv 9 # DTB read access violations +system.cpu1.dtb.read_accesses 276268 # DTB read accesses +system.cpu1.dtb.write_hits 1103623 # DTB write hits +system.cpu1.dtb.write_misses 1818 # DTB write misses +system.cpu1.dtb.write_acv 38 # DTB write access violations +system.cpu1.dtb.write_accesses 104203 # DTB write accesses +system.cpu1.dtb.data_hits 2837106 # DTB hits +system.cpu1.dtb.data_misses 11106 # DTB misses +system.cpu1.dtb.data_acv 47 # DTB access violations +system.cpu1.dtb.data_accesses 380471 # DTB accesses +system.cpu1.itb.fetch_hits 375000 # ITB hits +system.cpu1.itb.fetch_misses 5508 # ITB misses +system.cpu1.itb.fetch_acv 148 # ITB acv +system.cpu1.itb.fetch_accesses 380508 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1520,508 +1523,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 15794943 # number of cpu cycles simulated +system.cpu1.numCycles 14113255 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6044274 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12313553 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2604526 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1055239 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2204838 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 395965 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6209579 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26246 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 62195 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 53260 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1481011 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 50405 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14852690 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.829045 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.204427 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5353605 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 10974333 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2340238 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 934136 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1960258 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 346091 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 5695969 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 25528 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 53832 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 54284 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1309338 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 41617 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 13363974 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.821188 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.197770 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12647852 85.16% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 141564 0.95% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 235652 1.59% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 175889 1.18% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 303768 2.05% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 119285 0.80% 91.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 129403 0.87% 92.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 209113 1.41% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 890164 5.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11403716 85.33% 85.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 124023 0.93% 86.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 213549 1.60% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 153465 1.15% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 264643 1.98% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 105166 0.79% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 115273 0.86% 92.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 186335 1.39% 94.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 797804 5.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14852690 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164896 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.779588 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5971093 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6462269 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2062064 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 112088 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 245175 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 113398 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7205 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12081319 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21458 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 245175 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6179272 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 425366 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5395094 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1962879 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 644902 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11197795 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 57093 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 157527 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7361429 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13363056 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13213666 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 149390 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6300177 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1061252 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 451071 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 42573 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1993362 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2041709 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1326014 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 180090 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 100258 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9822573 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 491625 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9565946 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29815 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1410113 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 705464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 352077 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14852690 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644055 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.318534 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 13363974 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.165818 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.777590 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5293087 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 5922521 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1836128 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 97560 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 214677 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 97799 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 5876 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 10774764 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 17225 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 214677 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5481600 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 352411 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4990949 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1741665 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 582670 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 9967248 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 54670 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 132191 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 6553947 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 11886744 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 11748684 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 138060 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5636582 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 917365 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 415822 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 37623 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1815514 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1827244 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1170543 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 163690 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 89610 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 8737156 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 452580 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 8518295 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 27160 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1245229 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 620627 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 325893 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 13363974 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.637407 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.312561 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10648951 71.70% 71.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1930050 12.99% 84.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 818337 5.51% 90.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 551122 3.71% 93.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 476075 3.21% 97.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 213789 1.44% 98.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 136394 0.92% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 69529 0.47% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8443 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9608930 71.90% 71.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1736625 12.99% 84.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 727835 5.45% 90.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 487296 3.65% 93.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 421265 3.15% 97.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 191133 1.43% 98.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 120060 0.90% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 63613 0.48% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 7217 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14852690 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 13363974 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3207 1.63% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 106178 53.97% 55.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 87357 44.40% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2685 1.53% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 94663 54.03% 55.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 77863 44.44% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5966011 62.37% 62.40% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16243 0.17% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10971 0.11% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2021702 21.13% 83.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1274955 13.33% 97.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 270775 2.83% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5299330 62.21% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 14840 0.17% 62.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10732 0.13% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1812344 21.28% 83.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1125275 13.21% 97.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 250497 2.94% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9565946 # Type of FU issued -system.cpu1.iq.rate 0.605633 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 196742 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020567 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 33995446 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11620704 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9288457 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 215693 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 105258 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 101999 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9646700 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 112462 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 92569 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 8518295 # Type of FU issued +system.cpu1.iq.rate 0.603567 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 175211 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020569 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 30403276 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 10338814 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8274405 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 199659 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 97460 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 94461 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 8585899 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 104089 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 83773 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 282729 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1535 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1711 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 123624 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 247116 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1193 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1397 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 111584 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 323 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 14236 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 268 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 14213 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 245175 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 256542 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 43339 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10829040 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 147658 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2041709 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1326014 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 444647 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 36382 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1620 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1711 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 33953 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 99696 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 133649 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9473535 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1949759 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 92411 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 214677 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 210872 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 38123 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 9643840 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 131515 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1827244 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1170543 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 410565 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 32525 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1557 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1397 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28168 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 87904 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 116072 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8443529 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1749257 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 74766 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 514842 # number of nop insts executed -system.cpu1.iew.exec_refs 3209162 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1413585 # Number of branches executed -system.cpu1.iew.exec_stores 1259403 # Number of stores executed -system.cpu1.iew.exec_rate 0.599783 # Inst execution rate -system.cpu1.iew.wb_sent 9417236 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9390456 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4401006 # num instructions producing a value -system.cpu1.iew.wb_consumers 6190652 # num instructions consuming a value +system.cpu1.iew.exec_nop 454104 # number of nop insts executed +system.cpu1.iew.exec_refs 2860324 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1252098 # Number of branches executed +system.cpu1.iew.exec_stores 1111067 # Number of stores executed +system.cpu1.iew.exec_rate 0.598269 # Inst execution rate +system.cpu1.iew.wb_sent 8394111 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8368866 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 3943473 # num instructions producing a value +system.cpu1.iew.wb_consumers 5568899 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.594523 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710912 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.592979 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.708124 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1449457 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 139548 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 125475 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14607515 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.636458 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.578813 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1277535 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 126687 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 110026 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13149297 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.631052 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.572436 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11126487 76.17% 76.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1625013 11.12% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 604004 4.13% 91.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 371910 2.55% 93.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 263907 1.81% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 102565 0.70% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 109537 0.75% 97.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 110097 0.75% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 293995 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10035587 76.32% 76.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1461499 11.11% 87.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 536339 4.08% 91.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 329312 2.50% 94.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 237007 1.80% 95.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 91157 0.69% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 98866 0.75% 97.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 97470 0.74% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 262060 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14607515 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9297065 # Number of instructions committed -system.cpu1.commit.committedOps 9297065 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13149297 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8297892 # Number of instructions committed +system.cpu1.commit.committedOps 8297892 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2961370 # Number of memory references committed -system.cpu1.commit.loads 1758980 # Number of loads committed -system.cpu1.commit.membars 44792 # Number of memory barriers committed -system.cpu1.commit.branches 1328076 # Number of branches committed -system.cpu1.commit.fp_insts 100787 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8610735 # Number of committed integer instructions. -system.cpu1.commit.function_calls 147103 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 293995 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2639087 # Number of memory references committed +system.cpu1.commit.loads 1580128 # Number of loads committed +system.cpu1.commit.membars 40354 # Number of memory barriers committed +system.cpu1.commit.branches 1179945 # Number of branches committed +system.cpu1.commit.fp_insts 93281 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7680197 # Number of committed integer instructions. +system.cpu1.commit.function_calls 130349 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 262060 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 24970897 # The number of ROB reads -system.cpu1.rob.rob_writes 21736671 # The number of ROB writes -system.cpu1.timesIdled 134601 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 942253 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3790981004 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8842996 # Number of Instructions Simulated -system.cpu1.committedOps 8842996 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8842996 # Number of Instructions Simulated -system.cpu1.cpi 1.786153 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.786153 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.559862 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.559862 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12205153 # number of integer regfile reads -system.cpu1.int_regfile_writes 6674473 # number of integer regfile writes -system.cpu1.fp_regfile_reads 55471 # number of floating regfile reads -system.cpu1.fp_regfile_writes 55305 # number of floating regfile writes -system.cpu1.misc_regfile_reads 527113 # number of misc regfile reads -system.cpu1.misc_regfile_writes 218222 # number of misc regfile writes -system.cpu1.icache.replacements 225540 # number of replacements -system.cpu1.icache.tagsinuse 470.721925 # Cycle average of tags in use -system.cpu1.icache.total_refs 1246547 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 226052 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.514426 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1877726350000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.721925 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919379 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919379 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1246547 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1246547 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1246547 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1246547 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1246547 # number of overall hits -system.cpu1.icache.overall_hits::total 1246547 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 234464 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 234464 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 234464 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 234464 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 234464 # number of overall misses -system.cpu1.icache.overall_misses::total 234464 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3166624000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3166624000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3166624000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3166624000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3166624000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3166624000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1481011 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1481011 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1481011 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1481011 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1481011 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1481011 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158313 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.158313 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158313 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.158313 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158313 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.158313 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.800464 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.800464 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13505.800464 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13505.800464 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked +system.cpu1.rob.rob_reads 22380631 # The number of ROB reads +system.cpu1.rob.rob_writes 19363835 # The number of ROB writes +system.cpu1.timesIdled 119058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 749281 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3793736462 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 7893138 # Number of Instructions Simulated +system.cpu1.committedOps 7893138 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 7893138 # Number of Instructions Simulated +system.cpu1.cpi 1.788041 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.788041 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.559271 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.559271 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 10874027 # number of integer regfile reads +system.cpu1.int_regfile_writes 5958512 # number of integer regfile writes +system.cpu1.fp_regfile_reads 51748 # number of floating regfile reads +system.cpu1.fp_regfile_writes 51512 # number of floating regfile writes +system.cpu1.misc_regfile_reads 484557 # number of misc regfile reads +system.cpu1.misc_regfile_writes 198633 # number of misc regfile writes +system.cpu1.icache.tags.replacements 198364 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.505741 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1103940 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 198874 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.550952 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1894556454000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.505741 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918957 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.918957 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1103940 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1103940 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1103940 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1103940 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1103940 # number of overall hits +system.cpu1.icache.overall_hits::total 1103940 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 205398 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 205398 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 205398 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 205398 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 205398 # number of overall misses +system.cpu1.icache.overall_misses::total 205398 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2726676790 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2726676790 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2726676790 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2726676790 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2726676790 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2726676790 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1309338 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1309338 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1309338 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1309338 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1309338 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1309338 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.156872 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.156872 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.156872 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.156872 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.156872 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.156872 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13275.089290 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13275.089290 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13275.089290 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13275.089290 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 27 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.777778 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.166667 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8347 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8347 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8347 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8347 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8347 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8347 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 226117 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 226117 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 226117 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 226117 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 226117 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 226117 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2628094387 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2628094387 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2628094387 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2628094387 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2628094387 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2628094387 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152677 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.152677 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.152677 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11622.719154 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6463 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6463 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6463 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6463 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6463 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6463 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 198935 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 198935 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 198935 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 198935 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 198935 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 198935 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2267895657 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2267895657 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2267895657 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2267895657 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2267895657 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2267895657 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151936 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.151936 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.151936 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11400.184266 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11400.184266 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11400.184266 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 108851 # number of replacements -system.cpu1.dcache.tagsinuse 491.736427 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2599646 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 109251 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 23.795169 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 43858959000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 491.736427 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.960423 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.960423 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1587502 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1587502 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 943251 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 943251 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 32579 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 32579 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 31559 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 31559 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2530753 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2530753 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2530753 # number of overall hits -system.cpu1.dcache.overall_hits::total 2530753 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 209244 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 209244 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 218379 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 218379 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5510 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5510 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3216 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3216 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 427623 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 427623 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 427623 # number of overall misses -system.cpu1.dcache.overall_misses::total 427623 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2938034500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2938034500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7305073698 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7305073698 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 55149000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 55149000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 23385500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 23385500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10243108198 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10243108198 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10243108198 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10243108198 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1796746 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1796746 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1161630 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1161630 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38089 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 38089 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 34775 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 34775 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2958376 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2958376 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2958376 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2958376 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.116457 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.116457 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187994 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.187994 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.144661 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.144661 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092480 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092480 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.144547 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.144547 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.144547 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.144547 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14041.188756 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14041.188756 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33451.356119 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 33451.356119 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10008.892922 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10008.892922 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7271.610697 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7271.610697 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23953.595101 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23953.595101 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 227083 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 93782 # number of replacements +system.cpu1.dcache.tags.tagsinuse 490.645175 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2322631 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 94098 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.683107 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 44824844250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 490.645175 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.958291 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.958291 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1425624 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1425624 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 844173 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 844173 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 28774 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 28774 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27671 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 27671 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2269797 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2269797 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2269797 # number of overall hits +system.cpu1.dcache.overall_hits::total 2269797 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 184725 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 184725 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 178548 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 178548 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4789 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4789 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2902 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2902 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 363273 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 363273 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 363273 # number of overall misses +system.cpu1.dcache.overall_misses::total 363273 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2584165220 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2584165220 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5809552721 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5809552721 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46614997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 46614997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21574947 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 21574947 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8393717941 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8393717941 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8393717941 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8393717941 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1610349 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1610349 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1022721 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1022721 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33563 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 33563 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30573 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 30573 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2633070 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2633070 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2633070 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2633070 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114711 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.114711 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.174581 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.174581 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142687 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142687 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.137966 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.137966 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.137966 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.137966 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.255488 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.255488 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32537.764192 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32537.764192 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9733.764251 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9733.764251 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7434.509649 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7434.509649 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23105.812821 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23105.812821 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 188355 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 4054 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3483 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.014554 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 54.078381 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 72569 # number of writebacks -system.cpu1.dcache.writebacks::total 72569 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129770 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 129770 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 179212 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 179212 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 594 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 594 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 308982 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 308982 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 308982 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 308982 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79474 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 79474 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39167 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 39167 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4916 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4916 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3216 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3216 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 118641 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 118641 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 118641 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 118641 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 893939249 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 893939249 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081571527 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081571527 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37210004 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37210004 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16953500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16953500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1975510776 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1975510776 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1975510776 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1975510776 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23615501 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23615501 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 628297501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 628297501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 651913002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 651913002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044232 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044232 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.129066 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.129066 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092480 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092480 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040103 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040103 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11248.197511 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11248.197511 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27614.357163 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27614.357163 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7569.162734 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7569.162734 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5271.610697 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5271.610697 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 60866 # number of writebacks +system.cpu1.dcache.writebacks::total 60866 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 114750 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 114750 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 145883 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 145883 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 398 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 398 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 260633 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 260633 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 260633 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 260633 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69975 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 69975 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32665 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 32665 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4391 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4391 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 102640 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 102640 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 102640 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 102640 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 781048941 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 781048941 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 869596715 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 869596715 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32787753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32787753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15774053 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15774053 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1650645656 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1650645656 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1650645656 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1650645656 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18096000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18096000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 600498502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 600498502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 618594502 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 618594502 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043453 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043453 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031939 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031939 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130829 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130829 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094855 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094855 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038981 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038981 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11161.828382 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11161.828382 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26621.665850 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26621.665850 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7467.035527 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7467.035527 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5439.328621 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5439.328621 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2030,170 +2033,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6605 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 182638 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64421 40.50% 40.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.21% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 210 0.13% 41.93% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92368 58.07% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 159055 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63463 49.20% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.49% 50.80% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 210 0.16% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63253 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128982 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863089530500 97.87% 97.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64074500 0.00% 97.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 567937500 0.03% 97.90% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 100797000 0.01% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 39879064000 2.09% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903701403500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.985129 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6628 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 186556 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65870 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.19% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 193 0.12% 41.98% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 94141 58.02% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 162260 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64876 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.46% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 193 0.15% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64684 49.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 131809 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863192383000 97.84% 97.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64528500 0.00% 97.85% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 571927000 0.03% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 92721000 0.00% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 40351323000 2.12% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1904272882500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984910 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684793 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810927 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.687097 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812332 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 302 0.18% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3478 2.07% 2.26% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 152288 90.83% 93.12% # number of callpals executed -system.cpu0.kern.callpal::rdps 6536 3.90% 97.02% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rti 4500 2.68% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.21% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 167660 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7044 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches +system.cpu0.kern.callpal::wripir 275 0.16% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3568 2.09% 2.25% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed +system.cpu0.kern.callpal::swpipl 155408 90.82% 93.10% # number of callpals executed +system.cpu0.kern.callpal::rdps 6655 3.89% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4603 2.69% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 171120 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7202 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1285 -system.cpu0.kern.mode_good::user 1286 +system.cpu0.kern.mode_good::kernel 1370 +system.cpu0.kern.mode_good::user 1371 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.182425 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.190225 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.308643 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901692288000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2009107500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.319725 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1902171924000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2100950500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3479 # number of times the context was actually changed +system.cpu0.kern.swap_context 3569 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 57331 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18009 36.73% 36.73% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 3.92% 40.65% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 302 0.62% 41.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28797 58.73% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49032 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17590 47.41% 47.41% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 5.19% 52.59% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 302 0.81% 53.41% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17288 46.59% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37104 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1873168497000 98.41% 98.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531845000 0.03% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 136792000 0.01% 98.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29552054000 1.55% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903389188000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.976734 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2405 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 53020 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16452 36.11% 36.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 4.22% 40.33% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 275 0.60% 40.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 26914 59.07% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 45564 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16069 47.18% 47.18% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 5.65% 52.82% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 275 0.81% 53.63% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15794 46.37% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 34061 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1873583378500 98.41% 98.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531505500 0.03% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 123925000 0.01% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29687237000 1.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903926046000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976720 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.600340 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.756730 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.586832 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.747542 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 210 0.41% 0.42% # number of callpals executed +system.cpu1.kern.callpal::wripir 193 0.41% 0.41% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.42% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.42% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1165 2.30% 2.72% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.73% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.75% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43701 86.29% 89.04% # number of callpals executed -system.cpu1.kern.callpal::rdps 2223 4.39% 93.43% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.43% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.44% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.44% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.44% # number of callpals executed -system.cpu1.kern.callpal::rti 3104 6.13% 99.57% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.34% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1035 2.21% 2.63% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.63% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.65% # number of callpals executed +system.cpu1.kern.callpal::swpipl 40418 86.22% 88.87% # number of callpals executed +system.cpu1.kern.callpal::rdps 2100 4.48% 93.35% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.35% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 93.36% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.36% # number of callpals executed +system.cpu1.kern.callpal::rti 2947 6.29% 99.65% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.26% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 50643 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1414 # number of protection mode switches -system.cpu1.kern.mode_switch::user 459 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2447 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 685 -system.cpu1.kern.mode_good::user 459 -system.cpu1.kern.mode_good::idle 226 -system.cpu1.kern.mode_switch_good::kernel 0.484441 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 46877 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1217 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2392 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 567 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 200 +system.cpu1.kern.mode_switch_good::kernel 0.465900 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.092358 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.317130 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4654463000 0.24% 0.24% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 807268500 0.04% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1897916233000 99.71% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1166 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.083612 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.285211 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3949860500 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 686482000 0.04% 0.24% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1898967291500 99.76% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1036 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 6711c23df..59daab93c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,124 +1,124 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859220 # Number of seconds simulated -sim_ticks 1859219766000 # Number of ticks simulated -final_tick 1859219766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860201 # Number of seconds simulated +sim_ticks 1860200687500 # Number of ticks simulated +final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91264 # Simulator instruction rate (inst/s) -host_op_rate 91264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3202546943 # Simulator tick rate (ticks/s) -host_mem_usage 310256 # Number of bytes of host memory used -host_seconds 580.54 # Real time elapsed on the host -sim_insts 52982774 # Number of instructions simulated -sim_ops 52982774 # Number of ops (including micro ops) simulated +host_inst_rate 112423 # Simulator instruction rate (inst/s) +host_op_rate 112423 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3947369845 # Simulator tick rate (ticks/s) +host_mem_usage 310252 # Number of bytes of host memory used +host_seconds 471.25 # Real time elapsed on the host +sim_insts 52979577 # Number of instructions simulated +sim_ops 52979577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879296 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28495424 # Number of bytes read from this memory +system.physmem.bytes_read::total 28495552 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7515968 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515968 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388737 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388739 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445241 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13381510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1426560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15326550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4042229 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4042229 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4042229 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13381510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1426560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19368779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445241 # Total number of read requests seen -system.physmem.writeReqs 117428 # Total number of write requests seen -system.physmem.cpureqs 562841 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28495424 # Total number of bytes read from memory -system.physmem.bytesWritten 7515392 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28495424 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7515392 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27975 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28436 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27802 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27225 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27536 # Track reads on a per bank basis +system.physmem.num_reads::total 445243 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117437 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117437 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13374523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15318536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040407 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040407 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445243 # Total number of read requests seen +system.physmem.writeReqs 117437 # Total number of write requests seen +system.physmem.cpureqs 562856 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28495552 # Total number of bytes read from memory +system.physmem.bytesWritten 7515968 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 55 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27230 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27265 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27330 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28015 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27528 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28226 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28320 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7499 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7517 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6762 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6683 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7320 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8048 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7826 # Track writes on a per bank basis +system.physmem.perBankRdReqs::13 28243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28321 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7923 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7495 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7940 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7495 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6687 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6715 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7135 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6683 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7403 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7111 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7888 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8047 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7823 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1859214351000 # Total gap between requests +system.physmem.totGap 1860195209000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445241 # Categorize read packet sizes +system.physmem.readPktSize::6 445243 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117428 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 330939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1425 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117437 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 330882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3039 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -129,10 +129,10 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5104 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see @@ -141,235 +141,234 @@ system.physmem.wrQLenPdf::9 5106 # Wh system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 960.941176 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 233.799958 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2437.428145 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 12972 34.62% 34.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5555 14.83% 49.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3417 9.12% 58.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2277 6.08% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1679 4.48% 69.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1428 3.81% 72.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 991 2.64% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 802 2.14% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 632 1.69% 79.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 550 1.47% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 599 1.60% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 534 1.43% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 276 0.74% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 243 0.65% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 192 0.51% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 257 0.69% 86.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 103 0.27% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 109 0.29% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 145 0.39% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 226 0.60% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 117 0.31% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 450 1.20% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 603 1.61% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 73 0.19% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 37 0.10% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 34 0.09% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 78 0.21% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 30 0.08% 92.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 11 0.03% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 8 0.02% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 42 0.11% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 24 0.06% 92.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 2 0.01% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 19 0.05% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 6 0.02% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 4 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.00% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 2 0.01% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 2 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 2 0.01% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2434 6.50% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 3 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 955.810131 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 232.523406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2430.690638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 13031 34.59% 34.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5648 14.99% 49.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3558 9.45% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2240 5.95% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1644 4.36% 69.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1436 3.81% 73.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 989 2.63% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 804 2.13% 77.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 676 1.79% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 516 1.37% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 573 1.52% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 541 1.44% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 276 0.73% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 231 0.61% 85.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 160 0.42% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 263 0.70% 86.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 87 0.23% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 129 0.34% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 153 0.41% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 242 0.64% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 113 0.30% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 462 1.23% 89.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 590 1.57% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 81 0.22% 91.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 28 0.07% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 16 0.04% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 89 0.24% 91.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 26 0.07% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 8 0.02% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 14 0.04% 92.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 43 0.11% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 28 0.07% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 1 0.00% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 18 0.05% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 7 0.02% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 5 0.01% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 6 0.02% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.01% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.01% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 2 0.01% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 2 0.01% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 3 0.01% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 2 0.01% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 1 0.00% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.01% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 2 0.01% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.01% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 5 0.01% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2432 6.46% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 3 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 13 0.03% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 7 0.02% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 2 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17283 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37468 # Bytes accessed per row activation -system.physmem.totQLat 6065400750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13430024500 # Sum of mem lat for all requests -system.physmem.totBusLat 2225905000 # Total cycles spent in databus access -system.physmem.totBankLat 5138718750 # Total cycles spent in bank access -system.physmem.avgQLat 13624.57 # Average queueing delay per request -system.physmem.avgBankLat 11542.99 # Average bank access latency per request +system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 5 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37668 # Bytes accessed per row activation +system.physmem.totQLat 6113897250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13475242250 # Sum of mem lat for all requests +system.physmem.totBusLat 2225940000 # Total cycles spent in databus access +system.physmem.totBankLat 5135405000 # Total cycles spent in bank access +system.physmem.avgQLat 13733.29 # Average queueing delay per request +system.physmem.avgBankLat 11535.36 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30167.56 # Average memory access latency -system.physmem.avgRdBW 15.33 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 30268.66 # Average memory access latency +system.physmem.avgRdBW 15.32 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.33 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.32 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.93 # Average write queue length over time -system.physmem.readRowHits 430163 # Number of row buffer hits during reads -system.physmem.writeRowHits 94965 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes -system.physmem.avgGap 3304277.21 # Average gap between requests -system.membus.throughput 19411663 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296022 # Transaction distribution -system.membus.trans_dist::ReadResp 295937 # Transaction distribution +system.physmem.avgWrQLen 9.67 # Average write queue length over time +system.physmem.readRowHits 430049 # Number of row buffer hits during reads +system.physmem.writeRowHits 94886 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes +system.physmem.avgGap 3305955.80 # Average gap between requests +system.membus.throughput 19401806 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295958 # Transaction distribution +system.membus.trans_dist::ReadResp 295878 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117428 # Transaction distribution -system.membus.trans_dist::UpgradeReq 173 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 156790 # Transaction distribution -system.membus.trans_dist::ReadExResp 156790 # Transaction distribution -system.membus.trans_dist::BadAddressError 85 # Transaction distribution +system.membus.trans_dist::Writeback 117437 # Transaction distribution +system.membus.trans_dist::UpgradeReq 178 # Transaction distribution +system.membus.trans_dist::UpgradeResp 178 # Transaction distribution +system.membus.trans_dist::ReadExReq 156851 # Transaction distribution +system.membus.trans_dist::ReadExResp 156851 # Transaction distribution +system.membus.trans_dist::BadAddressError 80 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884153 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1008811 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042037 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1008832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745908 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36010816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36054964 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36054964 # Total data (bytes) +system.membus.tot_pkt_size::system.physmem.port 36011520 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36055668 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29876000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29849000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1541728249 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1552225748 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 108500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 97500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3763624798 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3765192546 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376221741 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.261712 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1709369770000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.261712 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078857 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078857 # Average percentage of cache occupancy +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -378,14 +377,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21342883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21342883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10471007269 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10471007269 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10492350152 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10492350152 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10492350152 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10492350152 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21345883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21345883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10482445518 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10482445518 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10503791401 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10503791401 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10503791401 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10503791401 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -402,19 +401,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123369.265896 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251997.672049 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251997.672049 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 251464.353553 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 251464.353553 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 273612 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123386.606936 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123386.606936 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252272.947584 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 252272.947584 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 251738.559641 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 251738.559641 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 274094 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27136 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27191 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.082989 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.080321 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -428,14 +427,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8309607278 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8309607278 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8321953411 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8321953411 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8321953411 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8321953411 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12348383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12348383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8320362536 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8320362536 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8332710919 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8332710919 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8332710919 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8332710919 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -444,14 +443,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199980.922170 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199980.922170 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71377.936416 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71377.936416 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200239.760685 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 200239.760685 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -465,35 +464,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13839600 # Number of BP lookups -system.cpu.branchPred.condPredicted 11609173 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399191 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9510547 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5805743 # Number of BTB hits +system.cpu.branchPred.lookups 13856452 # Number of BP lookups +system.cpu.branchPred.condPredicted 11625252 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 398822 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9666189 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5826807 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.045311 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 906368 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39168 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 60.280292 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 904750 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39047 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9923550 # DTB read hits -system.cpu.dtb.read_misses 41274 # DTB read misses -system.cpu.dtb.read_acv 543 # DTB read access violations -system.cpu.dtb.read_accesses 941562 # DTB read accesses -system.cpu.dtb.write_hits 6598688 # DTB write hits -system.cpu.dtb.write_misses 10641 # DTB write misses -system.cpu.dtb.write_acv 411 # DTB write access violations -system.cpu.dtb.write_accesses 338433 # DTB write accesses -system.cpu.dtb.data_hits 16522238 # DTB hits -system.cpu.dtb.data_misses 51915 # DTB misses -system.cpu.dtb.data_acv 954 # DTB access violations -system.cpu.dtb.data_accesses 1279995 # DTB accesses -system.cpu.itb.fetch_hits 1308614 # ITB hits -system.cpu.itb.fetch_misses 36742 # ITB misses -system.cpu.itb.fetch_acv 1058 # ITB acv -system.cpu.itb.fetch_accesses 1345356 # ITB accesses +system.cpu.dtb.read_hits 9922890 # DTB read hits +system.cpu.dtb.read_misses 41426 # DTB read misses +system.cpu.dtb.read_acv 537 # DTB read access violations +system.cpu.dtb.read_accesses 941977 # DTB read accesses +system.cpu.dtb.write_hits 6601888 # DTB write hits +system.cpu.dtb.write_misses 10414 # DTB write misses +system.cpu.dtb.write_acv 409 # DTB write access violations +system.cpu.dtb.write_accesses 338180 # DTB write accesses +system.cpu.dtb.data_hits 16524778 # DTB hits +system.cpu.dtb.data_misses 51840 # DTB misses +system.cpu.dtb.data_acv 946 # DTB access violations +system.cpu.dtb.data_accesses 1280157 # DTB accesses +system.cpu.itb.fetch_hits 1306702 # ITB hits +system.cpu.itb.fetch_misses 37996 # ITB misses +system.cpu.itb.fetch_acv 1078 # ITB acv +system.cpu.itb.fetch_accesses 1344698 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -506,268 +505,268 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 120145786 # number of cpu cycles simulated +system.cpu.numCycles 120724090 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28059248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70722559 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13839600 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6712111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13258692 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1994060 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38168658 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32286 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254324 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 364483 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8570347 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266679 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81425482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.868556 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.211321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28054756 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70765698 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13856452 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6731557 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13261846 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1996538 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38180961 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33921 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253688 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 362223 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8553305 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264520 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81438491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.868947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.211995 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68166790 83.72% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 854823 1.05% 84.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1706158 2.10% 86.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 819634 1.01% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2757548 3.39% 91.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 561946 0.69% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 649151 0.80% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1013766 1.25% 93.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4895666 6.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68176645 83.72% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 854498 1.05% 84.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1700203 2.09% 86.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 823613 1.01% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2757448 3.39% 91.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 566024 0.70% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 644448 0.79% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011541 1.24% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4904071 6.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81425482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115190 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.588640 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29284437 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37811275 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12102091 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 982484 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1245194 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 583690 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42726 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69419384 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129751 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1245194 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30419678 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14066203 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19996824 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11337239 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4360342 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65632842 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7067 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 503743 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1590486 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43821413 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79676034 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79196502 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479532 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38182467 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5638938 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682867 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239802 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12252220 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10440672 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6902467 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1316833 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 861587 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58171642 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2051698 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56802904 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 100593 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6885118 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3554028 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1390714 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81425482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697606 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359574 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81438491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.114778 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.586177 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29237679 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37865551 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12126902 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 959687 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1248671 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585551 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42601 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69445978 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129475 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1248671 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30384491 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14146796 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20012830 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11334710 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4310991 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65667162 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7173 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 505660 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1537414 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43855524 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79710296 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79230933 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479363 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38179970 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5675546 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682539 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240064 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12233478 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10440283 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6900737 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1318689 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 855517 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58206235 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050936 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56823082 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 100209 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6920159 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3549975 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1389936 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81438491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697742 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359996 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56719527 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10865996 13.34% 83.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5212450 6.40% 89.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3349939 4.11% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2634366 3.24% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1460723 1.79% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 752656 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 333424 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96401 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56732960 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10881055 13.36% 83.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5157432 6.33% 89.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3394617 4.17% 93.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2629816 3.23% 96.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1458992 1.79% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 753848 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332168 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 97603 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81425482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81438491 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 93250 11.76% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372953 47.03% 58.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326761 41.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91824 11.60% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372747 47.08% 58.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 327090 41.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38720727 68.17% 68.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61725 0.11% 68.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10357561 18.23% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6677285 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38740473 68.18% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61726 0.11% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10354642 18.22% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6680643 11.76% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949069 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56802904 # Type of FU issued -system.cpu.iq.rate 0.472783 # Inst issue rate -system.cpu.iq.fu_busy_cnt 792964 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013960 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195231977 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66785301 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55558093 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692869 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336906 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327947 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57227049 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361533 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597916 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56823082 # Type of FU issued +system.cpu.iq.rate 0.470686 # Inst issue rate +system.cpu.iq.fu_busy_cnt 791661 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013932 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195283781 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66854445 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55585028 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692743 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336682 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327940 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57245966 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361491 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598566 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1347952 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3269 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 524235 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1347977 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14180 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 522824 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17914 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 199705 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17906 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 181081 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1245194 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10207267 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 699182 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63757422 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 685568 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10440672 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6902467 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1806514 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512114 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18348 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 200766 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410779 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 611545 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56334870 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9992999 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 468033 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1248671 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10233873 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 701956 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63782733 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 684936 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10440283 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6900737 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1806230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512408 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17686 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14180 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 202063 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410564 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 612627 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56356224 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9992501 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 466857 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3534082 # number of nop insts executed -system.cpu.iew.exec_refs 16617553 # number of memory reference insts executed -system.cpu.iew.exec_branches 8923539 # Number of branches executed -system.cpu.iew.exec_stores 6624554 # Number of stores executed -system.cpu.iew.exec_rate 0.468888 # Inst execution rate -system.cpu.iew.wb_sent 55999832 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55886040 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27701007 # num instructions producing a value -system.cpu.iew.wb_consumers 37529982 # num instructions consuming a value +system.cpu.iew.exec_nop 3525562 # number of nop insts executed +system.cpu.iew.exec_refs 16620030 # number of memory reference insts executed +system.cpu.iew.exec_branches 8925380 # Number of branches executed +system.cpu.iew.exec_stores 6627529 # Number of stores executed +system.cpu.iew.exec_rate 0.466818 # Inst execution rate +system.cpu.iew.wb_sent 56027730 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55912968 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27713014 # num instructions producing a value +system.cpu.iew.wb_consumers 37524402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.465152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738103 # average fanout of values written-back +system.cpu.iew.wb_rate 0.463147 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738533 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7465540 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660984 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 567902 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80180288 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.700591 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.629829 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7495675 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661000 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 567647 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80189820 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.700468 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.629642 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59372363 74.05% 74.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8630775 10.76% 84.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4656269 5.81% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2498281 3.12% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1510890 1.88% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 609736 0.76% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 522635 0.65% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 527296 0.66% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1852043 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59377156 74.05% 74.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8657171 10.80% 84.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4615541 5.76% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2519398 3.14% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1507686 1.88% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 611065 0.76% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 523948 0.65% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 528681 0.66% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1849174 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80180288 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56173622 # Number of instructions committed -system.cpu.commit.committedOps 56173622 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80189820 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56170363 # Number of instructions committed +system.cpu.commit.committedOps 56170363 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470952 # Number of memory references committed -system.cpu.commit.loads 9092720 # Number of loads committed -system.cpu.commit.membars 226359 # Number of memory barriers committed -system.cpu.commit.branches 8440448 # Number of branches committed +system.cpu.commit.refs 15470219 # Number of memory references committed +system.cpu.commit.loads 9092306 # Number of loads committed +system.cpu.commit.membars 226376 # Number of memory barriers committed +system.cpu.commit.branches 8439998 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52023156 # Number of committed integer instructions. -system.cpu.commit.function_calls 740622 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1852043 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52019946 # Number of committed integer instructions. +system.cpu.commit.function_calls 740578 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1849174 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141717845 # The number of ROB reads -system.cpu.rob.rob_writes 128525319 # The number of ROB writes -system.cpu.timesIdled 1192872 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38720304 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598287306 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52982774 # Number of Instructions Simulated -system.cpu.committedOps 52982774 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52982774 # Number of Instructions Simulated -system.cpu.cpi 2.267639 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.267639 # CPI: Total CPI of All Threads -system.cpu.ipc 0.440987 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.440987 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73877727 # number of integer regfile reads -system.cpu.int_regfile_writes 40299404 # number of integer regfile writes -system.cpu.fp_regfile_reads 166073 # number of floating regfile reads -system.cpu.fp_regfile_writes 167447 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985193 # number of misc regfile reads +system.cpu.rob.rob_reads 141757103 # The number of ROB reads +system.cpu.rob.rob_writes 128582546 # The number of ROB writes +system.cpu.timesIdled 1193264 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 39285599 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599670846 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979577 # Number of Instructions Simulated +system.cpu.committedOps 52979577 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52979577 # Number of Instructions Simulated +system.cpu.cpi 2.278691 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.278691 # CPI: Total CPI of All Threads +system.cpu.ipc 0.438848 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.438848 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73899188 # number of integer regfile reads +system.cpu.int_regfile_writes 40322867 # number of integer regfile writes +system.cpu.fp_regfile_reads 166085 # number of floating regfile reads +system.cpu.fp_regfile_writes 167427 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985758 # number of misc regfile reads system.cpu.misc_regfile_writes 938984 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -800,7 +799,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1455318 # Throughput (bytes/s) +system.iobus.throughput 1454551 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51150 # Transaction distribution @@ -886,233 +885,225 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378262152 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 378268160 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43098759 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 112025274 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2118762 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2118660 # Transaction distribution +system.cpu.toL2Bus.throughput 111927083 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2117675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2117578 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840831 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 68 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020715 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3678751 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 5699466 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64659008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143612852 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 208271860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208261812 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17792 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2480878498 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2019865 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3677460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 5697325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64631872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143567348 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 208199220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1516366019 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1518735644 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2115023448 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.replacements 1009685 # number of replacements -system.cpu.icache.tagsinuse 509.751691 # Cycle average of tags in use -system.cpu.icache.total_refs 7503411 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1010193 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.427700 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 25536785000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.751691 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.995609 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.995609 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7503412 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7503412 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7503412 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7503412 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7503412 # number of overall hits -system.cpu.icache.overall_hits::total 7503412 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1066934 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1066934 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1066934 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1066934 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1066934 # number of overall misses -system.cpu.icache.overall_misses::total 1066934 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15003433992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15003433992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15003433992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15003433992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15003433992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15003433992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8570346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8570346 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69058.140169 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69058.140169 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1202,161 +1185,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1401615 # number of replacements -system.cpu.dcache.tagsinuse 511.994565 # Cycle average of tags in use -system.cpu.dcache.total_refs 11806786 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1402127 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.420625 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25214000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994565 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7200855 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7200855 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4204221 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4204221 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 185946 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 185946 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215517 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215517 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247335 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247335 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247335 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247335 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21903.622225 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21903.622225 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38964.588594 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38964.588594 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14152.848602 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14152.848602 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30752.145439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30752.145439 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2955693 # number of cycles access was blocked +system.cpu.dcache.tags.replacements 1401048 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203713 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186169 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186169 # 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number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3750803 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3750803 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3750803 # number of overall misses +system.cpu.dcache.overall_misses::total 3750803 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39803546178 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39803546178 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76325479834 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76325479834 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321955499 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 321955499 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 116129026012 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 116129026012 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 116129026012 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 116129026012 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9009292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9009292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208876 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208876 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215522 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215522 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15156980 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15156980 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15156980 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15156980 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200552 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200552 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316212 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316212 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108710 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108710 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247464 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247464 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247464 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247464 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22029.515913 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22029.515913 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39262.583024 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39262.583024 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14178.689347 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14178.689347 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30961.110464 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30961.110464 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2958985 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 101444 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 97398 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.136203 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.380347 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840976 # number of writebacks -system.cpu.dcache.writebacks::total 840976 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719736 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 719736 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643409 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1643409 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5171 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5171 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2363145 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2363145 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2363145 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2363145 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084321 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084321 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300378 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300378 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17577 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17577 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384699 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384699 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384699 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384699 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26518641540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26518641540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11550001786 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11550001786 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 202636005 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 202636005 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 57000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 57000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38068643326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38068643326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38068643326 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38068643326 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424047000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424047000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997793498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997793498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421840498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421840498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120414 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120414 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048858 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048858 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084224 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084224 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091382 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091382 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24456.449280 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24456.449280 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38451.556992 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38451.556992 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11528.474996 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11528.474996 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840831 # number of writebacks +system.cpu.dcache.writebacks::total 840831 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 723109 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 723109 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5191 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5191 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2366614 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2366614 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2366614 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2366614 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083719 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083719 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300470 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300470 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17516 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17516 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384189 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384189 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384189 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384189 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26582228002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26582228002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11613303338 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11613303338 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201814751 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201814751 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38195531340 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38195531340 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38195531340 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38195531340 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424015000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424015000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997805998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997805998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421820998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421820998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048875 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048875 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083858 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083858 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091324 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091324 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24528.709012 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24528.709012 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38650.458741 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38650.458741 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11521.737326 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11521.737326 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1365,28 +1348,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182247 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817988566000 97.78% 97.78% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64092000 0.00% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554660500 0.03% 97.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 40611610500 2.18% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859218929000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818706968000 97.77% 97.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64176500 0.00% 97.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 554827000 0.03% 97.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 40873882000 2.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860199853500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694268 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815393 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1425,8 +1408,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175130 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed @@ -1436,18 +1419,18 @@ system.cpu.kern.callpal::callsys 515 0.27% 99.91% # nu system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.callpal::total 191976 # number of callpals executed system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326328 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326158 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29661883000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2771562000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826785476000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29671097000 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2774842500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827753906000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 936d08062..feb99cd9c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842698 # Number of seconds simulated -sim_ticks 1842697801000 # Number of ticks simulated -final_tick 1842697801000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842705 # Number of seconds simulated +sim_ticks 1842705252000 # Number of ticks simulated +final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215096 # Simulator instruction rate (inst/s) -host_op_rate 215096 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5452418287 # Simulator tick rate (ticks/s) -host_mem_usage 309280 # Number of bytes of host memory used -host_seconds 337.96 # Real time elapsed on the host -sim_insts 72693799 # Number of instructions simulated -sim_ops 72693799 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 487424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20019264 # Number of bytes read from this memory +host_inst_rate 221595 # Simulator instruction rate (inst/s) +host_op_rate 221595 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5621199023 # Simulator tick rate (ticks/s) +host_mem_usage 308252 # Number of bytes of host memory used +host_seconds 327.81 # Real time elapsed on the host +sim_insts 72641883 # Number of instructions simulated +sim_ops 72641883 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20049216 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2316480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 282624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2529216 # Number of bytes read from this memory -system.physmem.bytes_read::total 28435264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 487424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 282624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 917952 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2290432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 282112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2525760 # Number of bytes read from this memory +system.physmem.bytes_read::total 28435648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 282112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 917888 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7459584 # Number of bytes written to this memory system.physmem.bytes_written::total 7459584 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 312801 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313269 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2311 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 36195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39519 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2302 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 35788 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39465 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444307 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 116556 # Number of write requests responded to by this memory system.physmem.num_writes::total 116556 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 264517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10864106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1257113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 153375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1372561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15431322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 264517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 153375 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498157 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 264517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10864106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1257113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 153375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1372561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19479509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 99716 # Total number of read requests seen -system.physmem.writeReqs 44920 # Total number of write requests seen -system.physmem.cpureqs 144680 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 6381824 # Total number of bytes read from memory -system.physmem.bytesWritten 2874880 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6381824 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2874880 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_read::cpu0.inst 265071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10880316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1242973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 153097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1370680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15431468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79952 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 153097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498120 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 265071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10880316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1242973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 153097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1370680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19479638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 99238 # Total number of read requests seen +system.physmem.writeReqs 44800 # Total number of write requests seen +system.physmem.cpureqs 144082 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 6351232 # Total number of bytes read from memory +system.physmem.bytesWritten 2867200 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6351232 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2867200 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6258 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 6232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6043 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6348 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 5767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6492 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6415 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 6657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6017 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6146 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2882 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2846 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2624 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 3004 # Track writes on a per bank basis +system.physmem.perBankRdReqs::5 6398 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6152 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6059 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 6626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5967 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6045 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2861 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2670 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2847 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 3000 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 2942 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2707 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3022 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2472 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2709 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2853 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2760 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2703 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2742 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2468 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2705 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2852 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2761 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1841685476500 # Total gap between requests +system.physmem.totGap 1841692926500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 99716 # Categorize read packet sizes +system.physmem.readPktSize::6 99238 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 44920 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 68031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 42 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44800 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 67489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -148,369 +148,367 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 15781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 586.280717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.240853 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1929.214074 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 6626 41.99% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 2550 16.16% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 1431 9.07% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 896 5.68% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 638 4.04% 76.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 562 3.56% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 391 2.48% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 301 1.91% 84.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 260 1.65% 86.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 205 1.30% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 214 1.36% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 213 1.35% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 77 0.49% 91.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 70 0.44% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 80 0.51% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 90 0.57% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 36 0.23% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 39 0.25% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 57 0.36% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 48 0.30% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 35 0.22% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 177 1.12% 95.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 87 0.55% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 34 0.22% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 15760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 584.832487 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.909397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1926.760563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 6603 41.90% 41.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 2572 16.32% 58.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 1454 9.23% 67.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 899 5.70% 73.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 642 4.07% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 535 3.39% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 370 2.35% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 312 1.98% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 250 1.59% 86.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 195 1.24% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 235 1.49% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 190 1.21% 90.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 101 0.64% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 71 0.45% 91.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 63 0.40% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 80 0.51% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 51 0.32% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 28 0.18% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 74 0.47% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 51 0.32% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 34 0.22% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 173 1.10% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 86 0.55% 95.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 27 0.17% 95.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::1664-1667 14 0.09% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 7 0.04% 96.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 18 0.11% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 14 0.09% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 8 0.05% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 12 0.08% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 22 0.14% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 10 0.06% 96.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 4 0.03% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::2048-2051 6 0.04% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 6 0.04% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 4 0.03% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 1 0.01% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.01% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 2 0.01% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 1 0.01% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 1 0.01% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.01% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 7 0.04% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 1 0.01% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 3 0.02% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 2 0.01% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 1 0.01% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 2 0.01% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 1 0.01% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 1 0.01% 96.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::3584-3587 1 0.01% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 1 0.01% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.01% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.01% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.01% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.01% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.01% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.01% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.01% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 2 0.01% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 2 0.01% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.01% 96.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7811 1 0.01% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 384 2.43% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 8 0.05% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 383 2.43% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 1 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 6 0.04% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.01% 99.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::16384-16387 111 0.70% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::16448-16451 1 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 1 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 2 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::16832-16835 1 0.01% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::17088-17091 1 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 15781 # Bytes accessed per row activation -system.physmem.totQLat 1934459750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3605914750 # Sum of mem lat for all requests -system.physmem.totBusLat 498525000 # Total cycles spent in databus access -system.physmem.totBankLat 1172930000 # Total cycles spent in bank access -system.physmem.avgQLat 19401.83 # Average queueing delay per request -system.physmem.avgBankLat 11764.00 # Average bank access latency per request +system.physmem.bytesPerActivate::total 15760 # Bytes accessed per row activation +system.physmem.totQLat 1910826000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3572864750 # Sum of mem lat for all requests +system.physmem.totBusLat 496135000 # Total cycles spent in databus access +system.physmem.totBankLat 1165903750 # Total cycles spent in bank access +system.physmem.avgQLat 19257.12 # Average queueing delay per request +system.physmem.avgBankLat 11749.86 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 36165.84 # Average memory access latency -system.physmem.avgRdBW 3.46 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 36006.98 # Average memory access latency +system.physmem.avgRdBW 3.45 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.46 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.45 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.17 # Average write queue length over time -system.physmem.readRowHits 93388 # Number of row buffer hits during reads -system.physmem.writeRowHits 35434 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.88 # Row buffer hit rate for writes -system.physmem.avgGap 12733243.98 # Average gap between requests -system.membus.throughput 19523449 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46002 # Transaction distribution -system.membus.trans_dist::ReadResp 45972 # Transaction distribution -system.membus.trans_dist::WriteReq 3749 # Transaction distribution -system.membus.trans_dist::WriteResp 3749 # Transaction distribution -system.membus.trans_dist::Writeback 44920 # Transaction distribution +system.physmem.readRowHits 92920 # Number of row buffer hits during reads +system.physmem.writeRowHits 35346 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.64 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.90 # Row buffer hit rate for writes +system.physmem.avgGap 12786160.09 # Average gap between requests +system.membus.throughput 19523578 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 45592 # Transaction distribution +system.membus.trans_dist::ReadResp 45560 # Transaction distribution +system.membus.trans_dist::WriteReq 3756 # Transaction distribution +system.membus.trans_dist::WriteResp 3756 # Transaction distribution +system.membus.trans_dist::Writeback 44800 # Transaction distribution system.membus.trans_dist::UpgradeReq 46 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 47 # Transaction distribution -system.membus.trans_dist::ReadExReq 56809 # Transaction distribution -system.membus.trans_dist::ReadExResp 56809 # Transaction distribution -system.membus.trans_dist::BadAddressError 30 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13314 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 192737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 206111 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51863 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 51863 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 13314 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 244600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 257974 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7047808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 7063555 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2208896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 9256704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9272451 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35965768 # Total data (bytes) -system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12475000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadExReq 56741 # Transaction distribution +system.membus.trans_dist::ReadExResp 56741 # Transaction distribution +system.membus.trans_dist::BadAddressError 32 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 191660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 205046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51865 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 51865 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 13322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 243525 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 256911 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7009472 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 7025226 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2208960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 9218432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9234186 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35966088 # Total data (bytes) +system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12465000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 520545500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 516080000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 35000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 39000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 777595953 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 771793954 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 156419750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 156435750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.replacements 337378 # number of replacements -system.l2c.tagsinuse 65422.722236 # Cycle average of tags in use -system.l2c.total_refs 2472063 # Total number of references to valid blocks. -system.l2c.sampled_refs 402541 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.141146 # Average number of references to valid blocks. -system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 54907.432737 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2460.754948 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2679.156770 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 579.419963 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 590.394247 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2099.377178 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 2106.186392 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.837821 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.037548 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.040881 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.008841 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.009009 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.032034 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.032138 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.998272 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 520270 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493307 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124051 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83977 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 292923 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 239241 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1753769 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835411 # number of Writeback hits -system.l2c.Writeback_hits::total 835411 # number of Writeback hits +system.l2c.tags.replacements 337384 # number of replacements +system.l2c.tags.tagsinuse 65423.390976 # Cycle average of tags in use +system.l2c.tags.total_refs 2471195 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402547 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.138898 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 54840.022307 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2455.785986 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2733.317890 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 573.564095 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 593.217562 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2104.783507 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2122.699630 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.836792 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.037472 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008752 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009052 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245249 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014809 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.114152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035044 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 53021.494385 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 52319.180833 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 55678.889927 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23728 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23728 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 52882.386480 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71118.606859 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62506.162049 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69139.659022 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52766.589659 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73945.878623 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62303.576116 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58932.120503 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69139.659022 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52766.589659 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73945.878623 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62303.576116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58932.120503 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 52973.119058 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69247.635118 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61636.983112 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52996.560876 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61314.775248 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58544.707135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52996.560876 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61314.775248 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58544.707135 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -628,15 +626,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.254871 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1694871315000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.254871 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078429 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078429 # Average percentage of cache occupancy +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.254957 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254957 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078435 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078435 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -645,14 +643,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9512963 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9512963 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4344125507 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4344125507 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4353638470 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4353638470 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4353638470 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4353638470 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9629212 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9629212 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 4353407559 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4353407559 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4363036771 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4363036771 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4363036771 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4363036771 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -669,56 +667,56 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54988.225434 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54988.225434 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104546.724755 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 104546.724755 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 104341.245536 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 104341.245536 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 113861 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55660.184971 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 55660.184971 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104770.108755 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 104770.108755 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 104566.489419 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 104566.489419 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 104566.489419 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 104566.489419 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 114649 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11412 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11461 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.977305 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.003403 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17349 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17349 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17349 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 17349 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5924213 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5924213 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3445287507 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3445287507 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3451211720 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3451211720 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3451211720 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3451211720 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_misses::tsunami.ide 17350 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 17350 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 17350 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 17350 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5987712 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5987712 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3454277559 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3454277559 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3460265271 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3460265271 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3460265271 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3460265271 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.415794 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85858.159420 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 85858.159420 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199380.064062 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199380.064062 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.415818 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.415818 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85538.742857 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 85538.742857 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199900.321701 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199900.321701 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199438.920519 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 199438.920519 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199438.920519 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 199438.920519 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -736,22 +734,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4916475 # DTB read hits -system.cpu0.dtb.read_misses 6063 # DTB read misses +system.cpu0.dtb.read_hits 4909978 # DTB read hits +system.cpu0.dtb.read_misses 6100 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 427415 # DTB read accesses -system.cpu0.dtb.write_hits 3510632 # DTB write hits -system.cpu0.dtb.write_misses 668 # DTB write misses +system.cpu0.dtb.read_accesses 428319 # DTB read accesses +system.cpu0.dtb.write_hits 3504299 # DTB write hits +system.cpu0.dtb.write_misses 671 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 162993 # DTB write accesses -system.cpu0.dtb.data_hits 8427107 # DTB hits -system.cpu0.dtb.data_misses 6731 # DTB misses +system.cpu0.dtb.write_accesses 163761 # DTB write accesses +system.cpu0.dtb.data_hits 8414277 # DTB hits +system.cpu0.dtb.data_misses 6771 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 590408 # DTB accesses -system.cpu0.itb.fetch_hits 2754785 # ITB hits -system.cpu0.itb.fetch_misses 3015 # ITB misses +system.cpu0.dtb.data_accesses 592080 # DTB accesses +system.cpu0.itb.fetch_hits 2758234 # ITB hits +system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2757800 # ITB accesses +system.cpu0.itb.fetch_accesses 2761268 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -764,51 +762,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928378822 # number of cpu cycles simulated +system.cpu0.numCycles 928316891 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33851772 # Number of instructions committed -system.cpu0.committedOps 33851772 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31712153 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169925 # Number of float alu accesses -system.cpu0.num_func_calls 812668 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4695347 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31712153 # number of integer instructions -system.cpu0.num_fp_insts 169925 # number of float instructions -system.cpu0.num_int_register_reads 44553309 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23136473 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87700 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89305 # number of times the floating registers were written -system.cpu0.num_mem_refs 8457205 # number of memory refs -system.cpu0.num_load_insts 4937806 # Number of load instructions -system.cpu0.num_store_insts 3519399 # Number of store instructions -system.cpu0.num_idle_cycles 213007832176.448029 # Number of idle cycles -system.cpu0.num_busy_cycles -212079453354.448029 # Number of busy cycles -system.cpu0.not_idle_fraction -228.440641 # Percentage of non-idle cycles -system.cpu0.idle_fraction 229.440641 # Percentage of idle cycles +system.cpu0.committedInsts 33736461 # Number of instructions committed +system.cpu0.committedOps 33736461 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31599588 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169686 # Number of float alu accesses +system.cpu0.num_func_calls 810809 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4665593 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31599588 # number of integer instructions +system.cpu0.num_fp_insts 169686 # number of float instructions +system.cpu0.num_int_register_reads 44374544 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23060255 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87629 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89168 # number of times the floating registers were written +system.cpu0.num_mem_refs 8444409 # number of memory refs +system.cpu0.num_load_insts 4931349 # Number of load instructions +system.cpu0.num_store_insts 3513060 # Number of store instructions +system.cpu0.num_idle_cycles 212988700365.392029 # Number of idle cycles +system.cpu0.num_busy_cycles -212060383474.392029 # Number of busy cycles +system.cpu0.not_idle_fraction -228.435339 # Percentage of non-idle cycles +system.cpu0.idle_fraction 229.435339 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211396 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105698 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182586 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819523663000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39251000 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365640000 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22768477500 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842697031500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819515680500 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39349500 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365678500 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22783774000 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842704482500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694800 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815835 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -844,10 +842,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175327 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -856,21 +854,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192238 # number of callpals executed +system.cpu0.kern.callpal::total 192242 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1738 -system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.321965 # fraction of useful protection mode switches +system.cpu0.kern.mode_good::idle 170 +system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29806042000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2607375500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810283609500 98.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4175 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29786026000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2614250500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810304201500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -902,73 +900,73 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110454960 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 786209 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 786164 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 371427 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150852 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133572 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 847417 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1371009 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 2218426 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27116864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55346243 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 82463107 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203524040 # Total data (bytes) +system.toL2Bus.throughput 110422039 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 786602 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 786555 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3756 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3756 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 371447 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 15 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 151061 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133781 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 32 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 849315 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1370344 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 2219659 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27177600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55325386 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 82502986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203464200 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2135036000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 2135432500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1907460021 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1913139810 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2223763109 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2237602233 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469142 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 2977 # Transaction distribution -system.iobus.trans_dist::ReadResp 2977 # Transaction distribution -system.iobus.trans_dist::WriteReq 21029 # Transaction distribution -system.iobus.trans_dist::WriteResp 21029 # Transaction distribution +system.iobus.throughput 1469136 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2975 # Transaction distribution +system.iobus.trans_dist::ReadResp 2975 # Transaction distribution +system.iobus.trans_dist::WriteReq 21036 # Transaction distribution +system.iobus.trans_dist::WriteResp 21036 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13314 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13322 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 48012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 48022 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15747 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15754 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1123115 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1123130 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2707184 # Total data (bytes) system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -976,384 +974,384 @@ system.iobus.reqLayer1.occupancy 105000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6219000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6200000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1797000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1827000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 157278470 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 157303021 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9565000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9566000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17530000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17990250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.replacements 950939 # number of replacements -system.cpu0.icache.tagsinuse 511.192426 # Cycle average of tags in use -system.cpu0.icache.total_refs 43369559 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 951450 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 45.582594 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10375508000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 249.451681 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 99.242283 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 162.498462 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.487210 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.193833 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.317380 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998423 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 33330806 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7798498 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2240255 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43369559 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 33330806 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7798498 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2240255 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43369559 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 33330806 # 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average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12348.272007 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12347.049089 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12348.272007 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12347.049089 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.272007 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1391818 # 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miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.313167 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.130687 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076572 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100373 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.125616 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092233 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108700 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069824 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233430 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10380870896 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3576805741 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6804065155 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10380870896 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 294283500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312003000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 606286500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 361937500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429433000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791370500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 656221000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 741436000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397657000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083444 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086144 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039451 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051014 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046894 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098681 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037292 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000039 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069604 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070775 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032215 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069604 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070775 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032215 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20778.830992 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16781.975276 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17906.452539 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33786.197965 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 28952.712667 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30582.187614 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11200.692841 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12344.669813 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12017.408959 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16999.500000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24847.038554 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19939.470498 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21395.519882 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24847.038554 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19939.470498 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21395.519882 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1368,22 +1366,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1206143 # DTB read hits -system.cpu1.dtb.read_misses 1395 # DTB read misses -system.cpu1.dtb.read_acv 35 # DTB read access violations -system.cpu1.dtb.read_accesses 142828 # DTB read accesses -system.cpu1.dtb.write_hits 904590 # DTB write hits -system.cpu1.dtb.write_misses 190 # DTB write misses +system.cpu1.dtb.read_hits 1205047 # DTB read hits +system.cpu1.dtb.read_misses 1367 # DTB read misses +system.cpu1.dtb.read_acv 34 # DTB read access violations +system.cpu1.dtb.read_accesses 142944 # DTB read accesses +system.cpu1.dtb.write_hits 904403 # DTB write hits +system.cpu1.dtb.write_misses 185 # DTB write misses system.cpu1.dtb.write_acv 23 # DTB write access violations -system.cpu1.dtb.write_accesses 58592 # DTB write accesses -system.cpu1.dtb.data_hits 2110733 # DTB hits -system.cpu1.dtb.data_misses 1585 # DTB misses -system.cpu1.dtb.data_acv 58 # DTB access violations -system.cpu1.dtb.data_accesses 201420 # DTB accesses -system.cpu1.itb.fetch_hits 862559 # ITB hits -system.cpu1.itb.fetch_misses 707 # ITB misses -system.cpu1.itb.fetch_acv 34 # ITB acv -system.cpu1.itb.fetch_accesses 863266 # ITB accesses +system.cpu1.dtb.write_accesses 58533 # DTB write accesses +system.cpu1.dtb.data_hits 2109450 # DTB hits +system.cpu1.dtb.data_misses 1552 # DTB misses +system.cpu1.dtb.data_acv 57 # DTB access violations +system.cpu1.dtb.data_accesses 201477 # DTB accesses +system.cpu1.itb.fetch_hits 861634 # ITB hits +system.cpu1.itb.fetch_misses 693 # ITB misses +system.cpu1.itb.fetch_acv 30 # ITB acv +system.cpu1.itb.fetch_accesses 862327 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1396,28 +1394,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953614983 # number of cpu cycles simulated +system.cpu1.numCycles 953630418 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7923216 # Number of instructions committed -system.cpu1.committedOps 7923216 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7378774 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44696 # Number of float alu accesses -system.cpu1.num_func_calls 212761 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1003934 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7378774 # number of integer instructions -system.cpu1.num_fp_insts 44696 # number of float instructions -system.cpu1.num_int_register_reads 10322317 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5366754 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24140 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24473 # number of times the floating registers were written -system.cpu1.num_mem_refs 2118035 # number of memory refs -system.cpu1.num_load_insts 1211092 # Number of load instructions -system.cpu1.num_store_insts 906943 # Number of store instructions -system.cpu1.num_idle_cycles -710985323.015638 # Number of idle cycles -system.cpu1.num_busy_cycles 1664600306.015638 # Number of busy cycles -system.cpu1.not_idle_fraction 1.745569 # Percentage of non-idle cycles -system.cpu1.idle_fraction -0.745569 # Percentage of idle cycles +system.cpu1.committedInsts 7889245 # Number of instructions committed +system.cpu1.committedOps 7889245 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7344952 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44937 # Number of float alu accesses +system.cpu1.num_func_calls 213049 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 993802 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7344952 # number of integer instructions +system.cpu1.num_fp_insts 44937 # number of float instructions +system.cpu1.num_int_register_reads 10269748 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5343251 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24271 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24577 # number of times the floating registers were written +system.cpu1.num_mem_refs 2116682 # number of memory refs +system.cpu1.num_load_insts 1209934 # Number of load instructions +system.cpu1.num_store_insts 906748 # Number of store instructions +system.cpu1.num_idle_cycles -715527638.238183 # Number of idle cycles +system.cpu1.num_busy_cycles 1669158056.238183 # Number of busy cycles +system.cpu1.not_idle_fraction 1.750320 # Percentage of non-idle cycles +system.cpu1.idle_fraction -0.750320 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1435,35 +1433,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8997247 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8318296 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 124435 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7453298 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6389224 # Number of BTB hits +system.cpu2.branchPred.lookups 9022316 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8342315 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 122648 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7529449 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6410701 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.723448 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 282371 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 13443 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.141702 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 283187 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 12478 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3184667 # DTB read hits -system.cpu2.dtb.read_misses 11563 # DTB read misses -system.cpu2.dtb.read_acv 122 # DTB read access violations -system.cpu2.dtb.read_accesses 218108 # DTB read accesses -system.cpu2.dtb.write_hits 2003168 # DTB write hits -system.cpu2.dtb.write_misses 2582 # DTB write misses -system.cpu2.dtb.write_acv 105 # DTB write access violations -system.cpu2.dtb.write_accesses 82984 # DTB write accesses -system.cpu2.dtb.data_hits 5187835 # DTB hits -system.cpu2.dtb.data_misses 14145 # DTB misses +system.cpu2.dtb.read_hits 3192037 # DTB read hits +system.cpu2.dtb.read_misses 11608 # DTB read misses +system.cpu2.dtb.read_acv 121 # DTB read access violations +system.cpu2.dtb.read_accesses 216573 # DTB read accesses +system.cpu2.dtb.write_hits 2009173 # DTB write hits +system.cpu2.dtb.write_misses 2522 # DTB write misses +system.cpu2.dtb.write_acv 106 # DTB write access violations +system.cpu2.dtb.write_accesses 81978 # DTB write accesses +system.cpu2.dtb.data_hits 5201210 # DTB hits +system.cpu2.dtb.data_misses 14130 # DTB misses system.cpu2.dtb.data_acv 227 # DTB access violations -system.cpu2.dtb.data_accesses 301092 # DTB accesses -system.cpu2.itb.fetch_hits 370432 # ITB hits -system.cpu2.itb.fetch_misses 5697 # ITB misses -system.cpu2.itb.fetch_acv 245 # ITB acv -system.cpu2.itb.fetch_accesses 376129 # ITB accesses +system.cpu2.dtb.data_accesses 298551 # DTB accesses +system.cpu2.itb.fetch_hits 369667 # ITB hits +system.cpu2.itb.fetch_misses 5681 # ITB misses +system.cpu2.itb.fetch_acv 262 # ITB acv +system.cpu2.itb.fetch_accesses 375348 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1476,270 +1474,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31194709 # number of cpu cycles simulated +system.cpu2.numCycles 31245078 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8336463 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 36595534 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8997247 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6671595 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8714180 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 607609 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9678498 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 11323 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1980 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 64467 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 86613 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2554168 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 86055 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27288913 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.341040 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.295561 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8348883 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 36663716 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9022316 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6693888 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8736568 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 602984 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9694630 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 11222 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1957 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63711 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 86195 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 437 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2553880 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 85053 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27335965 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.341226 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.294449 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18574733 68.07% 68.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 269160 0.99% 69.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 428961 1.57% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4866915 17.83% 88.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 754326 2.76% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 165422 0.61% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 191254 0.70% 92.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 429367 1.57% 94.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1608775 5.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18599397 68.04% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 269863 0.99% 69.03% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 429102 1.57% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4885317 17.87% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 756803 2.77% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 166340 0.61% 91.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 191609 0.70% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 429140 1.57% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1608394 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27288913 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288422 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.173133 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8484758 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9763089 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8105885 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 306526 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 382761 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165822 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12764 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36197990 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39851 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 382761 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8844170 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2798398 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5770090 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7975185 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1272419 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35047656 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 232046 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 447152 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23489226 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 43822690 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43659490 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 163200 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21694214 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1795012 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 501276 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59320 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3724979 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3343402 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2093050 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 368261 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 257932 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32557394 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 620599 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32107794 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 34091 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2143269 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1080696 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 438167 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27288913 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.176588 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.573888 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27335965 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288760 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.173424 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8495766 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9778515 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8128034 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 307242 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 380496 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165135 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12538 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36269918 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39153 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 380496 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8853799 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2797423 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5789351 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7998658 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1270334 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35131949 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2438 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 231189 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 444117 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23541427 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 43931372 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43768405 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 162967 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21760313 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1781114 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 501831 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59191 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3719256 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3350609 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2097879 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 369762 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 260934 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32641753 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 622044 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32196803 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 34835 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2138258 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1073109 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 438824 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27335965 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.177818 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.573987 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15150790 55.52% 55.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3070151 11.25% 66.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1548988 5.68% 72.45% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5689584 20.85% 93.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 903005 3.31% 96.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 480338 1.76% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 283929 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 143393 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18735 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15167963 55.49% 55.49% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3067850 11.22% 66.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1557003 5.70% 72.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5712284 20.90% 93.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 903378 3.30% 96.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 480833 1.76% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 285081 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 142652 0.52% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18921 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27288913 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27335965 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33803 13.75% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 111727 45.45% 59.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100297 40.80% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33684 13.60% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 113022 45.64% 59.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100957 40.76% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26449669 82.38% 82.39% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20147 0.06% 82.45% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8446 0.03% 82.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3312033 10.32% 92.79% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2025467 6.31% 99.10% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 288360 0.90% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26526068 82.39% 82.39% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20082 0.06% 82.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8432 0.03% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3318552 10.31% 92.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2030927 6.31% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 289082 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32107794 # Type of FU issued -system.cpu2.iq.rate 1.029271 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 245827 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 91550157 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35210267 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 31710626 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234262 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114809 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110859 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32229265 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 121908 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 186278 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32196803 # Type of FU issued +system.cpu2.iq.rate 1.030460 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 247663 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007692 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 91777621 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35291242 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 31803164 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234448 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114643 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110912 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32319915 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 122111 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 186470 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 409987 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1098 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3916 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 156672 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 409308 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1087 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 154806 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4171 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 28368 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4179 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 28515 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 382761 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2017515 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 205037 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34446466 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224960 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3343402 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2093050 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 551127 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 142834 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3916 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63764 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127616 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 191380 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 31948816 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3204490 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 158978 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 380496 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2018433 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 205280 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34533473 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 223572 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3350609 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2097879 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 552418 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 143005 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2030 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3940 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 62474 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127218 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 189692 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32041792 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3211958 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 155011 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1268473 # number of nop insts executed -system.cpu2.iew.exec_refs 5214665 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7427208 # Number of branches executed -system.cpu2.iew.exec_stores 2010175 # Number of stores executed -system.cpu2.iew.exec_rate 1.024174 # Inst execution rate -system.cpu2.iew.wb_sent 31853816 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 31821485 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18500784 # num instructions producing a value -system.cpu2.iew.wb_consumers 21694431 # num instructions consuming a value +system.cpu2.iew.exec_nop 1269676 # number of nop insts executed +system.cpu2.iew.exec_refs 5228104 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7451179 # Number of branches executed +system.cpu2.iew.exec_stores 2016146 # Number of stores executed +system.cpu2.iew.exec_rate 1.025499 # Inst execution rate +system.cpu2.iew.wb_sent 31946323 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 31914076 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18560539 # num instructions producing a value +system.cpu2.iew.wb_consumers 21756623 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.020092 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.852790 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.021411 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.853098 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2318994 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 182432 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 176935 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26906152 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.192355 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846387 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2307107 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 183220 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 175579 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26955469 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.193861 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.846623 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16157542 60.05% 60.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2331595 8.67% 68.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1218913 4.53% 73.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5433463 20.19% 93.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 503772 1.87% 95.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 185469 0.69% 96.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 177448 0.66% 96.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 178843 0.66% 97.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 719107 2.67% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16175286 60.01% 60.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2330504 8.65% 68.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1226068 4.55% 73.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5456953 20.24% 93.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 503178 1.87% 95.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186113 0.69% 96.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 177622 0.66% 96.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 179384 0.67% 97.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 720361 2.67% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26906152 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32081688 # Number of instructions committed -system.cpu2.commit.committedOps 32081688 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26955469 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32181084 # Number of instructions committed +system.cpu2.commit.committedOps 32181084 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4869793 # Number of memory references committed -system.cpu2.commit.loads 2933415 # Number of loads committed -system.cpu2.commit.membars 63859 # Number of memory barriers committed -system.cpu2.commit.branches 7280639 # Number of branches committed -system.cpu2.commit.fp_insts 109636 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30638732 # Number of committed integer instructions. -system.cpu2.commit.function_calls 228563 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 719107 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4884374 # Number of memory references committed +system.cpu2.commit.loads 2941301 # Number of loads committed +system.cpu2.commit.membars 64148 # Number of memory barriers committed +system.cpu2.commit.branches 7305681 # Number of branches committed +system.cpu2.commit.fp_insts 109768 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30735120 # Number of committed integer instructions. +system.cpu2.commit.function_calls 229363 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 720361 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 60513787 # The number of ROB reads -system.cpu2.rob.rob_writes 69183653 # The number of ROB writes -system.cpu2.timesIdled 245794 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3905796 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746583104 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 30918811 # Number of Instructions Simulated -system.cpu2.committedOps 30918811 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 30918811 # Number of Instructions Simulated -system.cpu2.cpi 1.008923 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.008923 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.991156 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.991156 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42017360 # number of integer regfile reads -system.cpu2.int_regfile_writes 22376128 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67819 # number of floating regfile reads -system.cpu2.fp_regfile_writes 67985 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5215792 # number of misc regfile reads -system.cpu2.misc_regfile_writes 257331 # number of misc regfile writes +system.cpu2.rob.rob_reads 60649307 # The number of ROB reads +system.cpu2.rob.rob_writes 69356385 # The number of ROB writes +system.cpu2.timesIdled 245741 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3909113 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746532644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31016177 # Number of Instructions Simulated +system.cpu2.committedOps 31016177 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31016177 # Number of Instructions Simulated +system.cpu2.cpi 1.007380 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.007380 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.992674 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.992674 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42141472 # number of integer regfile reads +system.cpu2.int_regfile_writes 22438304 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67749 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68082 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5235386 # number of misc regfile reads +system.cpu2.misc_regfile_writes 258296 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index bab672da1..03035c465 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534279 # Number of seconds simulated -sim_ticks 2534279149500 # Number of ticks simulated -final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534332 # Number of seconds simulated +sim_ticks 2534332336000 # Number of ticks simulated +final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43780 # Simulator instruction rate (inst/s) -host_op_rate 56332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1839722930 # Simulator tick rate (ticks/s) -host_mem_usage 400528 # Number of bytes of host memory used -host_seconds 1377.53 # Real time elapsed on the host -sim_insts 60307893 # Number of instructions simulated -sim_ops 77599512 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory +host_inst_rate 47356 # Simulator instruction rate (inst/s) +host_op_rate 60934 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1990051953 # Simulator tick rate (ticks/s) +host_mem_usage 400524 # Number of bytes of host memory used +host_seconds 1273.50 # Real time elapsed on the host +sim_insts 60307773 # Number of instructions simulated +sim_ops 77599321 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory -system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory +system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15098054 # Total number of read requests seen -system.physmem.writeReqs 813133 # Total number of write requests seen -system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966275456 # Total number of bytes read from memory -system.physmem.bytesWritten 52040512 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943214 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943684 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15101237 # Total number of read requests seen +system.physmem.writeReqs 813162 # Total number of write requests seen +system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966479168 # Total number of bytes read from memory +system.physmem.bytesWritten 52042368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry -system.physmem.totGap 2534279100000 # Total gap between requests +system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry +system.physmem.totGap 2534332242000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14943424 # Categorize read packet sizes +system.physmem.readPktSize::3 14946576 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154594 # Categorize read packet sizes +system.physmem.readPktSize::6 154625 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59115 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1052560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 982701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 988227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3681755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2757300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2755283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2712082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 39830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 13755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59144 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -139,326 +139,316 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32462 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3417 8.03% 27.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2234 5.25% 32.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 533 1.25% 49.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 414 0.97% 49.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 258 0.61% 51.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 148 0.35% 53.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 144 0.34% 53.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 105 0.25% 54.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 120 0.28% 54.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 89 0.21% 54.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 396 0.93% 55.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 139 0.33% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 56 0.13% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 104 0.24% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 62 0.15% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 22 0.05% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 58 0.14% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 29 0.07% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 47 0.11% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 13 0.03% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 11 0.03% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 28 0.07% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 17 0.04% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 18 0.04% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 18 0.04% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 6 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 14 0.03% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 12 0.03% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 2 0.00% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 7 0.02% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 6 0.01% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 17 0.04% 63.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 5 0.01% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 8 0.02% 63.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 3 0.01% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 5 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 9 0.02% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 1 0.00% 63.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 5 0.01% 63.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 9 0.02% 63.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 39 0.09% 63.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 5 0.01% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 7 0.02% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 4 0.01% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 6 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 2 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 3 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 4 0.01% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 6 0.01% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 1 0.00% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 8 0.02% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 5 0.01% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 5 0.01% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 1 0.00% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 2 0.00% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 3 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5599 1 0.00% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 2 0.00% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 3 0.01% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 3 0.01% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 3 0.01% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 6 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 3 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 1 0.00% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 3 0.01% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 2 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 3 0.01% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 18 0.04% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 5 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 1 0.00% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 8 0.02% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 6 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 8 0.02% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation +system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 5 0.01% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14495 1 0.00% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15839 1 0.00% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 4 0.01% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18399 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18719 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18847 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18975 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19167 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 3 0.01% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19615 1 0.00% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20511 2 0.00% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21023 1 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21279 2 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21919 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22367 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 2 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24031 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24095 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24640-24671 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24799 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24863 1 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25311 1 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 2 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25887 2 0.00% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26271 1 0.00% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 3 0.01% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26911 1 0.00% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 3 0.01% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27743 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28191 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28639 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 2 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29599 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29727 3 0.01% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30303 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30495 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 3 0.01% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31007 2 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32031 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32159 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32543 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33055 2 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 1 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 6 0.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33631 2 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33695 1 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 44 0.10% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34591 2 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35231 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35871 2 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37535 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37919 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37983 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38943 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40287 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40991 3 0.01% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44575 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46111 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47647 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50207 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51231 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52255 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52992-53023 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53056-53087 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53760-53791 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54528-54559 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57344-57375 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57856-57887 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 2 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65119 8 0.02% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65247 18 0.04% 65.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65375 12 0.03% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation -system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests -system.physmem.totBusLat 75488575000 # Total cycles spent in databus access -system.physmem.totBankLat 15730536250 # Total cycles spent in bank access -system.physmem.avgQLat 23521.25 # Average queueing delay per request -system.physmem.avgBankLat 1041.92 # Average bank access latency per request +system.physmem.bytesPerActivate::159168-159199 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation +system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests +system.physmem.totBusLat 75504790000 # Total cycles spent in databus access +system.physmem.totBankLat 15713238750 # Total cycles spent in bank access +system.physmem.avgQLat 23320.54 # Average queueing delay per request +system.physmem.avgBankLat 1040.55 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29563.16 # Average memory access latency -system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 29361.08 # Average memory access latency +system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 11.71 # Average write queue length over time -system.physmem.readRowHits 15070837 # Number of row buffer hits during reads -system.physmem.writeRowHits 797438 # Number of row buffer hits during writes +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 10.77 # Average write queue length over time +system.physmem.readRowHits 15074158 # Number of row buffer hits during reads +system.physmem.writeRowHits 797610 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes -system.physmem.avgGap 159276.56 # Average gap between requests +system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes +system.physmem.avgGap 159247.75 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -471,60 +461,60 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54705448 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16150672 # Transaction distribution -system.membus.trans_dist::ReadResp 16150669 # Transaction distribution +system.membus.throughput 54715776 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16153842 # Transaction distribution +system.membus.trans_dist::ReadResp 16153842 # Transaction distribution system.membus.trans_dist::WriteReq 763336 # Transaction distribution system.membus.trans_dist::WriteResp 763336 # Transaction distribution -system.membus.trans_dist::Writeback 59115 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution +system.membus.trans_dist::Writeback 59144 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution -system.membus.trans_dist::ReadExReq 131424 # Transaction distribution -system.membus.trans_dist::ReadExResp 131424 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution +system.membus.trans_dist::ReadExReq 131438 # Transaction distribution +system.membus.trans_dist::ReadExResp 131438 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138638877 # Total data (bytes) +system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138667961 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -532,13 +522,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48115298 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution -system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution +system.iobus.throughput 48124265 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution +system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution system.iobus.trans_dist::WriteReq 8158 # Transaction distribution system.iobus.trans_dist::WriteResp 8158 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -560,11 +550,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -586,10 +576,10 @@ system.iobus.pkt_count::system.realview.sci_fake.pio 16 system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -611,11 +601,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -637,12 +627,12 @@ system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121937597 # Total data (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121962881 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -686,26 +676,26 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.branchPred.lookups 14673159 # Number of BP lookups -system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits +system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu.branchPred.lookups 14663186 # Number of BP lookups +system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987453 # DTB read hits +system.cpu.checker.dtb.read_hits 14987443 # DTB read hits system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227781 # DTB write hits +system.cpu.checker.dtb.write_hits 11227745 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -716,13 +706,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994760 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229970 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994750 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229934 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215234 # DTB hits +system.cpu.checker.dtb.hits 26215188 # DTB hits system.cpu.checker.dtb.misses 9496 # DTB misses -system.cpu.checker.dtb.accesses 26224730 # DTB accesses -system.cpu.checker.itb.inst_hits 61481893 # ITB inst hits +system.cpu.checker.dtb.accesses 26224684 # DTB accesses +system.cpu.checker.itb.inst_hits 61481774 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -739,36 +729,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486364 # ITB inst accesses -system.cpu.checker.itb.hits 61481893 # DTB hits +system.cpu.checker.itb.inst_accesses 61486245 # ITB inst accesses +system.cpu.checker.itb.hits 61481774 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486364 # DTB accesses -system.cpu.checker.numCycles 77885319 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486245 # DTB accesses +system.cpu.checker.numCycles 77885129 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51397173 # DTB read hits -system.cpu.dtb.read_misses 63986 # DTB read misses -system.cpu.dtb.write_hits 11699533 # DTB write hits -system.cpu.dtb.write_misses 15890 # DTB write misses +system.cpu.dtb.read_hits 51389107 # DTB read hits +system.cpu.dtb.read_misses 64168 # DTB read misses +system.cpu.dtb.write_hits 11699261 # DTB write hits +system.cpu.dtb.write_misses 15977 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6549 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6541 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51461159 # DTB read accesses -system.cpu.dtb.write_accesses 11715423 # DTB write accesses +system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51453275 # DTB read accesses +system.cpu.dtb.write_accesses 11715238 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63096706 # DTB hits -system.cpu.dtb.misses 79876 # DTB misses -system.cpu.dtb.accesses 63176582 # DTB accesses -system.cpu.itb.inst_hits 12260245 # ITB inst hits -system.cpu.itb.inst_misses 11468 # ITB inst misses +system.cpu.dtb.hits 63088368 # DTB hits +system.cpu.dtb.misses 80145 # DTB misses +system.cpu.dtb.accesses 63168513 # DTB accesses +system.cpu.itb.inst_hits 12244686 # ITB inst hits +system.cpu.itb.inst_misses 11272 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -777,148 +767,148 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4980 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4958 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12271713 # ITB inst accesses -system.cpu.itb.hits 12260245 # DTB hits -system.cpu.itb.misses 11468 # DTB misses -system.cpu.itb.accesses 12271713 # DTB accesses -system.cpu.numCycles 475189978 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12255958 # ITB inst accesses +system.cpu.itb.hits 12244686 # DTB hits +system.cpu.itb.misses 11272 # DTB misses +system.cpu.itb.accesses 12255958 # DTB accesses +system.cpu.numCycles 475312551 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13589329 8.89% 79.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued @@ -931,397 +921,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued -system.cpu.iq.rate 0.261620 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued +system.cpu.iq.rate 0.261503 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221659 # number of nop insts executed -system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed -system.cpu.iew.exec_branches 11560329 # Number of branches executed -system.cpu.iew.exec_stores 12210910 # Number of stores executed -system.cpu.iew.exec_rate 0.255996 # Inst execution rate -system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47268053 # num instructions producing a value -system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value +system.cpu.iew.exec_nop 222537 # number of nop insts executed +system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed +system.cpu.iew.exec_branches 11556571 # Number of branches executed +system.cpu.iew.exec_stores 12211191 # Number of stores executed +system.cpu.iew.exec_rate 0.255895 # Inst execution rate +system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47268516 # num instructions producing a value +system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back +system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458274 # Number of instructions committed -system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458154 # Number of instructions committed +system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386690 # Number of memory references committed -system.cpu.commit.loads 15654575 # Number of loads committed -system.cpu.commit.membars 403596 # Number of memory barriers committed -system.cpu.commit.branches 9961373 # Number of branches committed +system.cpu.commit.refs 27386643 # Number of memory references committed +system.cpu.commit.loads 15654562 # Number of loads committed +system.cpu.commit.membars 403601 # Number of memory barriers committed +system.cpu.commit.branches 9961356 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68855105 # Number of committed integer instructions. -system.cpu.commit.function_calls 991268 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854920 # Number of committed integer instructions. +system.cpu.commit.function_calls 991265 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243879966 # The number of ROB reads -system.cpu.rob.rob_writes 201882555 # The number of ROB writes -system.cpu.timesIdled 1780421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322302334 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593285278 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307893 # Number of Instructions Simulated -system.cpu.committedOps 77599512 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307893 # Number of Instructions Simulated -system.cpu.cpi 7.879399 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.879399 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126913 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126913 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550704703 # number of integer regfile reads -system.cpu.int_regfile_writes 88578313 # number of integer regfile writes -system.cpu.fp_regfile_reads 8302 # number of floating regfile reads -system.cpu.fp_regfile_writes 2882 # number of floating regfile writes -system.cpu.misc_regfile_reads 30116391 # number of misc regfile reads +system.cpu.rob.rob_reads 243752783 # The number of ROB reads +system.cpu.rob.rob_writes 201807644 # The number of ROB writes +system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307773 # Number of Instructions Simulated +system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated +system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550637147 # number of integer regfile reads +system.cpu.int_regfile_writes 88566596 # number of integer regfile writes +system.cpu.fp_regfile_reads 8370 # number of floating regfile reads +system.cpu.fp_regfile_writes 2906 # number of floating regfile writes +system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads system.cpu.misc_regfile_writes 831896 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58661050 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657246 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657245 # Transaction distribution +system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607669 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246055 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1960500 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5796171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30982 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7913971 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62698816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85512245 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 42284 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 208804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148462149 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148462149 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 201328 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128322117 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1471549889 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474731013 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2533210636 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2562590429 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20419483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20135737 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74237753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74394752 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 980157 # number of replacements -system.cpu.icache.tagsinuse 511.579914 # Cycle average of tags in use -system.cpu.icache.total_refs 11196212 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980669 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.416912 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6837358000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.579914 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999180 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11196212 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11196212 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11196212 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11196212 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11196212 # number of overall hits -system.cpu.icache.overall_hits::total 11196212 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060409 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060409 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060409 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060409 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060409 # number of overall misses -system.cpu.icache.overall_misses::total 1060409 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14257699991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14257699991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14257699991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14257699991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14257699991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14257699991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12256621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12256621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12256621 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12256621 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12256621 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12256621 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086517 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086517 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086517 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086517 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086517 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13445.472446 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13445.472446 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13445.472446 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13445.472446 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked +system.cpu.icache.tags.replacements 980590 # number of replacements +system.cpu.icache.tags.tagsinuse 511.580932 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11180201 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981102 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.395554 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6861342250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.580932 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11180201 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11180201 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11180201 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11180201 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11180201 # number of overall hits +system.cpu.icache.overall_hits::total 11180201 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060929 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060929 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060929 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060929 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060929 # number of overall misses +system.cpu.icache.overall_misses::total 1060929 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14286603183 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14286603183 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14286603183 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14286603183 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14286603183 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14286603183 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12241130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12241130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12241130 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12241130 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12241130 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12241130 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086669 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086669 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086669 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086669 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086669 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086669 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13466.125615 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13466.125615 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13466.125615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13466.125615 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8464 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 372 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 385 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.473118 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.984416 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79698 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79698 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79698 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79698 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79698 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79698 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980711 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980711 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980711 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980711 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980711 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980711 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583440602 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11583440602 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583440602 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11583440602 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583440602 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11583440602 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9547000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9547000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9547000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 9547000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080015 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.080015 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.080015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11811.268153 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11811.268153 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11811.268153 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11811.268153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11811.268153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11811.268153 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79785 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79785 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79785 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79785 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79785 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79785 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981144 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981144 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981144 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981144 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981144 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981144 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11597968227 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11597968227 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11597968227 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11597968227 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11597968227 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11597968227 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9563750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9563750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9563750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 9563750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080151 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.080151 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.080151 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11820.862409 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11820.862409 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64365 # number of replacements -system.cpu.l2cache.tagsinuse 51350.135703 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1885273 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129757 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.529259 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2499221448500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36903.083753 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 33.180761 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000367 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8167.882252 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6245.988569 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563096 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000506 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124632 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095306 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783541 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52156 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10569 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967205 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387072 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1417002 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56362.872681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56790.535790 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1442,161 +1432,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643353 # 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Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13746666 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13746666 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259188 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242891 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242891 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21005854 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21005854 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21005854 # number of overall hits +system.cpu.dcache.overall_hits::total 21005854 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14482928 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14482928 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222349 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222349 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256439 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256439 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24705277 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24705277 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24705277 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24705277 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050837 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050837 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289871 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289871 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052831 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052831 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149742 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149742 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149742 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149742 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13687.983840 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13687.983840 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45454.842720 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45454.842720 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13619.740921 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15206.058824 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15206.058824 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39132.578126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39132.578126 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32140 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25391 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2640 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 284 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.174242 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.404930 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607669 # number of writebacks -system.cpu.dcache.writebacks::total 607669 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351798 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351798 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715004 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2715004 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066802 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066802 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066802 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066802 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385700 # 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number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607541 # number of writebacks +system.cpu.dcache.writebacks::total 607541 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350669 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350669 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714279 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064948 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064948 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064948 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064948 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385593 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385593 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248882 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248882 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12204 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12204 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634475 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634475 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634475 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967192840 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967192840 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10605079278 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10605079278 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144959500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144959500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 224497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 224497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15572272118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15572272118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15572272118 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15572272118 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182317512000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182317512000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35728890492 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35728890492 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218046402492 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218046402492 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024347 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024347 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.958023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.958023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42610.872936 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42610.872936 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11878.031793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11878.031793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13205.705882 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13205.705882 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1604,12 +1594,12 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1618,16 +1608,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 7f7f9360b..5451e0c81 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.613797 # Number of seconds simulated -sim_ticks 2613796876500 # Number of ticks simulated -final_tick 2613796876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.114023 # Number of seconds simulated +sim_ticks 1114022852000 # Number of ticks simulated +final_tick 1114022852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54493 # Simulator instruction rate (inst/s) -host_op_rate 70162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2268463215 # Simulator tick rate (ticks/s) -host_mem_usage 404628 # Number of bytes of host memory used -host_seconds 1152.23 # Real time elapsed on the host -sim_insts 62788171 # Number of instructions simulated -sim_ops 80843130 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory +host_inst_rate 79652 # Simulator instruction rate (inst/s) +host_op_rate 102538 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1440387686 # Simulator tick rate (ticks/s) +host_mem_usage 404604 # Number of bytes of host memory used +host_seconds 773.42 # Real time elapsed on the host +sim_insts 61604368 # Number of instructions simulated +sim_ops 79304455 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4352820 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 426432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5278640 # Number of bytes read from this memory -system.physmem.bytes_read::total 131565412 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 426432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4275200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 409408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4367220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 406208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory +system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 409408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4263872 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7304336 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7291216 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6663 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82505 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302272 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66800 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6397 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66623 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824084 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46335096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1665325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2019530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50334979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151124 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163147 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1635628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1152399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2794531 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1635628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46335096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1671828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3171928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53129510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302272 # Total number of read requests seen -system.physmem.writeReqs 824084 # Total number of write requests seen -system.physmem.cpureqs 244248 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979345408 # Total number of bytes read from memory -system.physmem.bytesWritten 52741376 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131565412 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7304336 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 446 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14097 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956336 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956715 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 957144 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 956165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955908 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 956880 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955453 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956251 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 956326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 956256 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 52171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 52441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51720 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51713 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 52086 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51540 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51490 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51756 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51508 # Track writes on a per bank basis +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823459 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43768208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 367504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3920225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 364632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4710438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53132845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 367504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 364632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 732136 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3827455 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15260 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2702228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6544943 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3827455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43768208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 367504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3935485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 364632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7412667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59677788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257953 # Total number of read requests seen +system.physmem.writeReqs 823459 # Total number of write requests seen +system.physmem.cpureqs 242171 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400508992 # Total number of bytes read from memory +system.physmem.bytesWritten 52701376 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7291216 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12548 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391121 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391049 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 391102 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391825 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 391535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 391243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391065 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 391482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390728 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 390299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 390904 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 391045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391022 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49928 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51967 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51963 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 52290 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51965 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51872 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51692 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51908 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51949 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51308 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51011 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51134 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51585 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51529 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32582 # Number of times wr buffer was full causing retry -system.physmem.totGap 2613795718500 # Total gap between requests +system.physmem.numWrRetry 32580 # Number of times wr buffer was full causing retry +system.physmem.totGap 1114021721000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 15138816 # Categorize read packet sizes +system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163351 # Categorize read packet sizes +system.physmem.readPktSize::6 163000 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 757284 # Categorize write packet sizes +system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66800 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1071823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1000587 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1004460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3729147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2791599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2788638 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2744704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 40361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 13794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66623 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 508306 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 436400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 409055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1494610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1111724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1109849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1096192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 11963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 16960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 11777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 12128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5024 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -156,350 +156,366 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32605 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48021 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 21491.760022 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1412.636943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31347.507834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 10706 22.29% 22.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 4255 8.86% 31.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2654 5.53% 36.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 2034 4.24% 40.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1364 2.84% 43.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1232 2.57% 46.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 971 2.02% 48.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 916 1.91% 50.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 629 1.31% 51.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 621 1.29% 52.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 497 1.03% 53.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 447 0.93% 54.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 308 0.64% 55.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 288 0.60% 56.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 206 0.43% 56.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 291 0.61% 57.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 124 0.26% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 166 0.35% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 102 0.21% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 142 0.30% 58.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 76 0.16% 58.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 430 0.90% 59.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 2116 4.41% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 511 1.06% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 96 0.20% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 187 0.39% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 61 0.13% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 129 0.27% 65.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 42 0.09% 65.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 82 0.17% 65.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 32 0.07% 66.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 81 0.17% 66.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 30 0.06% 66.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 40 0.08% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 20 0.04% 66.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 38 0.08% 66.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 8 0.02% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 24 0.05% 66.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 13 0.03% 66.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 21 0.04% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 4 0.01% 66.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 15 0.03% 66.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 7 0.01% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 25 0.05% 66.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 10 0.02% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 14 0.03% 66.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 5 0.01% 66.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 16 0.03% 66.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 3 0.01% 66.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 10 0.02% 66.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 6 0.01% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 12 0.02% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 3 0.01% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 12 0.02% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 7 0.01% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 8 0.02% 66.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 5 0.01% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 6 0.01% 66.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 4 0.01% 66.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 10 0.02% 67.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 8 0.02% 67.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 9 0.02% 67.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 7 0.01% 67.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 36 0.07% 67.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 3 0.01% 67.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 8 0.02% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 3 0.01% 67.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 8 0.02% 67.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 1 0.00% 67.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 7 0.01% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 4 0.01% 67.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 67.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 1 0.00% 67.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 5 0.01% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 4 0.01% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 2 0.00% 67.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 3 0.01% 67.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5087 3 0.01% 67.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 10 0.02% 67.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 3 0.01% 67.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 3 0.01% 67.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 2 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 1 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 1 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 2 0.00% 67.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5599 3 0.01% 67.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 4 0.01% 67.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 2 0.00% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 5 0.01% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 2 0.00% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 1 0.00% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 7 0.01% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 1 0.00% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 4 0.01% 67.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6367 2 0.00% 67.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 2 0.00% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 1 0.00% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 3 0.01% 67.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 1 0.00% 67.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 2 0.00% 67.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 13 0.03% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 2 0.00% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 6 0.01% 67.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7007 1 0.00% 67.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 3 0.01% 67.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 5 0.01% 67.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7263 3 0.01% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 2 0.00% 67.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 6 0.01% 67.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 1 0.00% 67.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 4 0.01% 67.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 1 0.00% 67.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 4 0.01% 67.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 67.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 6 0.01% 67.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 67.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 6 0.01% 67.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 67.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 320 0.67% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8479 2 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 3 0.01% 68.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 2 0.00% 68.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9439 1 0.00% 68.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9503 3 0.01% 68.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9759 1 0.00% 68.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9951 1 0.00% 68.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 16 0.03% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10463 1 0.00% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10783 1 0.00% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 4 0.01% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11359 1 0.00% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 1 0.00% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12895 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12959 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13087 1 0.00% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 2 0.00% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13855 1 0.00% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14111 1 0.00% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 1 0.00% 68.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 2 0.00% 68.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14879 2 0.00% 68.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15199 1 0.00% 68.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 2 0.00% 68.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15455 1 0.00% 68.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16159 2 0.00% 68.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16415 2 0.00% 68.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16671 1 0.00% 68.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 2 0.00% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17183 1 0.00% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 1 0.00% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 1 0.00% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17823 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17887 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17951 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18719 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19103 1 0.00% 68.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 1 0.00% 68.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 3 0.01% 68.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19999 1 0.00% 68.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20255 1 0.00% 68.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20511 15 0.03% 68.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20639 1 0.00% 68.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 4 0.01% 68.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22303 2 0.00% 68.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 1 0.00% 68.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22815 3 0.01% 68.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23071 3 0.01% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23391 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 3 0.01% 68.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23872-23903 1 0.00% 68.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24095 2 0.00% 68.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 1 0.00% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 3 0.01% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24863 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25119 1 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25887 1 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25951 1 0.00% 68.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26143 2 0.00% 68.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 2 0.00% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 2 0.00% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27167 1 0.00% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27423 2 0.00% 68.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27615 1 0.00% 68.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 3 0.01% 68.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 1 0.00% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28191 1 0.00% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 2 0.00% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 4 0.01% 68.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29215 1 0.00% 68.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 2 0.00% 68.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 68.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 2 0.00% 68.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 7 0.01% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31263 1 0.00% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31519 1 0.00% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 3 0.01% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32543 3 0.01% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33055 3 0.01% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 2 0.00% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33759 1 0.00% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 55 0.11% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-34015 1 0.00% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34079 1 0.00% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34847 2 0.00% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35359 1 0.00% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 1 0.00% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35999 1 0.00% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36127 2 0.00% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36511 1 0.00% 68.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36639 1 0.00% 68.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38175 1 0.00% 68.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39199 1 0.00% 68.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39263 1 0.00% 68.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39647 1 0.00% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40384-40415 1 0.00% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41247 2 0.00% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 2 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42271 1 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42719 1 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42783 1 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43039 1 0.00% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44063 3 0.01% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44447 1 0.00% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44703 1 0.00% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46623 1 0.00% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46943 1 0.00% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-47007 1 0.00% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48671 1 0.00% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48927 1 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49439 2 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50719 1 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50880-50911 1 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51231 2 0.00% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52255 2 0.00% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52608-52639 1 0.00% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54784-54815 1 0.00% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55296-55327 1 0.00% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55616-55647 1 0.00% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56095 1 0.00% 68.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56832-56863 1 0.00% 68.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57088-57119 2 0.00% 68.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58143 1 0.00% 68.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59584-59615 1 0.00% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59648-59679 1 0.00% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59840-59871 1 0.00% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60447 1 0.00% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61215 1 0.00% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61568-61599 1 0.00% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61952-61983 1 0.00% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62976-63007 1 0.00% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63519 1 0.00% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64064-64095 1 0.00% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64543 1 0.00% 68.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65055 25 0.05% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65119 6 0.01% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65183 7 0.01% 68.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 19 0.04% 68.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65439 7 0.01% 68.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65503 18 0.04% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14562 30.32% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97536-97567 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::103680-103711 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130176-130207 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130624-130655 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130688-130719 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 321 0.67% 99.96% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 2907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32597 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 38811 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11677.106800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 598.829081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 25969.144286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 10478 27.00% 27.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 4256 10.97% 37.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2718 7.00% 44.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 2024 5.22% 50.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1422 3.66% 53.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1213 3.13% 56.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 997 2.57% 59.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 905 2.33% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 654 1.69% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 573 1.48% 65.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 456 1.17% 66.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 470 1.21% 67.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 308 0.79% 68.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 261 0.67% 68.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 192 0.49% 69.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 284 0.73% 70.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 136 0.35% 70.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 144 0.37% 70.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 111 0.29% 71.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 147 0.38% 71.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 83 0.21% 71.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 412 1.06% 72.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 1956 5.04% 77.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 510 1.31% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 94 0.24% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 178 0.46% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 53 0.14% 79.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 122 0.31% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 38 0.10% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 83 0.21% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 40 0.10% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 68 0.18% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 23 0.06% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 47 0.12% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 17 0.04% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 43 0.11% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 13 0.03% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 28 0.07% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 13 0.03% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 25 0.06% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 10 0.03% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 18 0.05% 81.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 7 0.02% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 19 0.05% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 4 0.01% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 20 0.05% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.02% 81.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 20 0.05% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 6 0.02% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 9 0.02% 81.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 7 0.02% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 18 0.05% 81.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 3 0.01% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 11 0.03% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 6 0.02% 81.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 12 0.03% 81.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 6 0.02% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 2 0.01% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 6 0.02% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 7 0.02% 81.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 5 0.01% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 10 0.03% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 2 0.01% 81.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 40 0.10% 82.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 1 0.00% 82.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 7 0.02% 82.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 2 0.01% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 5 0.01% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 3 0.01% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 4 0.01% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 3 0.01% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 9 0.02% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 2 0.01% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 2 0.01% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 2 0.01% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 2 0.01% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 5 0.01% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5087 1 0.00% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 7 0.02% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 4 0.01% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 2 0.01% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 2 0.01% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.01% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 2 0.01% 82.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 2 0.01% 82.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5599 3 0.01% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 3 0.01% 82.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5727 2 0.01% 82.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 1 0.00% 82.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5855 1 0.00% 82.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 2 0.01% 82.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 2 0.01% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 3 0.01% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 2 0.01% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 5 0.01% 82.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 3 0.01% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 4 0.01% 82.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6367 2 0.01% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 4 0.01% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 1 0.00% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 1 0.00% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 1 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 2 0.01% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 2 0.01% 82.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 14 0.04% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 3 0.01% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 3 0.01% 82.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7007 2 0.01% 82.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 2 0.01% 82.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 3 0.01% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7263 1 0.00% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 1 0.00% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 6 0.02% 82.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7519 1 0.00% 82.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 4 0.01% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 6 0.02% 82.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 2 0.01% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 2 0.01% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 2 0.01% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 7 0.02% 82.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 82.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 7 0.02% 82.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 316 0.81% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8287 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 2 0.01% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 5 0.01% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9375 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9503 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9695 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10015 2 0.01% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 15 0.04% 83.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10399 1 0.00% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10527 1 0.00% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10783 1 0.00% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11039 3 0.01% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 3 0.01% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 2 0.01% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12063 1 0.00% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 5 0.01% 83.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 1 0.00% 83.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12831 2 0.01% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12895 1 0.00% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13087 1 0.00% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 2 0.01% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13535 1 0.00% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13599 1 0.00% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 4 0.01% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15135 3 0.01% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 1 0.00% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15455 1 0.00% 83.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15775 1 0.00% 83.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16671 3 0.01% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17183 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 1 0.00% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17375 1 0.00% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 2 0.01% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17695 2 0.01% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17759 1 0.00% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-18015 1 0.00% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18207 3 0.01% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18591 1 0.00% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18719 2 0.01% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18975 2 0.01% 83.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19231 1 0.00% 83.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 4 0.01% 83.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19615 1 0.00% 83.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19999 3 0.01% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20127 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20255 1 0.00% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20511 12 0.03% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20767 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21279 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 2 0.01% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21791 1 0.00% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21952-21983 2 0.01% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22047 1 0.00% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 4 0.01% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22687 1 0.00% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22815 3 0.01% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23327 1 0.00% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 1 0.00% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24031 1 0.00% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24095 2 0.01% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24192-24223 1 0.00% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 1 0.00% 83.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 2 0.01% 83.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24735 2 0.01% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25375 1 0.00% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25408-25439 1 0.00% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 2 0.01% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25887 1 0.00% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26079 1 0.00% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26143 4 0.01% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26335 1 0.00% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27167 3 0.01% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27423 2 0.01% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27487 1 0.00% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 2 0.01% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 1 0.00% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 2 0.01% 83.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30495 1 0.00% 83.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30559 1 0.00% 83.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 3 0.01% 83.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30943 1 0.00% 83.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31007 2 0.01% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31071 1 0.00% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 2 0.01% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31808-31839 1 0.00% 83.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32223 1 0.00% 83.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 83.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32415 1 0.00% 83.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32543 2 0.01% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32799 2 0.01% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 1 0.00% 83.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33375 1 0.00% 83.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 5 0.01% 83.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33631 2 0.01% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33695 3 0.01% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33759 2 0.01% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 43 0.11% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34496-34527 1 0.00% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34847 2 0.01% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35167 1 0.00% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35871 1 0.00% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36127 1 0.00% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36288-36319 1 0.00% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36383 1 0.00% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37824-37855 1 0.00% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37919 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38175 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39263 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39455 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39519 1 0.00% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40287 1 0.00% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40832-40863 1 0.00% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40991 1 0.00% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41503 2 0.01% 84.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41664-41695 1 0.00% 84.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42271 1 0.00% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43039 1 0.00% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44127 1 0.00% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45599 1 0.00% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46111 2 0.01% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46367 2 0.01% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46879 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-47007 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48671 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48927 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49183 1 0.00% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49472-49503 1 0.00% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51231 2 0.01% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51776-51807 1 0.00% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52255 2 0.01% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54528-54559 2 0.01% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54784-54815 1 0.00% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56064-56095 1 0.00% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56351 1 0.00% 84.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57280-57311 1 0.00% 84.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57600-57631 2 0.01% 84.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57792-57823 1 0.00% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57856-57887 1 0.00% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58624-58655 1 0.00% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59840-59871 1 0.00% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59968-59999 1 0.00% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60447 1 0.00% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61471 4 0.01% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62208-62239 1 0.00% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62400-62431 1 0.00% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62495 1 0.00% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63519 2 0.01% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63744-63775 1 0.00% 84.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64543 1 0.00% 84.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65183 6 0.02% 84.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 6 0.02% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65439 1 0.00% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 5797 14.94% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129920-129951 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130880-130911 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 326 0.84% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131328-131359 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 2 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::133632-133663 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::140032-140063 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::162560-162591 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::165568-165599 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::169728-169759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::182528-182559 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48021 # Bytes accessed per row activation -system.physmem.totQLat 359781455750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 452374882000 # Sum of mem lat for all requests -system.physmem.totBusLat 76509130000 # Total cycles spent in databus access -system.physmem.totBankLat 16084296250 # Total cycles spent in bank access -system.physmem.avgQLat 23512.32 # Average queueing delay per request -system.physmem.avgBankLat 1051.14 # Average bank access latency per request +system.physmem.bytesPerActivate::175552-175583 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::189440-189471 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 6 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38811 # Bytes accessed per row activation +system.physmem.totQLat 182252409750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 221627859750 # Sum of mem lat for all requests +system.physmem.totBusLat 31289130000 # Total cycles spent in databus access +system.physmem.totBankLat 8086320000 # Total cycles spent in bank access +system.physmem.avgQLat 29123.92 # Average queueing delay per request +system.physmem.avgBankLat 1292.19 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29563.46 # Average memory access latency -system.physmem.avgRdBW 374.68 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.18 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.33 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.79 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 35416.11 # Average memory access latency +system.physmem.avgRdBW 359.52 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.31 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.13 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.54 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.08 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 13.40 # Average write queue length over time -system.physmem.readRowHits 15272830 # Number of row buffer hits during reads -system.physmem.writeRowHits 805042 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.69 # Row buffer hit rate for writes -system.physmem.avgGap 162082.23 # Average gap between requests +system.physmem.busUtil 3.18 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.20 # Average read queue length over time +system.physmem.avgWrQLen 11.52 # Average write queue length over time +system.physmem.readRowHits 6237911 # Number of row buffer hits during reads +system.physmem.writeRowHits 804550 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes +system.physmem.avgGap 157316.33 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -509,307 +525,307 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54057191 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16352590 # Transaction distribution -system.membus.trans_dist::ReadResp 16352590 # Transaction distribution -system.membus.trans_dist::WriteReq 769166 # Transaction distribution -system.membus.trans_dist::WriteResp 769166 # Transaction distribution -system.membus.trans_dist::Writeback 66800 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35679 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 18283 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14097 # Transaction distribution -system.membus.trans_dist::ReadExReq 138270 # Transaction distribution -system.membus.trans_dist::ReadExResp 137887 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bw_read::cpu0.inst 57 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 345 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 402 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 57 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 345 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 402 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 57 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 345 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 402 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 61845817 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306747 # Transaction distribution +system.membus.trans_dist::ReadResp 7306747 # Transaction distribution +system.membus.trans_dist::WriteReq 767893 # Transaction distribution +system.membus.trans_dist::WriteResp 767893 # Transaction distribution +system.membus.trans_dist::Writeback 66623 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33809 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17757 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12548 # Transaction distribution +system.membus.trans_dist::ReadExReq 138043 # Transaction distribution +system.membus.trans_dist::ReadExResp 137663 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1970999 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4376896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32254354 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 14160695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34654528 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::system.realview.local_cpu_timer.pio 850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 16555723 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389777 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17759220 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17723636 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23300 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20183988 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20138869 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2389777 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 138869748 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 66482420 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 23300 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141294516 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141294516 # Total data (bytes) +system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 68897653 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68897653 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1493240500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475761000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17657749750 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 11792000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 8620588249 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) +system.membus.reqLayer3.occupancy 9828000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 1805500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 756000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4833822840 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34180950731 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.replacements 73069 # number of replacements -system.l2c.tagsinuse 53059.477869 # Cycle average of tags in use -system.l2c.total_refs 1873536 # Total number of references to valid blocks. -system.l2c.sampled_refs 138222 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.554543 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37743.094868 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 4.500926 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000358 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4196.922721 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2968.415869 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 13.090066 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4030.052193 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4103.400867 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575914 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064040 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045294 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000200 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061494 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062613 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809623 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 23020 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 393598 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165506 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 32735 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098671 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000724 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010581 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098671 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61102.112440 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66724.991783 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63327.411493 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.099965 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.024613 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.503682 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.908740 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.811644 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.006608 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54663.358211 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58809.379683 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56945.687406 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61029.875296 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65172.040849 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62905.227161 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.604692 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.486386 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.093278 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.941824 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.858852 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.891841 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54677.242037 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59038.145621 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57070.582409 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55256.139729 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55256.139729 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1000,67 +1016,67 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58542991 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2739841 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2739840 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769166 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769166 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 583280 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 34832 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53489 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 259511 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 259511 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 800088 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073172 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13793 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 57051 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1229933 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4820895 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 15468 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 74350 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 8084750 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25585472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34695904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 18508 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 92124 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 39339008 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 48266196 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 22912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 131012 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 148151136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148151136 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4868352 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4921338984 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1802175919 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1506283904 # Layer occupancy (ticks) +system.toL2Bus.throughput 135543504 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2708876 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2708875 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767893 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767893 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 581377 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33332 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18117 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51449 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258856 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258856 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 787342 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073883 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13468 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 55968 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1192763 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4801194 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 14594 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 72477 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 8011689 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25176640 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34854805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 17052 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 88352 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 38149824 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 47763808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 20036 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 124096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 146194613 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146194613 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4803948 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4894718895 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1774755611 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1516721983 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9191448 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9224710 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34164696 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34035182 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2769642515 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3249270250 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9767440 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2687171756 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 3246383092 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 9605952 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41898883 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41732428 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47250451 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322888 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322888 # Transaction distribution -system.iobus.trans_dist::WriteReq 8066 # Transaction distribution -system.iobus.trans_dist::WriteResp 8066 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes) +system.iobus.throughput 45913386 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution +system.iobus.trans_dist::WriteReq 7946 # Transaction distribution +system.iobus.trans_dist::WriteResp 7946 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1077,16 +1093,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384276 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382510 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1103,15 +1119,15 @@ system.iobus.pkt_count::system.realview.sci_fake.pio 16 system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32661908 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 14572206 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1128,16 +1144,16 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2392552 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389777 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1154,25 +1170,25 @@ system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123503080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123503080 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 51148561 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148561 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4430000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4018000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 369000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) @@ -1203,44 +1219,44 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376210000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu0.branchPred.lookups 6073314 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4627623 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295826 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3795187 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2949225 # Number of BTB hits +system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374564000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 16693526268 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.branchPred.lookups 6007013 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4581243 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296095 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3784394 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2916091 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.709610 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 683153 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28183 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.055692 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673819 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28621 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8970256 # DTB read hits -system.cpu0.dtb.read_misses 29375 # DTB read misses -system.cpu0.dtb.write_hits 5214738 # DTB write hits -system.cpu0.dtb.write_misses 5731 # DTB write misses +system.cpu0.dtb.read_hits 8911671 # DTB read hits +system.cpu0.dtb.read_misses 28579 # DTB read misses +system.cpu0.dtb.write_hits 5140325 # DTB write hits +system.cpu0.dtb.write_misses 5457 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 935 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 591 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8999631 # DTB read accesses -system.cpu0.dtb.write_accesses 5220469 # DTB write accesses +system.cpu0.dtb.perms_faults 555 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8940250 # DTB read accesses +system.cpu0.dtb.write_accesses 5145782 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14184994 # DTB hits -system.cpu0.dtb.misses 35106 # DTB misses -system.cpu0.dtb.accesses 14220100 # DTB accesses -system.cpu0.itb.inst_hits 4276462 # ITB inst hits -system.cpu0.itb.inst_misses 5070 # ITB inst misses +system.cpu0.dtb.hits 14051996 # DTB hits +system.cpu0.dtb.misses 34036 # DTB misses +system.cpu0.dtb.accesses 14086032 # DTB accesses +system.cpu0.itb.inst_hits 4224524 # ITB inst hits +system.cpu0.itb.inst_misses 5106 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1249,530 +1265,534 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1351 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1346 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1356 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1478 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4281532 # ITB inst accesses -system.cpu0.itb.hits 4276462 # DTB hits -system.cpu0.itb.misses 5070 # DTB misses -system.cpu0.itb.accesses 4281532 # DTB accesses -system.cpu0.numCycles 69613456 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4229630 # ITB inst accesses +system.cpu0.itb.hits 4224524 # DTB hits +system.cpu0.itb.misses 5106 # DTB misses +system.cpu0.itb.accesses 4229630 # DTB accesses +system.cpu0.numCycles 69191123 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11926468 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32461716 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6073314 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3632378 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7613392 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1460130 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 63151 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20074417 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46093 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1371911 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4274981 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157877 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2111 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 42149460 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.995068 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.376418 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11726999 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32040106 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6007013 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3589910 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7522223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1454890 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60839 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19594371 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47034 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1322790 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4222942 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157135 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2060 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41323427 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.001891 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.382270 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34543319 81.95% 81.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 572779 1.36% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 825233 1.96% 85.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 684006 1.62% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 778589 1.85% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 565339 1.34% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 679715 1.61% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 356870 0.85% 92.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3143610 7.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33808589 81.81% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565594 1.37% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 817189 1.98% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676917 1.64% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 774557 1.87% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 561158 1.36% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 668023 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352527 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3098873 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 42149460 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.087243 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.466314 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12452855 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21284567 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6905227 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 522550 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 984261 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 948796 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64785 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40574738 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212216 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 984261 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13028707 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5941224 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13201317 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6800913 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2193038 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39456506 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 442978 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1248488 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 66 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39834265 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 178291734 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 178257443 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34291 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31450110 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8384154 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 420012 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 376763 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5452877 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7762434 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5776236 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1132872 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1233884 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37360552 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 904892 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37716432 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 82271 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6323448 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13282471 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257104 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 42149460 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.894826 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.507768 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41323427 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086818 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.463067 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12228313 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20776644 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6830919 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 507068 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 980483 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935966 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64632 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40044073 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213118 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 980483 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12794933 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5974902 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12785484 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6719608 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2068017 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38935181 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1840 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 426390 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1152446 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 100 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39283995 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175854037 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175819876 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34161 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30939461 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8344533 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411347 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370357 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5351975 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7655764 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5689444 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124222 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1281984 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36848399 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895286 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37254672 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81509 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6299557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13203578 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256355 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41323427 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901539 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.514633 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26809075 63.60% 63.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5821539 13.81% 77.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3209963 7.62% 85.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2497911 5.93% 90.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2123670 5.04% 96.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 939017 2.23% 98.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 502938 1.19% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 188935 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 56412 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26248165 63.52% 63.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5684023 13.75% 77.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3115322 7.54% 84.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2467752 5.97% 90.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2139591 5.18% 95.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 926164 2.24% 98.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 502996 1.22% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185723 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53691 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 42149460 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41323427 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27471 2.55% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 463 0.04% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 839894 78.10% 80.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207538 19.30% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27493 2.57% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 842638 78.71% 81.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 200034 18.68% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22648900 60.05% 60.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47937 0.13% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9431477 25.01% 85.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5535066 14.68% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22336809 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46914 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9369783 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5448235 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37716432 # Type of FU issued -system.cpu0.iq.rate 0.541798 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1075366 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028512 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 118766388 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44596758 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34851054 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8389 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 37254672 # Type of FU issued +system.cpu0.iq.rate 0.538431 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070617 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028738 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117010237 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44051144 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34347967 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8478 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38735073 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4381 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 316422 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 38268613 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4462 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307627 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1379018 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2578 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13049 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 541624 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1377452 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2519 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13094 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537577 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149592 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 6129 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192819 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5737 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 984261 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4297602 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 105996 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38383622 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 87186 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7762434 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5776236 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 577553 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40750 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2975 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13049 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150118 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117853 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267971 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37335026 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9287293 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 381406 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 980483 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4321779 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 103852 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37861161 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83824 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7655764 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5689444 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571291 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39684 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 13815 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13094 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150380 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118124 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 268504 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36875907 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9227090 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 378765 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118178 # number of nop insts executed -system.cpu0.iew.exec_refs 14774953 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4916788 # Number of branches executed -system.cpu0.iew.exec_stores 5487660 # Number of stores executed -system.cpu0.iew.exec_rate 0.536319 # Inst execution rate -system.cpu0.iew.wb_sent 37140556 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34854926 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18563816 # num instructions producing a value -system.cpu0.iew.wb_consumers 35689656 # num instructions consuming a value +system.cpu0.iew.exec_nop 117476 # number of nop insts executed +system.cpu0.iew.exec_refs 14627584 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4856181 # Number of branches executed +system.cpu0.iew.exec_stores 5400494 # Number of stores executed +system.cpu0.iew.exec_rate 0.532957 # Inst execution rate +system.cpu0.iew.wb_sent 36680744 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34351839 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18317228 # num instructions producing a value +system.cpu0.iew.wb_consumers 35218038 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.500692 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520146 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.496478 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520109 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6130188 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 647788 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232202 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 41165199 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.772263 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.733134 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6105741 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638931 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232529 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40342944 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775737 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.743782 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29286812 71.14% 71.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5810011 14.11% 85.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1968218 4.78% 90.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 996844 2.42% 92.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 804428 1.95% 94.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 515457 1.25% 95.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 392582 0.95% 96.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 223885 0.54% 97.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1166962 2.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28719843 71.19% 71.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5706970 14.15% 85.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1863125 4.62% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 981446 2.43% 92.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 776304 1.92% 94.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 515472 1.28% 95.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 394004 0.98% 96.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 214891 0.53% 97.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1170889 2.90% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 41165199 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24069809 # Number of instructions committed -system.cpu0.commit.committedOps 31790359 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40342944 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23687602 # Number of instructions committed +system.cpu0.commit.committedOps 31295507 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11618028 # Number of memory references committed -system.cpu0.commit.loads 6383416 # Number of loads committed -system.cpu0.commit.membars 231880 # Number of memory barriers committed -system.cpu0.commit.branches 4307208 # Number of branches committed +system.cpu0.commit.refs 11430179 # Number of memory references committed +system.cpu0.commit.loads 6278312 # Number of loads committed +system.cpu0.commit.membars 229695 # Number of memory barriers committed +system.cpu0.commit.branches 4246577 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28099612 # Number of committed integer instructions. -system.cpu0.commit.function_calls 498731 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1166962 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27650890 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489495 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1170889 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 77052413 # The number of ROB reads -system.cpu0.rob.rob_writes 76827079 # The number of ROB writes -system.cpu0.timesIdled 370271 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27463996 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5157937915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23989067 # Number of Instructions Simulated -system.cpu0.committedOps 31709617 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23989067 # Number of Instructions Simulated -system.cpu0.cpi 2.901883 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.901883 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.344604 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.344604 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174143996 # number of integer regfile reads -system.cpu0.int_regfile_writes 34604534 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3264 # number of floating regfile reads -system.cpu0.fp_regfile_writes 896 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13203658 # number of misc regfile reads -system.cpu0.misc_regfile_writes 457594 # number of misc regfile writes -system.cpu0.icache.replacements 399659 # number of replacements -system.cpu0.icache.tagsinuse 511.575445 # Cycle average of tags in use -system.cpu0.icache.total_refs 3842942 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 400171 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.603250 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6980726000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.575445 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999171 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999171 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3842942 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3842942 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3842942 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3842942 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3842942 # number of overall hits -system.cpu0.icache.overall_hits::total 3842942 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 431911 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 431911 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 431911 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 431911 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 431911 # number of overall misses -system.cpu0.icache.overall_misses::total 431911 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5969636493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5969636493 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5969636493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5969636493 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5969636493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5969636493 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4274853 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4274853 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4274853 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4274853 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4274853 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4274853 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.101035 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.101035 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.101035 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.101035 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.101035 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.101035 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.450468 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13821.450468 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13821.450468 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13821.450468 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3644 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75722045 # The number of ROB reads +system.cpu0.rob.rob_writes 75784919 # The number of ROB writes +system.cpu0.timesIdled 368023 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27867696 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2158812857 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23606860 # Number of Instructions Simulated +system.cpu0.committedOps 31214765 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23606860 # Number of Instructions Simulated +system.cpu0.cpi 2.930975 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.930975 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.341183 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.341183 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171887932 # number of integer regfile reads +system.cpu0.int_regfile_writes 34101589 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads +system.cpu0.fp_regfile_writes 874 # number of floating regfile writes +system.cpu0.misc_regfile_reads 12983242 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451267 # number of misc regfile writes +system.cpu0.icache.tags.replacements 393301 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.011114 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3798020 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 393813 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.644222 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6979217250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.011114 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998069 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3798020 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3798020 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3798020 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3798020 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3798020 # number of overall hits +system.cpu0.icache.overall_hits::total 3798020 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 424793 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 424793 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 424793 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 424793 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 424793 # number of overall misses +system.cpu0.icache.overall_misses::total 424793 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5908836480 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5908836480 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5908836480 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5908836480 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5908836480 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5908836480 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222813 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4222813 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4222813 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4222813 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4222813 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4222813 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100595 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100595 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100595 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100595 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100595 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100595 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.919608 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.919608 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.919608 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13909.919608 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.919608 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13909.919608 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3571 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.942529 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.620879 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31718 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31718 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31718 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31718 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31718 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31718 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400193 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 400193 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 400193 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 400193 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 400193 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 400193 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4864756575 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4864756575 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4864756575 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4864756575 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4864756575 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4864756575 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9682500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9682500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9682500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9682500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093616 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093616 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093616 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12156.026155 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12156.026155 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12156.026155 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30958 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30958 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30958 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30958 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30958 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30958 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393835 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393835 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393835 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393835 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393835 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393835 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4811729884 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4811729884 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4811729884 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4811729884 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4811729884 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4811729884 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9686500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9686500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9686500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 9686500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093264 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093264 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093264 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.628916 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.628916 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.628916 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275313 # number of replacements -system.cpu0.dcache.tagsinuse 479.702966 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9426114 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275825 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.174255 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 49336000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 479.702966 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.936920 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.936920 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5876643 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5876643 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3228072 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3228072 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139641 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139641 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137200 # 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number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1977793 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1977793 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1977793 # number of overall misses -system.cpu0.dcache.overall_misses::total 1977793 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5514730000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5514730000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76877974883 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 76877974883 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 89351500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 89351500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49685500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 49685500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 82392704883 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 82392704883 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 82392704883 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 82392704883 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6269229 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6269229 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4813279 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4813279 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148473 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148473 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144954 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144954 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11082508 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11082508 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11082508 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11082508 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062621 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062621 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329340 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.329340 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059486 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059486 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053493 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053493 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178461 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178461 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178461 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178461 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14047.189660 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14047.189660 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48497.120492 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48497.120492 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10116.791214 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10116.791214 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6407.725045 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6407.725045 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41658.912173 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41658.912173 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 10507 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 10018 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 605 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 134 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.366942 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 74.761194 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 276277 # number of replacements +system.cpu0.dcache.tags.tagsinuse 458.508643 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9265297 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 276789 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.474224 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 49564250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 458.508643 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.895525 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.895525 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5784459 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5784459 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159328 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159328 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139329 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139329 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137110 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137110 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8943787 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8943787 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8943787 # number of overall hits +system.cpu0.dcache.overall_hits::total 8943787 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392022 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392022 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1584787 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1584787 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8757 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8757 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7526 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7526 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1976809 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1976809 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1976809 # number of overall misses +system.cpu0.dcache.overall_misses::total 1976809 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5532398989 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5532398989 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77338129003 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77338129003 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88246985 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88246985 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46297127 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46297127 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 82870527992 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 82870527992 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 82870527992 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 82870527992 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6176481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744115 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744115 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148086 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148086 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144636 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144636 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10920596 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10920596 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10920596 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10920596 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063470 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063470 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334053 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334053 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059135 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059135 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052034 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052034 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181017 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181017 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181017 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181017 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14112.470701 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14112.470701 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48800.330267 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 48800.330267 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10077.307868 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10077.307868 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6151.624635 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6151.624635 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41921.363163 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41921.363163 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41921.363163 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41921.363163 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9474 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 7234 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 614 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 133 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.429967 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 54.390977 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255296 # number of writebacks -system.cpu0.dcache.writebacks::total 255296 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203565 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203565 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454109 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454109 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 475 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 475 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657674 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657674 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657674 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657674 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189021 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189021 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131098 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131098 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8357 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8357 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7751 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7751 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320119 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320119 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320119 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320119 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2392342380 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2392342380 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5118910660 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5118910660 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67659513 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67659513 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34183001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34183001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7511253040 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7511253040 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7511253040 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7511253040 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13429863028 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13429863028 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251424879 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1251424879 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14681287907 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14681287907 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030151 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030151 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027237 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027237 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056286 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056286 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053472 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053472 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028885 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028885 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12656.489914 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12656.489914 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39046.443577 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39046.443577 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8096.148498 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8096.148498 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4410.140756 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4410.140756 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256588 # number of writebacks +system.cpu0.dcache.writebacks::total 256588 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203202 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203202 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454368 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454368 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 460 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 460 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657570 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657570 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657570 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657570 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188820 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188820 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130419 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130419 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8297 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7522 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7522 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319239 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319239 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319239 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319239 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2408343372 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2408343372 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110867707 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110867707 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66642015 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66642015 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31254873 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31254873 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7519211079 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7519211079 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7519211079 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7519211079 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504631783 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504631783 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180253969 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180253969 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14684885752 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14684885752 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030571 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030571 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027491 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027491 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056028 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056028 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052006 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052006 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029233 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029233 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.704862 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.704862 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39188.060842 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39188.060842 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8032.061589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8032.061589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4155.128024 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4155.128024 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1780,38 +1800,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9253585 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7592303 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 416171 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6192388 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5325484 # Number of BTB hits +system.cpu1.branchPred.lookups 9066954 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7451944 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 406719 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6049384 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5236824 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.000490 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 798470 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43798 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.567889 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772531 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42321 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43179554 # DTB read hits -system.cpu1.dtb.read_misses 37431 # DTB read misses -system.cpu1.dtb.write_hits 6972554 # DTB write hits -system.cpu1.dtb.write_misses 10848 # DTB write misses +system.cpu1.dtb.read_hits 42909677 # DTB read hits +system.cpu1.dtb.read_misses 36560 # DTB read misses +system.cpu1.dtb.write_hits 6823585 # DTB write hits +system.cpu1.dtb.write_misses 10691 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2926 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 258 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2608 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43216985 # DTB read accesses -system.cpu1.dtb.write_accesses 6983402 # DTB write accesses +system.cpu1.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42946237 # DTB read accesses +system.cpu1.dtb.write_accesses 6834276 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50152108 # DTB hits -system.cpu1.dtb.misses 48279 # DTB misses -system.cpu1.dtb.accesses 50200387 # DTB accesses -system.cpu1.itb.inst_hits 8467709 # ITB inst hits -system.cpu1.itb.inst_misses 5542 # ITB inst misses +system.cpu1.dtb.hits 49733262 # DTB hits +system.cpu1.dtb.misses 47251 # DTB misses +system.cpu1.dtb.accesses 49780513 # DTB accesses +system.cpu1.itb.inst_hits 8323198 # ITB inst hits +system.cpu1.itb.inst_misses 5400 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1820,113 +1840,113 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1529 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1492 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8473251 # ITB inst accesses -system.cpu1.itb.hits 8467709 # DTB hits -system.cpu1.itb.misses 5542 # DTB misses -system.cpu1.itb.accesses 8473251 # DTB accesses -system.cpu1.numCycles 412553366 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8328598 # ITB inst accesses +system.cpu1.itb.hits 8323198 # DTB hits +system.cpu1.itb.misses 5400 # DTB misses +system.cpu1.itb.accesses 8328598 # DTB accesses +system.cpu1.numCycles 410695591 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 20142179 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 67124404 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9253585 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6123954 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14367636 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3996679 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 69030 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77666254 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41513 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1490350 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8465907 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 710561 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2899 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 116503477 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.698188 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.043258 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19628666 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66104666 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9066954 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6009355 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14131573 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3952223 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 62853 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77248707 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42228 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1436171 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 176 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8321388 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 704092 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2736 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 115246116 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.694374 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.038205 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 102143196 87.67% 87.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 814134 0.70% 88.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 962782 0.83% 89.20% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1912655 1.64% 90.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1508621 1.29% 92.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 586161 0.50% 92.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2143967 1.84% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 421141 0.36% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6010820 5.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101121884 87.74% 87.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796637 0.69% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937162 0.81% 89.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1885853 1.64% 90.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1499695 1.30% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570142 0.49% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2110638 1.83% 94.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410756 0.36% 94.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5913349 5.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 116503477 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022430 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.162705 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21695015 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78657608 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12988209 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 540911 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2621734 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1137928 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 100371 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 76331637 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 334218 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2621734 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 23056356 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33279261 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41089956 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12073504 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4382666 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 71129037 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18835 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 684998 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3107715 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 374 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 75211284 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 327489941 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 327430919 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50108296 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 25102988 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 461152 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 401338 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8025308 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13414582 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8304810 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1056481 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1432553 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 64611179 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1174620 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 90302569 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94169 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16313013 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45540722 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 275640 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 116503477 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.775106 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513735 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 115246116 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022077 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.160958 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21155925 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78195753 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12775663 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 524358 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2594417 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105836 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98153 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75067660 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 326745 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2594417 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22501379 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33242741 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40762154 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11860446 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4284979 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69913296 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18816 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 670004 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3042907 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 379 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73978163 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321899381 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321840484 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58897 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49060581 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24917582 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444517 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387690 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7870912 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13163327 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8127092 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1028302 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1543452 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63442447 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157372 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89134089 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93553 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16181139 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45168283 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 276533 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 115246116 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.773424 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513958 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 85607171 73.48% 73.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8609069 7.39% 80.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4398916 3.78% 84.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3887525 3.34% 87.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10612061 9.11% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1964931 1.69% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1085414 0.93% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 259410 0.22% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 78980 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84850695 73.63% 73.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8420843 7.31% 80.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4255514 3.69% 84.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3817238 3.31% 87.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10566074 9.17% 97.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1932638 1.68% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1074262 0.93% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 253370 0.22% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75482 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 116503477 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 115246116 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32357 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32069 0.41% 0.41% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available @@ -1955,395 +1975,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7572484 95.70% 96.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 307046 3.88% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7550960 95.79% 96.21% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 298953 3.79% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 38359652 42.48% 42.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1701 0.00% 42.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.90% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44223929 48.97% 91.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7342124 8.13% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37650996 42.24% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59191 0.07% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43937068 49.29% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7171235 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 90302569 # Type of FU issued -system.cpu1.iq.rate 0.218887 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7912883 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.087626 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 305148356 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 82107584 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54845197 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15407 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8039 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6808 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 97893314 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8206 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 355446 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89134089 # Type of FU issued +system.cpu1.iq.rate 0.217032 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7882978 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088440 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 301522554 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80789150 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53744584 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15343 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8026 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96694852 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8153 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 340284 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3436601 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3841 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17378 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1303587 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3407112 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3737 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 16742 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1286559 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31958921 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 917809 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31912923 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 915604 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2621734 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25482277 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 363023 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 65889169 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 115264 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13414582 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8304810 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 878172 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 66494 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3874 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17378 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 205598 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 157346 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 362944 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87965313 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43561744 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2337256 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2594417 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25467221 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 361914 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64703269 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112618 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13163327 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8127092 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869000 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64609 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6290 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 16742 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 200151 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154994 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355145 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86813167 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43279828 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2320922 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103370 # number of nop insts executed -system.cpu1.iew.exec_refs 50840273 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7156944 # Number of branches executed -system.cpu1.iew.exec_stores 7278529 # Number of stores executed -system.cpu1.iew.exec_rate 0.213222 # Inst execution rate -system.cpu1.iew.wb_sent 86983330 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54852005 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30529736 # num instructions producing a value -system.cpu1.iew.wb_consumers 54511543 # num instructions consuming a value +system.cpu1.iew.exec_nop 103450 # number of nop insts executed +system.cpu1.iew.exec_refs 50389574 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6997831 # Number of branches executed +system.cpu1.iew.exec_stores 7109746 # Number of stores executed +system.cpu1.iew.exec_rate 0.211381 # Inst execution rate +system.cpu1.iew.wb_sent 85834090 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53751385 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29958578 # num instructions producing a value +system.cpu1.iew.wb_consumers 53322000 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.132957 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560060 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.130879 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.561843 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16208484 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 898980 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 317402 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 113881743 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.432055 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.398122 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16054832 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880839 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310229 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112651699 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.427506 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.393608 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 96739305 84.95% 84.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8399776 7.38% 92.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2206670 1.94% 94.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1295256 1.14% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1289720 1.13% 96.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 586162 0.51% 97.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 954092 0.84% 97.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 596070 0.52% 98.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1814692 1.59% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95929787 85.16% 85.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8195439 7.28% 92.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2121242 1.88% 94.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1255081 1.11% 95.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1260461 1.12% 96.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 575308 0.51% 97.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 943355 0.84% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 590559 0.52% 98.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1780467 1.58% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 113881743 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38868743 # Number of instructions committed -system.cpu1.commit.committedOps 49203152 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112651699 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38067147 # Number of instructions committed +system.cpu1.commit.committedOps 48159329 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16979204 # Number of memory references committed -system.cpu1.commit.loads 9977981 # Number of loads committed -system.cpu1.commit.membars 195491 # Number of memory barriers committed -system.cpu1.commit.branches 6119212 # Number of branches committed +system.cpu1.commit.refs 16596748 # Number of memory references committed +system.cpu1.commit.loads 9756215 # Number of loads committed +system.cpu1.commit.membars 190139 # Number of memory barriers committed +system.cpu1.commit.branches 5967970 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43616743 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553203 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1814692 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42694003 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534679 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1780467 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 176412864 # The number of ROB reads -system.cpu1.rob.rob_writes 133542996 # The number of ROB writes -system.cpu1.timesIdled 1428534 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 296049889 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4814402067 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38799104 # Number of Instructions Simulated -system.cpu1.committedOps 49133513 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38799104 # Number of Instructions Simulated -system.cpu1.cpi 10.633064 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.633064 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.094046 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.094046 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 393827212 # number of integer regfile reads -system.cpu1.int_regfile_writes 57409312 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5077 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2342 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18946986 # number of misc regfile reads -system.cpu1.misc_regfile_writes 419134 # number of misc regfile writes -system.cpu1.icache.replacements 614670 # number of replacements -system.cpu1.icache.tagsinuse 498.803951 # Cycle average of tags in use -system.cpu1.icache.total_refs 7804426 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 615182 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.686369 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74831061000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.803951 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974226 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974226 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7804426 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7804426 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7804426 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7804426 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7804426 # number of overall hits -system.cpu1.icache.overall_hits::total 7804426 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 661434 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 661434 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 661434 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 661434 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 661434 # number of overall misses -system.cpu1.icache.overall_misses::total 661434 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8993382992 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8993382992 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8993382992 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8993382992 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8993382992 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8993382992 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8465860 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8465860 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8465860 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8465860 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8465860 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8465860 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.078130 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.078130 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.078130 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.078130 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.078130 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.078130 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13596.795738 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13596.795738 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13596.795738 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13596.795738 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3054 # number of cycles access was blocked +system.cpu1.rob.rob_reads 174041277 # The number of ROB reads +system.cpu1.rob.rob_writes 131120872 # The number of ROB writes +system.cpu1.timesIdled 1414866 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295449475 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1816711228 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37997508 # Number of Instructions Simulated +system.cpu1.committedOps 48089690 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37997508 # Number of Instructions Simulated +system.cpu1.cpi 10.808488 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.808488 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092520 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092520 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 388394171 # number of integer regfile reads +system.cpu1.int_regfile_writes 56329363 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2330 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18495746 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405487 # number of misc regfile writes +system.cpu1.icache.tags.replacements 596092 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.837460 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7679654 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 596604 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 12.872280 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74828235500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.837460 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.939136 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.939136 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7679654 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7679654 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7679654 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7679654 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7679654 # number of overall hits +system.cpu1.icache.overall_hits::total 7679654 # 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number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8321340 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8321340 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8321340 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8321340 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8321340 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8321340 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.077113 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.077113 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.077113 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.077113 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.077113 # 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number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7121155232 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7121155232 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7121155232 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7121155232 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3411250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3411250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3411250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3411250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071698 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071698 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071698 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11935.710532 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11935.710532 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11935.710532 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363541 # number of replacements -system.cpu1.dcache.tagsinuse 487.194544 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13012998 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363907 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.759131 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70879256000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.194544 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951552 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951552 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8508304 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8508304 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4270423 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4270423 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99789 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 99789 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97069 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 97069 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12778727 # 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average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5299.504950 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5299.504950 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 41631.625064 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 41631.625064 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 41631.625064 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 41631.625064 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 31799 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 19293 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3299 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 180 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.638982 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 107.183333 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 360464 # number of replacements +system.cpu1.dcache.tags.tagsinuse 473.569939 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 12678323 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 360816 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.137918 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70878166000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.569939 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924941 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.924941 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8311494 # 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number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75676889684 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 75676889684 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129078996 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129078996 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53253915 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53253915 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 81809071748 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 81809071748 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 81809071748 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 81809071748 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8709670 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8709670 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5697011 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5697011 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111511 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111511 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105477 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105477 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14406681 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14406681 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14406681 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14406681 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045717 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045717 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273503 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273503 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125010 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125010 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100486 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100486 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135793 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135793 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135793 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135793 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15400.682271 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15400.682271 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48568.361549 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 48568.361549 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9259.612339 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9259.612339 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5024.428248 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5024.428248 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 41817.666438 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 41817.666438 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 41817.666438 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 41817.666438 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29976 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 17316 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3303 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 173 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.075386 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 100.092486 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327984 # number of writebacks -system.cpu1.dcache.writebacks::total 327984 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171525 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171525 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401265 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1401265 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1449 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1449 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572790 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1572790 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572790 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1572790 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231477 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231477 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163056 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163056 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10906 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10906 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394533 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394533 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394533 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394533 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2900781135 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2900781135 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6520340298 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6520340298 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90030007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90030007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35995000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35995000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9421121433 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9421121433 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9421121433 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9421121433 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169236235005 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169236235005 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34877229187 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34877229187 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204113464192 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204113464192 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025976 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025976 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027946 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027946 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111823 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111823 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101003 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101003 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026755 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026755 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12531.617115 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12531.617115 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39988.349389 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39988.349389 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7063.392986 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7063.392986 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3300.476802 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3300.476802 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324789 # number of writebacks +system.cpu1.dcache.writebacks::total 324789 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170095 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170095 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396532 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1396532 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1437 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1437 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566627 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566627 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566627 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566627 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228081 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228081 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161620 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161620 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12503 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12503 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10598 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10598 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389701 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389701 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389701 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389701 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2839406051 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2839406051 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6490016907 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6490016907 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88435503 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88435503 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32057085 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32057085 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9329422958 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9329422958 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9329422958 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9329422958 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168915044006 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168915044006 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34787133815 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34787133815 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 203702177821 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 203702177821 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026187 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112123 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112123 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100477 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100477 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12449.112600 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12449.112600 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40156.025906 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40156.025906 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7073.142686 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7073.142686 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.824023 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.824023 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23939.951291 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23939.951291 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2351,12 +2371,12 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2365,18 +2385,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1508067529269 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1508067529269 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 644226028268 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 644226028268 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 644226028268 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 644226028268 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42383 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50336 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b3687441c..49ef0687e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534279 # Number of seconds simulated -sim_ticks 2534279149500 # Number of ticks simulated -final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534332 # Number of seconds simulated +sim_ticks 2534332336000 # Number of ticks simulated +final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51469 # Simulator instruction rate (inst/s) -host_op_rate 66227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2162854547 # Simulator tick rate (ticks/s) -host_mem_usage 400508 # Number of bytes of host memory used -host_seconds 1171.73 # Real time elapsed on the host -sim_insts 60307893 # Number of instructions simulated -sim_ops 77599512 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory +host_inst_rate 60160 # Simulator instruction rate (inst/s) +host_op_rate 77409 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2528112838 # Simulator tick rate (ticks/s) +host_mem_usage 401532 # Number of bytes of host memory used +host_seconds 1002.46 # Real time elapsed on the host +sim_insts 60307773 # Number of instructions simulated +sim_ops 77599321 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory -system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory +system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15098054 # Total number of read requests seen -system.physmem.writeReqs 813133 # Total number of write requests seen -system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966275456 # Total number of bytes read from memory -system.physmem.bytesWritten 52040512 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943214 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943684 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15101237 # Total number of read requests seen +system.physmem.writeReqs 813162 # Total number of write requests seen +system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966479168 # Total number of bytes read from memory +system.physmem.bytesWritten 52042368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry -system.physmem.totGap 2534279100000 # Total gap between requests +system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry +system.physmem.totGap 2534332242000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14943424 # Categorize read packet sizes +system.physmem.readPktSize::3 14946576 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154594 # Categorize read packet sizes +system.physmem.readPktSize::6 154625 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59115 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1052560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 982701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 988227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3681755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2757300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2755283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2712082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 39830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 13755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59144 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -139,326 +139,316 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32462 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3417 8.03% 27.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2234 5.25% 32.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 533 1.25% 49.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 414 0.97% 49.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 258 0.61% 51.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 148 0.35% 53.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 144 0.34% 53.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 105 0.25% 54.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 120 0.28% 54.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 89 0.21% 54.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 396 0.93% 55.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 139 0.33% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 56 0.13% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 104 0.24% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 62 0.15% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 22 0.05% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 58 0.14% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 29 0.07% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 47 0.11% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 13 0.03% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 11 0.03% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 28 0.07% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 17 0.04% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 18 0.04% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 18 0.04% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 6 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 14 0.03% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 12 0.03% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 2 0.00% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 7 0.02% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 6 0.01% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 17 0.04% 63.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 5 0.01% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 8 0.02% 63.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 3 0.01% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 5 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 9 0.02% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 1 0.00% 63.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 5 0.01% 63.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 9 0.02% 63.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 39 0.09% 63.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 5 0.01% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 7 0.02% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 4 0.01% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 6 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 2 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 3 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 4 0.01% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 6 0.01% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 1 0.00% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 8 0.02% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 5 0.01% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 5 0.01% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 1 0.00% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 2 0.00% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 3 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5599 1 0.00% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 2 0.00% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 3 0.01% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 3 0.01% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 3 0.01% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 6 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 3 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 1 0.00% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 3 0.01% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 2 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 3 0.01% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 18 0.04% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 5 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 1 0.00% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 8 0.02% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 6 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 8 0.02% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation +system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 5 0.01% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14495 1 0.00% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15839 1 0.00% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 4 0.01% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18399 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18719 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18847 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18975 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19167 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 3 0.01% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19615 1 0.00% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20511 2 0.00% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21023 1 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21279 2 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21919 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22367 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 2 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24031 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24095 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24640-24671 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24799 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24863 1 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25311 1 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 2 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25887 2 0.00% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26271 1 0.00% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 3 0.01% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26911 1 0.00% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 3 0.01% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27743 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28191 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28639 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 2 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29599 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29727 3 0.01% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30303 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30495 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 3 0.01% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31007 2 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32031 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32159 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32543 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33055 2 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 1 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 6 0.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33631 2 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33695 1 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 44 0.10% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34591 2 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35231 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35871 2 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37535 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37919 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37983 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38943 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40287 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40991 3 0.01% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44575 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46111 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47647 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50207 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51231 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52255 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52992-53023 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53056-53087 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53760-53791 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54528-54559 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57344-57375 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57856-57887 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 2 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65119 8 0.02% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65247 18 0.04% 65.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65375 12 0.03% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation -system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests -system.physmem.totBusLat 75488575000 # Total cycles spent in databus access -system.physmem.totBankLat 15730536250 # Total cycles spent in bank access -system.physmem.avgQLat 23521.25 # Average queueing delay per request -system.physmem.avgBankLat 1041.92 # Average bank access latency per request +system.physmem.bytesPerActivate::159168-159199 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation +system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests +system.physmem.totBusLat 75504790000 # Total cycles spent in databus access +system.physmem.totBankLat 15713238750 # Total cycles spent in bank access +system.physmem.avgQLat 23320.54 # Average queueing delay per request +system.physmem.avgBankLat 1040.55 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29563.16 # Average memory access latency -system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 29361.08 # Average memory access latency +system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 11.71 # Average write queue length over time -system.physmem.readRowHits 15070837 # Number of row buffer hits during reads -system.physmem.writeRowHits 797438 # Number of row buffer hits during writes +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 10.77 # Average write queue length over time +system.physmem.readRowHits 15074158 # Number of row buffer hits during reads +system.physmem.writeRowHits 797610 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes -system.physmem.avgGap 159276.56 # Average gap between requests +system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes +system.physmem.avgGap 159247.75 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -471,60 +461,60 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54705448 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16150672 # Transaction distribution -system.membus.trans_dist::ReadResp 16150669 # Transaction distribution +system.membus.throughput 54715776 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16153842 # Transaction distribution +system.membus.trans_dist::ReadResp 16153842 # Transaction distribution system.membus.trans_dist::WriteReq 763336 # Transaction distribution system.membus.trans_dist::WriteResp 763336 # Transaction distribution -system.membus.trans_dist::Writeback 59115 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution +system.membus.trans_dist::Writeback 59144 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution -system.membus.trans_dist::ReadExReq 131424 # Transaction distribution -system.membus.trans_dist::ReadExResp 131424 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution +system.membus.trans_dist::ReadExReq 131438 # Transaction distribution +system.membus.trans_dist::ReadExResp 131438 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138638877 # Total data (bytes) +system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138667961 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -532,13 +522,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48115298 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution -system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution +system.iobus.throughput 48124265 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution +system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution system.iobus.trans_dist::WriteReq 8158 # Transaction distribution system.iobus.trans_dist::WriteResp 8158 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -560,11 +550,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -586,10 +576,10 @@ system.iobus.pkt_count::system.realview.sci_fake.pio 16 system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -611,11 +601,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -637,12 +627,12 @@ system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121937597 # Total data (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121962881 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -686,44 +676,44 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.branchPred.lookups 14673159 # Number of BP lookups -system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits +system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu.branchPred.lookups 14663186 # Number of BP lookups +system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51397173 # DTB read hits -system.cpu.dtb.read_misses 63986 # DTB read misses -system.cpu.dtb.write_hits 11699533 # DTB write hits -system.cpu.dtb.write_misses 15890 # DTB write misses +system.cpu.dtb.read_hits 51389107 # DTB read hits +system.cpu.dtb.read_misses 64168 # DTB read misses +system.cpu.dtb.write_hits 11699261 # DTB write hits +system.cpu.dtb.write_misses 15977 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3558 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51461159 # DTB read accesses -system.cpu.dtb.write_accesses 11715423 # DTB write accesses +system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51453275 # DTB read accesses +system.cpu.dtb.write_accesses 11715238 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63096706 # DTB hits -system.cpu.dtb.misses 79876 # DTB misses -system.cpu.dtb.accesses 63176582 # DTB accesses -system.cpu.itb.inst_hits 12260245 # ITB inst hits -system.cpu.itb.inst_misses 11468 # ITB inst misses +system.cpu.dtb.hits 63088368 # DTB hits +system.cpu.dtb.misses 80145 # DTB misses +system.cpu.dtb.accesses 63168513 # DTB accesses +system.cpu.itb.inst_hits 12244686 # ITB inst hits +system.cpu.itb.inst_misses 11272 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -732,148 +722,148 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2492 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2481 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12271713 # ITB inst accesses -system.cpu.itb.hits 12260245 # DTB hits -system.cpu.itb.misses 11468 # DTB misses -system.cpu.itb.accesses 12271713 # DTB accesses -system.cpu.numCycles 475189978 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12255958 # ITB inst accesses +system.cpu.itb.hits 12244686 # DTB hits +system.cpu.itb.misses 11272 # DTB misses +system.cpu.itb.accesses 12255958 # DTB accesses +system.cpu.numCycles 475312551 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13589329 8.89% 79.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued @@ -886,397 +876,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued -system.cpu.iq.rate 0.261620 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued +system.cpu.iq.rate 0.261503 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221659 # number of nop insts executed -system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed -system.cpu.iew.exec_branches 11560329 # Number of branches executed -system.cpu.iew.exec_stores 12210910 # Number of stores executed -system.cpu.iew.exec_rate 0.255996 # Inst execution rate -system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47268053 # num instructions producing a value -system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value +system.cpu.iew.exec_nop 222537 # number of nop insts executed +system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed +system.cpu.iew.exec_branches 11556571 # Number of branches executed +system.cpu.iew.exec_stores 12211191 # Number of stores executed +system.cpu.iew.exec_rate 0.255895 # Inst execution rate +system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47268516 # num instructions producing a value +system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back +system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458274 # Number of instructions committed -system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458154 # Number of instructions committed +system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386690 # Number of memory references committed -system.cpu.commit.loads 15654575 # Number of loads committed -system.cpu.commit.membars 403596 # Number of memory barriers committed -system.cpu.commit.branches 9961373 # Number of branches committed +system.cpu.commit.refs 27386643 # Number of memory references committed +system.cpu.commit.loads 15654562 # Number of loads committed +system.cpu.commit.membars 403601 # Number of memory barriers committed +system.cpu.commit.branches 9961356 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68855105 # Number of committed integer instructions. -system.cpu.commit.function_calls 991268 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854920 # Number of committed integer instructions. +system.cpu.commit.function_calls 991265 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243879966 # The number of ROB reads -system.cpu.rob.rob_writes 201882555 # The number of ROB writes -system.cpu.timesIdled 1780421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322302334 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593285278 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307893 # Number of Instructions Simulated -system.cpu.committedOps 77599512 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307893 # Number of Instructions Simulated -system.cpu.cpi 7.879399 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.879399 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126913 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126913 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550704700 # number of integer regfile reads -system.cpu.int_regfile_writes 88578312 # number of integer regfile writes -system.cpu.fp_regfile_reads 8302 # number of floating regfile reads -system.cpu.fp_regfile_writes 2882 # number of floating regfile writes -system.cpu.misc_regfile_reads 30116391 # number of misc regfile reads +system.cpu.rob.rob_reads 243752783 # The number of ROB reads +system.cpu.rob.rob_writes 201807644 # The number of ROB writes +system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307773 # Number of Instructions Simulated +system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated +system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550637144 # number of integer regfile reads +system.cpu.int_regfile_writes 88566595 # number of integer regfile writes +system.cpu.fp_regfile_reads 8370 # number of floating regfile reads +system.cpu.fp_regfile_writes 2906 # number of floating regfile writes +system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads system.cpu.misc_regfile_writes 831896 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58661050 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657246 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657245 # Transaction distribution +system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607669 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246055 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1960500 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5796171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30982 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7913971 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62698816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85512245 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 42284 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 208804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148462149 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148462149 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 201328 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128322117 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1471549889 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474731013 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2533210636 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2562590429 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20419483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20135737 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74237753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74394752 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 980157 # number of replacements -system.cpu.icache.tagsinuse 511.579914 # Cycle average of tags in use -system.cpu.icache.total_refs 11196212 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980669 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.416912 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6837358000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.579914 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999180 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11196212 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11196212 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11196212 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11196212 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11196212 # number of overall hits -system.cpu.icache.overall_hits::total 11196212 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060409 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060409 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060409 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060409 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060409 # number of overall misses -system.cpu.icache.overall_misses::total 1060409 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14257699991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14257699991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14257699991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14257699991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14257699991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14257699991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12256621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12256621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12256621 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12256621 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12256621 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12256621 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086517 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086517 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086517 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086517 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086517 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13445.472446 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13445.472446 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13445.472446 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13445.472446 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked +system.cpu.icache.tags.replacements 980590 # number of replacements +system.cpu.icache.tags.tagsinuse 511.580932 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11180201 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981102 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.395554 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6861342250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.580932 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11180201 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11180201 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11180201 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11180201 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11180201 # number of overall hits +system.cpu.icache.overall_hits::total 11180201 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060929 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060929 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060929 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060929 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060929 # number of overall misses +system.cpu.icache.overall_misses::total 1060929 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14286603183 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14286603183 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14286603183 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14286603183 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14286603183 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14286603183 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12241130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12241130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12241130 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12241130 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12241130 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12241130 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086669 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086669 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086669 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086669 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086669 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086669 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13466.125615 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13466.125615 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13466.125615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13466.125615 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8464 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 372 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 385 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.473118 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.984416 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79698 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79698 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79698 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79698 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79698 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79698 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980711 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980711 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980711 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980711 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980711 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980711 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583440602 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11583440602 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583440602 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11583440602 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583440602 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11583440602 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9547000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9547000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9547000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 9547000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080015 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26354291876 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26354291876 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 7076250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193278593876 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193285670126 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016014 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985165 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985165 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541421 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541421 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012604 # 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mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.092654 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61214.751905 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.118744 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61930.328272 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.343407 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.343407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61664.831606 # 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average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1397,161 +1387,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643353 # number of replacements -system.cpu.dcache.tagsinuse 511.992092 # Cycle average of tags in use -system.cpu.dcache.total_refs 21505591 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643865 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.400777 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 48193000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.992092 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13753583 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13753583 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258444 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258444 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242854 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242854 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21012027 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21012027 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21012027 # 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number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256439 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256439 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24705277 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24705277 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24705277 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24705277 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050837 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050837 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289871 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289871 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052831 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052831 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149742 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149742 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149742 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149742 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13687.983840 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13687.983840 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45454.842720 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45454.842720 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13619.740921 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15206.058824 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15206.058824 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39132.578126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39132.578126 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32140 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25391 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2640 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 284 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.174242 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.404930 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607669 # number of writebacks -system.cpu.dcache.writebacks::total 607669 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351798 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351798 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715004 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2715004 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066802 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066802 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066802 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066802 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385700 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385700 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248938 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607541 # number of writebacks +system.cpu.dcache.writebacks::total 607541 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350669 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350669 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714279 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064948 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064948 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064948 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064948 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385593 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385593 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248882 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248882 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12204 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12204 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634475 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634475 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634475 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967192840 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967192840 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10605079278 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10605079278 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144959500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144959500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 224497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 224497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15572272118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15572272118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15572272118 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15572272118 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182317512000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182317512000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35728890492 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35728890492 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218046402492 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218046402492 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024347 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024347 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.958023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.958023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42610.872936 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42610.872936 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11878.031793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11878.031793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13205.705882 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13205.705882 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1559,12 +1549,12 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1573,16 +1563,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index edfc62ccf..2906c8c25 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,165 +1,165 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401127 # Number of seconds simulated -sim_ticks 2401127269500 # Number of ticks simulated -final_tick 2401127269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403594 # Number of seconds simulated +sim_ticks 2403594294500 # Number of ticks simulated +final_tick 2403594294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142330 # Simulator instruction rate (inst/s) -host_op_rate 182788 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5664980832 # Simulator tick rate (ticks/s) -host_mem_usage 401540 # Number of bytes of host memory used -host_seconds 423.85 # Real time elapsed on the host -sim_insts 60327009 # Number of instructions simulated -sim_ops 77475387 # Number of ops (including micro ops) simulated +host_inst_rate 127977 # Simulator instruction rate (inst/s) +host_op_rate 164357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5098961801 # Simulator tick rate (ticks/s) +host_mem_usage 401544 # Number of bytes of host memory used +host_seconds 471.39 # Real time elapsed on the host +sim_insts 60327163 # Number of instructions simulated +sim_ops 77476179 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7145552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 511136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7143248 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 78912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 687680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 688768 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 173184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1243936 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 78912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 173184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3744064 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1523456 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 157860 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1334500 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759880 # Number of bytes written to this memory +system.physmem.bytes_read::cpu2.inst 171584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1244640 # Number of bytes read from this memory +system.physmem.bytes_read::total 124657616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 511136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 171584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 761248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3742592 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1523692 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 157804 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1334320 # Number of bytes written to this memory +system.physmem.bytes_written::total 6758408 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 111683 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14189 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 111647 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1233 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10762 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2706 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 19444 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512400 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58501 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380864 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39465 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 333625 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812455 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47818820 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.inst 2681 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 19455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512355 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58478 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380923 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39451 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 333580 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812432 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47769739 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2975916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 212655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2971903 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 286399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 286558 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 72126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 518063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51917488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32865 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 72126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318024 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1559294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 634475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 65744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 555781 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2815294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1559294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47818820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 71386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 517824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 212655 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 71386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557081 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 633922 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 65653 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 555135 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2811792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47769739 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3610391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 212655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3605825 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 352143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 32671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 352211 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 72126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1073844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54732782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12420439 # Total number of read requests seen -system.physmem.writeReqs 390212 # Total number of write requests seen -system.physmem.cpureqs 53603 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 794908096 # Total number of bytes read from memory -system.physmem.bytesWritten 24973568 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 101274592 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2588168 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2354 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 776339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 775940 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 776092 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 776425 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 777292 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 776809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 775620 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 775424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 775584 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 776041 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 775688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 776201 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 777483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 777433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 776149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 775918 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 25457 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 25320 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 25407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25903 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 26305 # Track writes on a per bank basis +system.physmem.bw_total::cpu2.inst 71386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1072960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54674794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13478004 # Total number of read requests seen +system.physmem.writeReqs 390132 # Total number of write requests seen +system.physmem.cpureqs 53582 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 862592256 # Total number of bytes read from memory +system.physmem.bytesWritten 24968448 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 109734944 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2586588 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2357 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 837777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 837385 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 837533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 838713 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 839756 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 839804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 839650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 840522 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 841715 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 844141 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 844930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 846498 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 848135 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 848079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 846803 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 846563 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 25455 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 25327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 25409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 26300 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 26088 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 25428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 23374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 23183 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 23262 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 21306 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 21574 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24259 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 23496 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25221 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 25421 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 23356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 23184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 23261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 21260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 21580 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24253 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 23500 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25208 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 14413 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400092064000 # Total gap between requests +system.physmem.totGap 2402559124000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 8 # Categorize read packet sizes -system.physmem.readPktSize::3 12386304 # Categorize read packet sizes +system.physmem.readPktSize::3 13443872 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 34127 # Categorize read packet sizes +system.physmem.readPktSize::6 34124 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 373090 # Categorize write packet sizes +system.physmem.writePktSize::2 373031 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17122 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 803531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 778993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 809862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3060255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2298083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2298065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2262695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 12148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 12111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 22591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 22584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17101 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 870514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 846629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 868006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3320451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2492641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2492474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2466384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 13526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 25989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 38321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 25827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -173,161 +173,191 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 16974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 16970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 16964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 16959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 16952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 16947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 16934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 16973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 16965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 16963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 16956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 16951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 16946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 16941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 16929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16918 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 14497 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 14485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14472 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 14454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14453 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 14449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14427 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 39302.074493 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 6009.687839 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33098.413312 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 3004 14.40% 14.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 1328 6.37% 20.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 811 3.89% 24.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 565 2.71% 27.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 381 1.83% 29.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 362 1.74% 30.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 265 1.27% 32.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 238 1.14% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 172 0.82% 34.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 151 0.72% 34.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 130 0.62% 35.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 127 0.61% 36.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 66 0.32% 36.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 86 0.41% 36.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 45 0.22% 37.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 78 0.37% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 36 0.17% 37.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 26 0.12% 37.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 22 0.11% 37.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 43 0.21% 38.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 28 0.13% 38.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 87 0.42% 38.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 101 0.48% 39.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 96 0.46% 39.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 23 0.11% 39.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 38 0.18% 39.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 20 0.10% 39.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 38 0.18% 40.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 12 0.06% 40.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 22 0.11% 40.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 8 0.04% 40.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 17 0.08% 40.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 10 0.05% 40.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 9 0.04% 40.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 4 0.02% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 3 0.01% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 5 0.02% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 9 0.04% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 4 0.02% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 4 0.02% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 2 0.01% 40.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 2 0.01% 40.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 6 0.03% 40.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 3 0.01% 40.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 7 0.03% 40.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 1 0.00% 40.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 2 0.01% 40.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 4 0.02% 40.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 1 0.00% 40.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 3 0.01% 40.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 3 0.01% 40.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 8 0.04% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 2 0.01% 40.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 3 0.01% 40.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 1 0.00% 40.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 3 0.01% 40.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 2 0.01% 40.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 2 0.01% 40.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 2 0.01% 40.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 1 0.00% 40.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 1 0.00% 40.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 1 0.00% 40.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 6 0.03% 40.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 2 0.01% 40.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 3 0.01% 40.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 40.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 2 0.01% 40.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 2 0.01% 40.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 1 0.00% 40.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 1 0.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 1 0.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 1 0.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 1 0.00% 41.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 1 0.00% 41.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 4 0.02% 41.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 1 0.00% 41.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 2 0.01% 41.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 1 0.00% 41.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 2 0.01% 41.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 1 0.00% 41.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 2 0.01% 41.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 41.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 41.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 1 0.00% 41.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 2 0.01% 41.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11167 1 0.00% 41.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 1 0.00% 41.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 41.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15199 1 0.00% 41.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 41.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 1 0.00% 41.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31007 1 0.00% 41.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 2 0.01% 41.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 1 0.00% 41.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 12093 57.97% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::127424-127455 1 0.00% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 181 0.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20861 # Bytes accessed per row activation -system.physmem.totQLat 241895050750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 315493767000 # Sum of mem lat for all requests -system.physmem.totBusLat 62102190000 # Total cycles spent in databus access -system.physmem.totBankLat 11496526250 # Total cycles spent in bank access -system.physmem.avgQLat 19475.57 # Average queueing delay per request -system.physmem.avgBankLat 925.61 # Average bank access latency per request +system.physmem.wrQLenPdf::29 14444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14424 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 22008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 40328.985823 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 6672.817905 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32794.691650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 2992 13.60% 13.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 1338 6.08% 19.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 840 3.82% 23.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 568 2.58% 26.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 356 1.62% 27.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 350 1.59% 29.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 274 1.25% 30.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 258 1.17% 31.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 159 0.72% 32.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 152 0.69% 33.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 129 0.59% 33.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 166 0.75% 34.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 85 0.39% 34.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 79 0.36% 35.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 56 0.25% 35.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 66 0.30% 35.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 41 0.19% 35.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 34 0.15% 36.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 24 0.11% 36.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 38 0.17% 36.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 28 0.13% 36.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 94 0.43% 36.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 111 0.50% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 95 0.43% 37.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 19 0.09% 37.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 37 0.17% 38.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 24 0.11% 38.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 40 0.18% 38.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 12 0.05% 38.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 17 0.08% 38.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 8 0.04% 38.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 19 0.09% 38.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 12 0.05% 38.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 11 0.05% 38.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 5 0.02% 38.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 5 0.02% 38.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 3 0.01% 38.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 10 0.05% 38.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 2 0.01% 38.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 1 0.00% 38.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 1 0.00% 38.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 5 0.02% 38.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 5 0.02% 38.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 5 0.02% 38.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 3 0.01% 38.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 1 0.00% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 1 0.00% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 7 0.03% 39.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 2 0.01% 39.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 3 0.01% 39.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 4 0.02% 39.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 7 0.03% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 2 0.01% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 2 0.01% 39.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 3 0.01% 39.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 2 0.01% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 1 0.00% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 2 0.01% 39.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 3 0.01% 39.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 3 0.01% 39.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 7 0.03% 39.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 3 0.01% 39.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 1 0.00% 39.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 39.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 2 0.01% 39.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 3 0.01% 39.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 1 0.00% 39.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 1 0.00% 39.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 1 0.00% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.01% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 2 0.01% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 8 0.04% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 1 0.00% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 1 0.00% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 1 0.00% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 4 0.02% 39.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 2 0.01% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 2 0.01% 39.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 1 0.00% 39.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 2 0.01% 39.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 1 0.00% 39.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 1 0.00% 39.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 2 0.01% 39.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 1 0.00% 39.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 3 0.01% 39.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8479 1 0.00% 39.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8607 1 0.00% 39.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 1 0.00% 39.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 3 0.01% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 1 0.00% 39.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13983 1 0.00% 39.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 1 0.00% 39.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19231 1 0.00% 39.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 1 0.00% 39.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19999 1 0.00% 39.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21791 1 0.00% 39.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 2 0.01% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23327 1 0.00% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 1 0.00% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28191 1 0.00% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 1 0.00% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32031 2 0.01% 39.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33055 2 0.01% 39.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 2 0.01% 39.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 2 0.01% 39.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 1 0.00% 39.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34847 1 0.00% 39.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35871 1 0.00% 39.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36895 1 0.00% 39.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37919 1 0.00% 39.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38943 1 0.00% 39.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40991 1 0.00% 39.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 1 0.00% 39.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42783 1 0.00% 39.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46111 1 0.00% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49439 1 0.00% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50975 1 0.00% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 39.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54303 1 0.00% 39.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54464-54495 1 0.00% 39.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56576-56607 1 0.00% 39.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58240-58271 1 0.00% 39.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58624-58655 1 0.00% 39.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59423 1 0.00% 39.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 13106 59.55% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 181 0.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22008 # Bytes accessed per row activation +system.physmem.totQLat 259991264250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 339839911750 # Sum of mem lat for all requests +system.physmem.totBusLat 67390020000 # Total cycles spent in databus access +system.physmem.totBankLat 12458627500 # Total cycles spent in bank access +system.physmem.avgQLat 19290.04 # Average queueing delay per request +system.physmem.avgBankLat 924.37 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25401.18 # Average memory access latency -system.physmem.avgRdBW 331.06 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.40 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.18 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 25214.41 # Average memory access latency +system.physmem.avgRdBW 358.88 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 45.65 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.08 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.67 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.busUtil 2.88 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.14 # Average read queue length over time system.physmem.avgWrQLen 0.40 # Average write queue length over time -system.physmem.readRowHits 12404411 # Number of row buffer hits during reads -system.physmem.writeRowHits 385376 # Number of row buffer hits during writes +system.physmem.readRowHits 13460829 # Number of row buffer hits during reads +system.physmem.writeRowHits 385299 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.76 # Row buffer hit rate for writes -system.physmem.avgGap 187351.30 # Average gap between requests +system.physmem.avgGap 173243.12 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -340,315 +370,315 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55731119 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 12759502 # Transaction distribution -system.membus.trans_dist::ReadResp 12759502 # Transaction distribution -system.membus.trans_dist::WriteReq 375940 # Transaction distribution -system.membus.trans_dist::WriteResp 375940 # Transaction distribution -system.membus.trans_dist::Writeback 17122 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2354 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2354 # Transaction distribution -system.membus.trans_dist::ReadExReq 26440 # Transaction distribution -system.membus.trans_dist::ReadExResp 26440 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736482 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 224 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1572986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 24772608 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 24772608 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 736482 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 25608888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 224 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 26345594 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740439 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4772328 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5513215 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 99090432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 99090432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 740439 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 103862760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 104603647 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133817510 # Total data (bytes) +system.membus.throughput 55672102 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13817032 # Transaction distribution +system.membus.trans_dist::ReadResp 13817032 # Transaction distribution +system.membus.trans_dist::WriteReq 375870 # Transaction distribution +system.membus.trans_dist::WriteResp 375870 # Transaction distribution +system.membus.trans_dist::Writeback 17101 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2357 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2357 # Transaction distribution +system.membus.trans_dist::ReadExReq 26474 # Transaction distribution +system.membus.trans_dist::ReadExResp 26474 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736448 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836141 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1572823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887744 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26887744 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 736448 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 27723885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28460567 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4770556 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5511420 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550976 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107550976 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 112321532 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113062396 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133813146 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 420513000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 415491000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 13413227250 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 14469192250 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.reqLayer3.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 218000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1495675396 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1494318294 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 27962648500 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.replacements 63244 # number of replacements -system.l2c.tagsinuse 50337.430960 # Cycle average of tags in use -system.l2c.total_refs 1749337 # Total number of references to valid blocks. -system.l2c.sampled_refs 128639 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.598808 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374950539000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36831.801957 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5222.807479 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3773.258681 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.993312 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 729.926692 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 767.531716 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 5.853930 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1434.252547 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1571.004504 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.562009 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.079694 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057575 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.011138 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011712 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000089 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.021885 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.023972 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768088 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9056 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3360 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 461135 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166289 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 135286 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65788 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18369 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4267 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 282351 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 141179 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290913 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597640 # number of Writeback hits -system.l2c.Writeback_hits::total 597640 # number of Writeback hits +system.membus.respLayer2.occupancy 30346616000 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.l2c.tags.replacements 63199 # number of replacements +system.l2c.tags.tagsinuse 50350.442050 # Cycle average of tags in use +system.l2c.tags.total_refs 1748255 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128595 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.595046 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375554811500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36868.064409 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5218.650868 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3758.862884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 721.252750 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 766.461515 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 4.929404 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1435.478788 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1575.747972 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562562 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079630 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.057356 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011005 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011695 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000075 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.021904 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768287 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8900 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3220 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 462102 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166367 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2587 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1159 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 134524 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 65754 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18045 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4210 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 282039 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 141097 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290004 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597664 # number of Writeback hits +system.l2c.Writeback_hits::total 597664 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60771 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19509 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33371 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113651 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9056 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3360 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 461135 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 227060 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 135286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 85297 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18369 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4267 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 282351 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 174550 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404564 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9056 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3360 # number of overall hits -system.l2c.overall_hits::cpu0.inst 461135 # number of overall hits -system.l2c.overall_hits::cpu0.data 227060 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2625 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1208 # number of overall hits -system.l2c.overall_hits::cpu1.inst 135286 # number of overall hits -system.l2c.overall_hits::cpu1.data 85297 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60302.311436 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51699.757372 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65644.401330 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 58211.212881 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56811.908735 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60051.344743 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52409.126121 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 67371.036927 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 58144.499451 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57112.994971 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -801,52 +831,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58868329 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1038711 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1038710 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 375940 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 375940 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 275281 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1501 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1503 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80190 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80190 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 843862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2343005 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15512 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 51160 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 3253539 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26980864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38469375 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21900 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 84004 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 65556143 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141250094 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 100256 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2175069728 # Layer occupancy (ticks) +system.toL2Bus.throughput 58801079 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1037457 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1037456 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 375870 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 375870 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 275194 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1507 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80165 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80165 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 841603 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2342492 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15419 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50807 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 3250321 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26910144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38454204 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21476 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 82556 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 65468380 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141234858 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 99080 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2173969472 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1900577406 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1896208409 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1863798035 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1871332229 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10055959 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10065963 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30318675 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30326428 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48814240 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 12751762 # Transaction distribution -system.iobus.trans_dist::ReadResp 12751762 # Transaction distribution -system.iobus.trans_dist::WriteReq 2783 # Transaction distribution -system.iobus.trans_dist::WriteResp 2783 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48764132 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13809327 # Transaction distribution +system.iobus.trans_dist::ReadResp 13809327 # Transaction distribution +system.iobus.trans_dist::WriteReq 2769 # Transaction distribution +system.iobus.trans_dist::WriteResp 2769 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -862,17 +892,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 736482 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 24772608 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 736448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26887744 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -888,16 +918,16 @@ system.iobus.pkt_count::system.realview.sci_fake.pio 16 system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 25509090 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27624192 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -913,17 +943,17 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 740439 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 99090432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 740396 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550976 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -939,14 +969,14 @@ system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 99830871 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209202 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7987000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108291372 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209190 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7942000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1551000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1545000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 131000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -956,7 +986,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 361193000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 361211000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -988,34 +1018,34 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 12386304000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 733699000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13443872000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 733679000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 24772608000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 36855511000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8064428 # DTB read hits -system.cpu0.dtb.read_misses 6238 # DTB read misses -system.cpu0.dtb.write_hits 6663212 # DTB write hits -system.cpu0.dtb.write_misses 2045 # DTB write misses +system.cpu0.dtb.read_hits 8066197 # DTB read hits +system.cpu0.dtb.read_misses 6232 # DTB read misses +system.cpu0.dtb.write_hits 6664992 # DTB write hits +system.cpu0.dtb.write_misses 2050 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5690 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5697 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 114 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 113 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8070666 # DTB read accesses -system.cpu0.dtb.write_accesses 6665257 # DTB write accesses +system.cpu0.dtb.read_accesses 8072429 # DTB read accesses +system.cpu0.dtb.write_accesses 6667042 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14727640 # DTB hits -system.cpu0.dtb.misses 8283 # DTB misses -system.cpu0.dtb.accesses 14735923 # DTB accesses -system.cpu0.itb.inst_hits 32885888 # ITB inst hits +system.cpu0.dtb.hits 14731189 # DTB hits +system.cpu0.dtb.misses 8282 # DTB misses +system.cpu0.dtb.accesses 14739471 # DTB accesses +system.cpu0.itb.inst_hits 32886560 # ITB inst hits system.cpu0.itb.inst_misses 3493 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1023,409 +1053,409 @@ system.cpu0.itb.write_hits 0 # DT system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2597 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2599 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32889381 # ITB inst accesses -system.cpu0.itb.hits 32885888 # DTB hits +system.cpu0.itb.inst_accesses 32890053 # ITB inst accesses +system.cpu0.itb.hits 32886560 # DTB hits system.cpu0.itb.misses 3493 # DTB misses -system.cpu0.itb.accesses 32889381 # DTB accesses -system.cpu0.numCycles 114194187 # number of cpu cycles simulated +system.cpu0.itb.accesses 32890053 # DTB accesses +system.cpu0.numCycles 114224752 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32400694 # Number of instructions committed -system.cpu0.committedOps 42604041 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37748945 # Number of integer alu accesses +system.cpu0.committedInsts 32403519 # Number of instructions committed +system.cpu0.committedOps 42610516 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37756553 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses -system.cpu0.num_func_calls 1185552 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4241024 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37748945 # number of integer instructions +system.cpu0.num_func_calls 1186218 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4240514 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37756553 # number of integer instructions system.cpu0.num_fp_insts 5021 # number of float instructions -system.cpu0.num_int_register_reads 192241357 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39867524 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192274568 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39869839 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written -system.cpu0.num_mem_refs 15390684 # number of memory refs -system.cpu0.num_load_insts 8430090 # Number of load instructions -system.cpu0.num_store_insts 6960594 # Number of store instructions -system.cpu0.num_idle_cycles 13437222906.022394 # Number of idle cycles -system.cpu0.num_busy_cycles -13323028719.022394 # Number of busy cycles -system.cpu0.not_idle_fraction -116.669938 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.669938 # Percentage of idle cycles +system.cpu0.num_mem_refs 15395098 # number of memory refs +system.cpu0.num_load_insts 8432454 # Number of load instructions +system.cpu0.num_store_insts 6962644 # Number of store instructions +system.cpu0.num_idle_cycles 13455441823.416426 # Number of idle cycles +system.cpu0.num_busy_cycles -13341217071.416426 # Number of busy cycles +system.cpu0.not_idle_fraction -116.797952 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.797952 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.replacements 891212 # number of replacements -system.cpu0.icache.tagsinuse 511.602596 # Cycle average of tags in use -system.cpu0.icache.total_refs 44302670 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 891724 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.682043 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8165076000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 482.545707 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 22.025938 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 7.030951 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.942472 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.043019 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.013732 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32419122 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8206609 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3676939 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44302670 # 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average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11885.964647 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11791.549509 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11593.611217 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11885.964647 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11791.549509 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11593.611217 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11885.964647 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11791.549509 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 629902 # number of replacements -system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23235714 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630414 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.857865 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.218177 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 10.352055 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.426883 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.967223 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.020219 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012553 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999994 # 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Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.020306 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013257 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6949237 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1880036 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4481409 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13310682 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5977872 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1354370 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2102552 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9434794 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131076 # 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number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3867 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11962 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334632 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 95009 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 869657 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1299298 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 334632 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 95009 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 869657 # number of overall misses -system.cpu0.dcache.overall_misses::total 1299298 # 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number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1387041 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2684743 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216354 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137233 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 36022 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77346 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250601 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137233 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 36022 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74135 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247390 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13258635 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3332693 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7454666 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24045994 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13258635 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3332693 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7454666 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24045994 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023387 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033512 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.060278 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037535 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027383 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021489 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.216832 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.076367 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045966 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049609 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.049996 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047733 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # 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miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033504 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.060451 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037593 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027375 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021469 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.217253 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.076499 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045978 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049848 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050379 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047886 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3478998609 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5140341860 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27433716000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28893863250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56327579250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1437767401 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13930226833 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15367994234 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28871483401 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42824090083 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71695573484 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033504 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029403 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014852 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021469 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019323 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007989 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049848 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044720 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020904 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000041 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011936 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011936 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12256.839489 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12923.226949 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12711.800040 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29026.695305 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32109.403745 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30987.083191 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11123.954267 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.873473 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11369.050086 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1438,34 +1468,34 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2160353 # DTB read hits -system.cpu1.dtb.read_misses 2072 # DTB read misses -system.cpu1.dtb.write_hits 1463428 # DTB write hits -system.cpu1.dtb.write_misses 375 # DTB write misses +system.cpu1.dtb.read_hits 2159851 # DTB read hits +system.cpu1.dtb.read_misses 2083 # DTB read misses +system.cpu1.dtb.write_hits 1460405 # DTB write hits +system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1741 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1742 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 41 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 44 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2162425 # DTB read accesses -system.cpu1.dtb.write_accesses 1463803 # DTB write accesses +system.cpu1.dtb.read_accesses 2161934 # DTB read accesses +system.cpu1.dtb.write_accesses 1460778 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3623781 # DTB hits -system.cpu1.dtb.misses 2447 # DTB misses -system.cpu1.dtb.accesses 3626228 # DTB accesses -system.cpu1.itb.inst_hits 8343384 # ITB inst hits -system.cpu1.itb.inst_misses 1170 # ITB inst misses +system.cpu1.dtb.hits 3620256 # DTB hits +system.cpu1.dtb.misses 2456 # DTB misses +system.cpu1.dtb.accesses 3622712 # DTB accesses +system.cpu1.itb.inst_hits 8340023 # ITB inst hits +system.cpu1.itb.inst_misses 1172 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions @@ -1474,66 +1504,66 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8344554 # ITB inst accesses -system.cpu1.itb.hits 8343384 # DTB hits -system.cpu1.itb.misses 1170 # DTB misses -system.cpu1.itb.accesses 8344554 # DTB accesses -system.cpu1.numCycles 576594127 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8341195 # ITB inst accesses +system.cpu1.itb.hits 8340023 # DTB hits +system.cpu1.itb.misses 1172 # DTB misses +system.cpu1.itb.accesses 8341195 # DTB accesses +system.cpu1.numCycles 580203695 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8139213 # Number of instructions committed -system.cpu1.committedOps 10387341 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9296011 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses -system.cpu1.num_func_calls 319457 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1149983 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9296011 # number of integer instructions -system.cpu1.num_fp_insts 2143 # number of float instructions -system.cpu1.num_int_register_reads 53626328 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10059981 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read +system.cpu1.committedInsts 8134078 # Number of instructions committed +system.cpu1.committedOps 10379103 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9286356 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2127 # Number of float alu accesses +system.cpu1.num_func_calls 319009 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1149936 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9286356 # number of integer instructions +system.cpu1.num_fp_insts 2127 # number of float instructions +system.cpu1.num_int_register_reads 53580768 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10053974 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1614 # number of times the floating registers were read system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3800206 # number of memory refs -system.cpu1.num_load_insts 2257531 # Number of load instructions -system.cpu1.num_store_insts 1542675 # Number of store instructions -system.cpu1.num_idle_cycles 550949024.070645 # Number of idle cycles -system.cpu1.num_busy_cycles 25645102.929355 # Number of busy cycles -system.cpu1.not_idle_fraction 0.044477 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.955523 # Percentage of idle cycles +system.cpu1.num_mem_refs 3795930 # number of memory refs +system.cpu1.num_load_insts 2256544 # Number of load instructions +system.cpu1.num_store_insts 1539386 # Number of store instructions +system.cpu1.num_idle_cycles 585938491.751716 # Number of idle cycles +system.cpu1.num_busy_cycles -5734796.751716 # Number of busy cycles +system.cpu1.not_idle_fraction -0.009884 # Percentage of non-idle cycles +system.cpu1.idle_fraction 1.009884 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4706679 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3828645 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 220746 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3114772 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2519361 # Number of BTB hits +system.cpu2.branchPred.lookups 4707573 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3829869 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 221083 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3125328 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2519731 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.884283 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 411150 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21524 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.622930 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 410392 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21556 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10881090 # DTB read hits -system.cpu2.dtb.read_misses 22334 # DTB read misses -system.cpu2.dtb.write_hits 3233578 # DTB write hits -system.cpu2.dtb.write_misses 5962 # DTB write misses +system.cpu2.dtb.read_hits 10881991 # DTB read hits +system.cpu2.dtb.read_misses 22472 # DTB read misses +system.cpu2.dtb.write_hits 3235005 # DTB write hits +system.cpu2.dtb.write_misses 5987 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2292 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 695 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.flush_entries 2290 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 674 # Number of TLB faults due to alignment restrictions system.cpu2.dtb.prefetch_faults 165 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10903424 # DTB read accesses -system.cpu2.dtb.write_accesses 3239540 # DTB write accesses +system.cpu2.dtb.perms_faults 480 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10904463 # DTB read accesses +system.cpu2.dtb.write_accesses 3240992 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14114668 # DTB hits -system.cpu2.dtb.misses 28296 # DTB misses -system.cpu2.dtb.accesses 14142964 # DTB accesses -system.cpu2.itb.inst_hits 3988029 # ITB inst hits -system.cpu2.itb.inst_misses 4597 # ITB inst misses +system.cpu2.dtb.hits 14116996 # DTB hits +system.cpu2.dtb.misses 28459 # DTB misses +system.cpu2.dtb.accesses 14145455 # DTB accesses +system.cpu2.itb.inst_hits 3987789 # ITB inst hits +system.cpu2.itb.inst_misses 4600 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1542,114 +1572,114 @@ system.cpu2.itb.flush_tlb 276 # Nu system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1713 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1704 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 994 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1012 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 3992626 # ITB inst accesses -system.cpu2.itb.hits 3988029 # DTB hits -system.cpu2.itb.misses 4597 # DTB misses -system.cpu2.itb.accesses 3992626 # DTB accesses -system.cpu2.numCycles 88357796 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 3992389 # ITB inst accesses +system.cpu2.itb.hits 3987789 # DTB hits +system.cpu2.itb.misses 4600 # DTB misses +system.cpu2.itb.accesses 3992389 # DTB accesses +system.cpu2.numCycles 88356031 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9310481 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32575007 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4706679 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2930511 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6844695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1834626 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50535 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18792292 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 211 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 834 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32689 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 721380 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3986556 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 271694 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2030 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37012176 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.054575 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.442886 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9299223 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32583630 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4707573 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2930123 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6845670 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1836223 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50265 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18768642 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 865 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32747 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 722165 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3986309 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 272069 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2032 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36980430 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.055775 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.444098 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30172484 81.52% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 383589 1.04% 82.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 509700 1.38% 83.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 816595 2.21% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 649845 1.76% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 340688 0.92% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1002283 2.71% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 233105 0.63% 92.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2903887 7.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30139736 81.50% 81.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 382786 1.04% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 509834 1.38% 83.92% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 817196 2.21% 86.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 649833 1.76% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 340544 0.92% 88.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1001875 2.71% 91.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 233328 0.63% 92.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2905298 7.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37012176 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053268 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.368672 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9923582 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19398911 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6192413 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 289708 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1206624 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608704 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53227 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36668894 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 179672 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1206624 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10457732 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6796532 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11090349 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5929465 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1530564 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34717207 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2441 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 375073 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 892617 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 118 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37295857 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 158754403 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 158727276 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27127 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25598469 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11697387 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231672 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 208131 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3300393 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6518889 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3789656 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530954 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 691805 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31588093 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511099 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34136489 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54725 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7434189 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19599124 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 154239 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37012176 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.922304 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.578312 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36980430 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053280 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.368777 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9914058 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19374148 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6194025 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 289491 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1207748 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608647 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53413 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36680754 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 180211 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1207748 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10448619 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6814881 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11054882 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5930497 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1522855 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34729839 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2439 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 374808 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 885539 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 119 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37310430 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 158812282 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 158784890 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27392 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25602072 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11708357 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 230914 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207478 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3294482 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6519802 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3791560 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 528920 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 689934 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31598942 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 510602 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34143520 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55455 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7440971 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19631999 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 154198 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36980430 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.923286 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.579350 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24481195 66.14% 66.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3912173 10.57% 76.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2318887 6.27% 82.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2014061 5.44% 88.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2743513 7.41% 95.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 884212 2.39% 98.22% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 492586 1.33% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 130661 0.35% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34888 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24453619 66.13% 66.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3907365 10.57% 76.69% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2316831 6.27% 82.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2013006 5.44% 88.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2745101 7.42% 95.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 885827 2.40% 98.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 492123 1.33% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 131266 0.35% 99.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35292 0.10% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37012176 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36980430 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 18493 1.21% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 18547 1.21% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 1 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available @@ -1678,13 +1708,13 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1405660 91.60% 92.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110389 7.19% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1407485 91.52% 92.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 111832 7.27% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61311 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19306288 56.56% 56.74% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 26277 0.08% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61314 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19310512 56.56% 56.74% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 26216 0.08% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.81% # Type of FU issued @@ -1697,135 +1727,135 @@ system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.81% # Ty system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 7 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 4 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 4 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 369 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 372 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11344167 33.23% 90.05% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3398057 9.95% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11345203 33.23% 90.04% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3399891 9.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34136489 # Type of FU issued -system.cpu2.iq.rate 0.386344 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1534543 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044953 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 106895526 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39538518 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27366143 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7075 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3717 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3145 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35605938 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3783 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206498 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34143520 # Type of FU issued +system.cpu2.iq.rate 0.386431 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1537865 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.045041 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 106882112 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39555566 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27370238 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7010 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3779 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3144 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35616337 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3734 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206224 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1561517 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1841 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9166 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 566678 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1563789 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2001 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9138 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 567371 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5349938 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 380447 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5351721 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 380538 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1206624 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5097630 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 92333 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32182024 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61203 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6518889 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3789656 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 368677 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31621 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2335 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9166 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105355 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88176 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193531 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33238932 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11092763 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 897557 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1207748 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5118466 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 92736 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32192718 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 58170 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6519802 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3791560 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 368228 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31927 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2425 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9138 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105201 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88411 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193612 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33245955 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11093572 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 897565 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82832 # number of nop insts executed -system.cpu2.iew.exec_refs 14457569 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3671446 # Number of branches executed -system.cpu2.iew.exec_stores 3364806 # Number of stores executed -system.cpu2.iew.exec_rate 0.376186 # Inst execution rate -system.cpu2.iew.wb_sent 32811396 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27369288 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15602510 # num instructions producing a value -system.cpu2.iew.wb_consumers 28268763 # num instructions consuming a value +system.cpu2.iew.exec_nop 83174 # number of nop insts executed +system.cpu2.iew.exec_refs 14459722 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3671566 # Number of branches executed +system.cpu2.iew.exec_stores 3366150 # Number of stores executed +system.cpu2.iew.exec_rate 0.376273 # Inst execution rate +system.cpu2.iew.wb_sent 32817620 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27373382 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15610718 # num instructions producing a value +system.cpu2.iew.wb_consumers 28284338 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.309755 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.551935 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.309808 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.551921 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7374898 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356860 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 168297 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35805367 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.685358 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.714033 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7382656 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356404 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 168463 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35772498 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.686059 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.714745 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27231349 76.05% 76.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4142496 11.57% 87.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1257531 3.51% 91.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 645964 1.80% 92.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 562986 1.57% 94.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 317406 0.89% 95.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 386660 1.08% 96.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 302677 0.85% 97.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 958298 2.68% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27202420 76.04% 76.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4136400 11.56% 87.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1256838 3.51% 91.12% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 645513 1.80% 92.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 564789 1.58% 94.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 319868 0.89% 95.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 386889 1.08% 96.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 302652 0.85% 97.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 957129 2.68% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35805367 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19842604 # Number of instructions committed -system.cpu2.commit.committedOps 24539507 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35772498 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19845047 # Number of instructions committed +system.cpu2.commit.committedOps 24542041 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8180350 # Number of memory references committed -system.cpu2.commit.loads 4957372 # Number of loads committed -system.cpu2.commit.membars 94561 # Number of memory barriers committed -system.cpu2.commit.branches 3152552 # Number of branches committed -system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21772655 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294654 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 958298 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8180202 # Number of memory references committed +system.cpu2.commit.loads 4956013 # Number of loads committed +system.cpu2.commit.membars 94398 # Number of memory barriers committed +system.cpu2.commit.branches 3153060 # Number of branches committed +system.cpu2.commit.fp_insts 3107 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21774748 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294560 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 957129 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66237138 # The number of ROB reads -system.cpu2.rob.rob_writes 65080734 # The number of ROB writes -system.cpu2.timesIdled 362582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51345620 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3559271384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19787102 # Number of Instructions Simulated -system.cpu2.committedOps 24484005 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19787102 # Number of Instructions Simulated -system.cpu2.cpi 4.465424 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.465424 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.223943 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.223943 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153570043 # number of integer regfile reads -system.cpu2.int_regfile_writes 29228694 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22407 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes -system.cpu2.misc_regfile_reads 8993137 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241651 # number of misc regfile writes -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.rob.rob_reads 66215885 # The number of ROB reads +system.cpu2.rob.rob_writes 65102408 # The number of ROB writes +system.cpu2.timesIdled 362250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51375601 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3556629546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19789566 # Number of Instructions Simulated +system.cpu2.committedOps 24486560 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19789566 # Number of Instructions Simulated +system.cpu2.cpi 4.464779 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.464779 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.223975 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.223975 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153595531 # number of integer regfile reads +system.cpu2.int_regfile_writes 29235365 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22348 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20810 # number of floating regfile writes +system.cpu2.misc_regfile_reads 8997423 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241258 # number of misc regfile writes +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1834,10 +1864,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1181598504500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1181598504500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1279969503000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1279969503000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 1abf69682..c58b97d9e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,150 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.548434 # Number of seconds simulated -sim_ticks 2548433543500 # Number of ticks simulated -final_tick 2548433543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.548515 # Number of seconds simulated +sim_ticks 2548515380000 # Number of ticks simulated +final_tick 2548515380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62524 # Simulator instruction rate (inst/s) -host_op_rate 80452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2641694597 # Simulator tick rate (ticks/s) -host_mem_usage 403600 # Number of bytes of host memory used -host_seconds 964.70 # Real time elapsed on the host -sim_insts 60316814 # Number of instructions simulated -sim_ops 77611972 # Number of ops (including micro ops) simulated +host_inst_rate 61977 # Simulator instruction rate (inst/s) +host_op_rate 79748 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2618667230 # Simulator tick rate (ticks/s) +host_mem_usage 403588 # Number of bytes of host memory used +host_seconds 973.21 # Real time elapsed on the host +sim_insts 60316341 # Number of instructions simulated +sim_ops 77611368 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 441408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4859600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 357888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4231256 # Number of bytes read from this memory -system.physmem.bytes_read::total 131003368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 441408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 357888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1678512 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1337588 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799652 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 440128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4850064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 360448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4242200 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 440128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 360448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785088 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1679112 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1336988 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801188 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 19 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 75965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5592 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 66119 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293431 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 419628 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 334397 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47523518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 452 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6877 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 75816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66290 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293471 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59142 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 419778 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 334247 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813167 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47521992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 477 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 173208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1906897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 140435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1660336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51405448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 173208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 140435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 658645 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 524867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2668169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47523518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 172700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1903094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 141435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1664577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51404802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 172700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 141435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1485213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 658859 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 524614 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2668686 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1485213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47521992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 173208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2565541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 140435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2185203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54073617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293431 # Total number of read requests seen -system.physmem.writeReqs 813143 # Total number of write requests seen -system.physmem.cpureqs 218375 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978779584 # Total number of bytes read from memory -system.physmem.bytesWritten 52041152 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131003368 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799652 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955758 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955993 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955787 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955113 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956214 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 172700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2561953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 141435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2189191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54073488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293471 # Total number of read requests seen +system.physmem.writeReqs 813167 # Total number of write requests seen +system.physmem.cpureqs 218464 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978782144 # Total number of bytes read from memory +system.physmem.bytesWritten 52042688 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131005928 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801188 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4709 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 955865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955532 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 955892 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 955763 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955998 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955786 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955940 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955511 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956216 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956070 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955978 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48908 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51082 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51006 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51266 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51202 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51317 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51099 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50759 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50974 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51268 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51122 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 956077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49128 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50979 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51091 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51270 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51265 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51204 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51097 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50416 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51359 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51272 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51123 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32387 # Number of times wr buffer was full causing retry -system.physmem.totGap 2548432371500 # Total gap between requests +system.physmem.numWrRetry 32396 # Number of times wr buffer was full causing retry +system.physmem.totGap 2548513467000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 42 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154573 # Categorize read packet sizes +system.physmem.readPktSize::6 154613 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754025 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59118 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1060830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 986831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 991569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2806537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2806300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2762834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 14911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 40328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 3593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59142 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1060849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 987246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 977477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2806386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2806166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2776833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,222 +156,215 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2878 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32473 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32415 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40040 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 25744.741658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2072.132686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32880.697508 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 6923 17.29% 17.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3475 8.68% 25.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2293 5.73% 31.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1778 4.44% 36.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1271 3.17% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1070 2.67% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 793 1.98% 43.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 869 2.17% 46.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 551 1.38% 47.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 489 1.22% 48.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 420 1.05% 49.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 393 0.98% 50.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 261 0.65% 51.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 255 0.64% 52.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 183 0.46% 52.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 282 0.70% 53.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 123 0.31% 53.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 156 0.39% 53.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 102 0.25% 54.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 126 0.31% 54.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 80 0.20% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 383 0.96% 55.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 613 1.53% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 451 1.13% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 81 0.20% 58.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 160 0.40% 58.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 53 0.13% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 109 0.27% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 41 0.10% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 74 0.18% 59.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 65 0.16% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 23 0.06% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 42 0.10% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 15 0.04% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 29 0.07% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 18 0.04% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 27 0.07% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 12 0.03% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 7 0.02% 60.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 22 0.05% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 8 0.02% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 11 0.03% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 11 0.03% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 16 0.04% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 19 0.05% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 8 0.02% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 9 0.02% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 8 0.02% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 6 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 6 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 9 0.02% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 4 0.01% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 9 0.02% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 6 0.01% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 4 0.01% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 10 0.02% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 40 0.10% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 3 0.01% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 5 0.01% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 4 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 4 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 3 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 2 0.00% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 3 0.01% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 3 0.01% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 2 0.00% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 5 0.01% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 2 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 4 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 3 0.01% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5087 2 0.00% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 5 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 6 0.01% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.00% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 5 0.01% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 7 0.02% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 1 0.00% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5855 1 0.00% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 2 0.00% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 6 0.01% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 1 0.00% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 2 0.00% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6367 1 0.00% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 3 0.01% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 1 0.00% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 5 0.01% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 2 0.00% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 2 0.00% 61.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 2 0.00% 61.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 20 0.05% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 1 0.00% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 2 0.00% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 3 0.01% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 2 0.00% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 9 0.02% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7519 1 0.00% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 4 0.01% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 7 0.02% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 4 0.01% 61.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 7 0.02% 61.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 2 0.00% 61.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 309 0.77% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 1 0.00% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9695 1 0.00% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12831 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18975 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30623 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32031 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32799 2 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 6 0.01% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35359 1 0.00% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42975 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58143 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58624-58655 1 0.00% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61120-61151 1 0.00% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14762 36.87% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::123712-123743 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130048-130079 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.wrQLenPdf::30 32442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32421 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 25722.964516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2062.503898 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32877.713086 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 7020 17.52% 17.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3450 8.61% 26.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2302 5.74% 31.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1762 4.40% 36.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1221 3.05% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1083 2.70% 42.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 782 1.95% 43.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 826 2.06% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 552 1.38% 47.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 527 1.32% 48.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 441 1.10% 49.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 399 1.00% 50.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 278 0.69% 51.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 274 0.68% 52.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 181 0.45% 52.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 260 0.65% 53.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 121 0.30% 53.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 146 0.36% 53.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 103 0.26% 54.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 108 0.27% 54.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 77 0.19% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 372 0.93% 55.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 611 1.52% 57.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 461 1.15% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 86 0.21% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 174 0.43% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 54 0.13% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 96 0.24% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 48 0.12% 59.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 68 0.17% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 67 0.17% 59.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 19 0.05% 59.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 52 0.13% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 17 0.04% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 39 0.10% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 17 0.04% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 35 0.09% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 6 0.01% 60.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 5 0.01% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 15 0.04% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 12 0.03% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 19 0.05% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 10 0.02% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 19 0.05% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 14 0.03% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 5 0.01% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 6 0.01% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 5 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 3 0.01% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 12 0.03% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 10 0.02% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 3 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 8 0.02% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 7 0.02% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 6 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 7 0.02% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 35 0.09% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 5 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 2 0.00% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 3 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 7 0.02% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 4 0.01% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 5 0.01% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 1 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 7 0.02% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 7 0.02% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 3 0.01% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 5 0.01% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 4 0.01% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 2 0.00% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 2 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 5 0.01% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 4 0.01% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 5 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 1 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 1 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 2 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 4 0.01% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 3 0.01% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6367 2 0.00% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 5 0.01% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 3 0.01% 61.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 4 0.01% 61.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 61.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 21 0.05% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 4 0.01% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 2 0.00% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 3 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 5 0.01% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 2 0.00% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 3 0.01% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 1 0.00% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 6 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 1 0.00% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 7 0.02% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 7 0.02% 61.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 9 0.02% 61.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 3 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 305 0.76% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10143 1 0.00% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14111 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16735 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21023 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24799 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26143 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 1 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 2 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30431 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 5 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34847 1 0.00% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35167 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37663 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39455 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43167 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51487 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56832-56863 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60864-60895 1 0.00% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14763 36.84% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::126336-126367 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130496-130527 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131008-131039 1 0.00% 99.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::161280-161311 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::168384-168415 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::187392-187423 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::161792-161823 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::168960-168991 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::196608-196639 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40040 # Bytes accessed per row activation -system.physmem.totQLat 308881805250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 400754322750 # Sum of mem lat for all requests -system.physmem.totBusLat 76467100000 # Total cycles spent in databus access -system.physmem.totBankLat 15405417500 # Total cycles spent in bank access -system.physmem.avgQLat 20197.04 # Average queueing delay per request -system.physmem.avgBankLat 1007.32 # Average bank access latency per request +system.physmem.bytesPerActivate::total 40074 # Bytes accessed per row activation +system.physmem.totQLat 305431681500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 397314004000 # Sum of mem lat for all requests +system.physmem.totBusLat 76467280000 # Total cycles spent in databus access +system.physmem.totBankLat 15415042500 # Total cycles spent in bank access +system.physmem.avgQLat 19971.40 # Average queueing delay per request +system.physmem.avgBankLat 1007.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26204.36 # Average memory access latency -system.physmem.avgRdBW 384.07 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25979.35 # Average memory access latency +system.physmem.avgRdBW 384.06 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.41 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 1.10 # Average write queue length over time -system.physmem.readRowHits 15267875 # Number of row buffer hits during reads -system.physmem.writeRowHits 798648 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.11 # Average write queue length over time +system.physmem.readRowHits 15267858 # Number of row buffer hits during reads +system.physmem.writeRowHits 798688 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes -system.physmem.avgGap 158223.12 # Average gap between requests +system.physmem.avgGap 158227.53 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -384,289 +377,291 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55014580 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346067 # Transaction distribution -system.membus.trans_dist::ReadResp 16346070 # Transaction distribution +system.membus.throughput 55014417 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346104 # Transaction distribution +system.membus.trans_dist::ReadResp 16346107 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4682 # Transaction distribution +system.membus.trans_dist::Writeback 59142 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4707 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4684 # Transaction distribution -system.membus.trans_dist::ReadExReq 131411 # Transaction distribution -system.membus.trans_dist::ReadExResp 131411 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4709 # Transaction distribution +system.membus.trans_dist::ReadExReq 131412 # Transaction distribution +system.membus.trans_dist::ReadExResp 131412 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885920 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272668 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32163398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32163552 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550150 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550300 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692492 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696588 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19090473 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19094561 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 137803020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 137807116 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140201001 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140201001 # Total data (bytes) +system.membus.tot_pkt_size::total 140205089 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140205089 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1492522500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1476111500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17540815750 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17555240750 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3583500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3581500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4705924038 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4707147287 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34177393245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34172276993 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.replacements 64346 # number of replacements -system.l2c.tagsinuse 51424.069961 # Cycle average of tags in use -system.l2c.total_refs 1905385 # Total number of references to valid blocks. -system.l2c.sampled_refs 129735 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.686746 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2511358439500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36974.185132 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 11.366489 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000367 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4621.370879 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3355.179290 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 15.725461 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3578.652286 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2867.590058 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.564181 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000173 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.070517 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.051196 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000240 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.054606 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.043756 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784669 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 33086 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6984 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 499528 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 184262 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6676 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 472129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 203355 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1436386 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits -system.l2c.Writeback_hits::total 608398 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 21 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 36 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57570 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55424 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112994 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 33086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6984 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 499528 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 241832 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30366 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6676 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 472129 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 258779 # number of demand (read+write) hits -system.l2c.demand_hits::total 1549380 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 33086 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6984 # number of overall hits -system.l2c.overall_hits::cpu0.inst 499528 # number of overall hits -system.l2c.overall_hits::cpu0.data 241832 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30366 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6676 # number of overall hits -system.l2c.overall_hits::cpu1.inst 472129 # number of overall hits -system.l2c.overall_hits::cpu1.data 258779 # number of overall hits -system.l2c.overall_hits::total 1549380 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 18 # number of ReadReq misses +system.l2c.tags.replacements 64386 # number of replacements +system.l2c.tags.tagsinuse 51442.070809 # Cycle average of tags in use +system.l2c.tags.total_refs 1905390 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129776 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.682145 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2511428822500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36972.715861 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.496871 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000368 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4611.296465 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3332.598424 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.513991 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3606.043873 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2894.404957 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564159 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070363 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050851 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.055024 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044165 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784944 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 33100 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6967 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 497324 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 183110 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30320 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6628 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 474382 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 204508 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1436339 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608377 # number of Writeback hits +system.l2c.Writeback_hits::total 608377 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 25 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 20 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58192 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54720 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112912 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 33100 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6967 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 497324 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 241302 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30320 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6628 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 474382 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 259228 # number of demand (read+write) hits +system.l2c.demand_hits::total 1549251 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 33100 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6967 # number of overall hits +system.l2c.overall_hits::cpu0.inst 497324 # number of overall hits +system.l2c.overall_hits::cpu0.data 241302 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30320 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6628 # number of overall hits +system.l2c.overall_hits::cpu1.inst 474382 # number of overall hits +system.l2c.overall_hits::cpu1.data 259228 # number of overall hits +system.l2c.overall_hits::total 1549251 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 19 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6786 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6144 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 22 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5600 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4553 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 84168652000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166932224750 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 13405485754 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 10155458000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 23560943754 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6781750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 96097654029 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 94391718749 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 190496154528 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000286 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013395 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032053 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011705 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021779 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015791 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986607 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989146 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.987797 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.551471 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.529588 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.540998 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000286 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013395 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.241204 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011705 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.205460 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091591 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000286 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013395 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.241204 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011705 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.205460 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091591 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6768250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 96162290254 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 94324110000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190493168504 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032089 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021902 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015818 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.983964 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.985836 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.984854 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.548497 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.533185 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541204 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.241317 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.205558 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091627 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.241317 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.205558 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091627 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61674.135507 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62787.378534 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61810.745390 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10005.201034 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.731529 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.573439 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60817.646245 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64195.633188 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61853.395911 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.303781 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.683527 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56143.257661 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55885.895105 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56022.680137 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56090.553308 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56116.480736 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56102.719595 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -861,49 +852,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58505331 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677704 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677706 # Transaction distribution +system.toL2Bus.throughput 58503668 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677420 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677422 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608398 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2960 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246173 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246173 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608377 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2971 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2984 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969441 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798176 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37507 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149666 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7954790 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62986112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85598825 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253968 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 148893553 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148893553 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 203396 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4965063678 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969614 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798105 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149421 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7954388 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62990656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85594465 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54388 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 148893341 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148893341 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 204156 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964785971 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4434793437 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4437766959 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4469014832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4499076262 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23886909 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23705637 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86662497 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86451768 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48461480 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution +system.iobus.throughput 48459921 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322133 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322133 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution system.iobus.trans_dist::WriteResp 8160 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -925,11 +916,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -952,9 +943,9 @@ system.iobus.pkt_count::system.realview.aaci_fake.pio 16 system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660586 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -976,11 +967,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390325 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1003,11 +994,11 @@ system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500861 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500853 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500853 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1053,684 +1044,684 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374794000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu0.branchPred.lookups 7472736 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5963732 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 379354 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4914816 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4037140 # Number of BTB hits +system.iobus.respLayer1.occupancy 41501177007 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu0.branchPred.lookups 7460849 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5960235 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 378283 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4914778 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4045811 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 82.142241 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 698266 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38240 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 82.319303 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 696591 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38344 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25723416 # DTB read hits -system.cpu0.dtb.read_misses 39440 # DTB read misses -system.cpu0.dtb.write_hits 6006462 # DTB write hits -system.cpu0.dtb.write_misses 9528 # DTB write misses +system.cpu0.dtb.read_hits 25704058 # DTB read hits +system.cpu0.dtb.read_misses 39030 # DTB read misses +system.cpu0.dtb.write_hits 5997479 # DTB write hits +system.cpu0.dtb.write_misses 9591 # DTB write misses system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5597 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1333 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5605 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25762856 # DTB read accesses -system.cpu0.dtb.write_accesses 6015990 # DTB write accesses +system.cpu0.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25743088 # DTB read accesses +system.cpu0.dtb.write_accesses 6007070 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31729878 # DTB hits -system.cpu0.dtb.misses 48968 # DTB misses -system.cpu0.dtb.accesses 31778846 # DTB accesses -system.cpu0.itb.inst_hits 6261683 # ITB inst hits -system.cpu0.itb.inst_misses 7235 # ITB inst misses +system.cpu0.dtb.hits 31701537 # DTB hits +system.cpu0.dtb.misses 48621 # DTB misses +system.cpu0.dtb.accesses 31750158 # DTB accesses +system.cpu0.itb.inst_hits 6247488 # ITB inst hits +system.cpu0.itb.inst_misses 7199 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1719 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6268918 # ITB inst accesses -system.cpu0.itb.hits 6261683 # DTB hits -system.cpu0.itb.misses 7235 # DTB misses -system.cpu0.itb.accesses 6268918 # DTB accesses -system.cpu0.numCycles 237920120 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6254687 # ITB inst accesses +system.cpu0.itb.hits 6247488 # DTB hits +system.cpu0.itb.misses 7199 # DTB misses +system.cpu0.itb.accesses 6254687 # DTB accesses +system.cpu0.numCycles 237974378 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15748746 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 49352173 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7472736 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4735406 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10833707 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2792544 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 84623 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 47712542 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1287 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1922 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 50902 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1299242 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6259599 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 422561 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2976 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77655749 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.785029 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.152550 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15699723 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 49234228 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7460849 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4742402 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10819268 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2791638 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 83518 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 47679796 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1910 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 50382 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1297285 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 371 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6245426 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 421717 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2971 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77555768 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.784584 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.151481 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66829888 86.06% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 668416 0.86% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 858180 1.11% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1304413 1.68% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1126910 1.45% 91.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 549966 0.71% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1380247 1.78% 93.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 376750 0.49% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4560979 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 66744115 86.06% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 668305 0.86% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 854486 1.10% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1301033 1.68% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1140084 1.47% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 550475 0.71% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1373308 1.77% 93.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 375655 0.48% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4548307 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77655749 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031409 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.207432 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16823690 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 48684179 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9802416 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 509733 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1833567 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1006000 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91487 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 57560969 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 307020 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1833567 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17765952 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19652864 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 25831801 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9294758 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3274685 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54590229 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7255 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 552363 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2204905 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 211 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 56896376 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 249980910 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 249932531 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48379 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39701074 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 17195302 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 410578 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 363043 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6638624 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10379903 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6907552 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1064074 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1362159 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50052762 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 969661 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62837234 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92382 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11367794 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 29332821 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 250599 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77655749 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.809177 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.518047 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77555768 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031351 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.206889 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16771569 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 48649935 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9795097 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 503008 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1834030 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1000504 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90828 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 57451762 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 304997 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1834030 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17711945 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 19691518 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 25851696 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9283653 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3180864 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54475085 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7298 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 545691 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2120831 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 197 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 56755313 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 249403500 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 249355386 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48114 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39528436 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 17226877 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 410327 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 362870 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6606046 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10343576 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6897280 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1045135 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1291149 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49940914 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 982735 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62750040 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92397 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11407526 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 29277622 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 263780 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77555768 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.809096 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.520917 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55074638 70.92% 70.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6993608 9.01% 79.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3678555 4.74% 84.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3117743 4.01% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6240678 8.04% 96.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1479911 1.91% 98.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 787330 1.01% 99.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 219248 0.28% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 64038 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55086998 71.03% 71.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6938242 8.95% 79.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3598420 4.64% 84.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3124608 4.03% 88.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6233139 8.04% 96.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1485765 1.92% 98.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 804564 1.04% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 219887 0.28% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 64145 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77655749 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77555768 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 30466 0.70% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4143838 94.53% 95.23% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 209138 4.77% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 31748 0.72% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4146155 94.50% 95.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 209698 4.78% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 167413 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29876413 47.55% 47.81% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48260 0.08% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 946 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26437550 42.07% 89.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6306621 10.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 168420 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29819854 47.52% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48156 0.08% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 937 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26415371 42.10% 89.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6297270 10.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62837234 # Type of FU issued -system.cpu0.iq.rate 0.264111 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4383444 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.069759 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207842642 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62399132 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43895220 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12180 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6627 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67046851 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6414 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 320881 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62750040 # Type of FU issued +system.cpu0.iq.rate 0.263684 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4387604 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.069922 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 207571986 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62340159 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43794455 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12289 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6579 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5482 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66962707 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6517 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 317894 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2431860 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3521 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16133 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 922699 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2428904 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3600 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16156 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 921017 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 16864632 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 486760 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 16878789 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 486624 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1833567 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14994749 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 240124 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 51146104 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107104 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10379903 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6907552 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 682007 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 55746 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3189 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16133 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 183360 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147814 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 331174 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61530066 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26055329 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1307168 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1834030 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15021196 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239984 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51041656 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 102587 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10343576 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6897280 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 695313 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54984 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10683 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16156 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184294 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 146657 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 330951 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61443864 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26034265 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1306176 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 123681 # number of nop insts executed -system.cpu0.iew.exec_refs 32305514 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5821167 # Number of branches executed -system.cpu0.iew.exec_stores 6250185 # Number of stores executed -system.cpu0.iew.exec_rate 0.258616 # Inst execution rate -system.cpu0.iew.wb_sent 60920832 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43900742 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23943541 # num instructions producing a value -system.cpu0.iew.wb_consumers 43567103 # num instructions consuming a value +system.cpu0.iew.exec_nop 118007 # number of nop insts executed +system.cpu0.iew.exec_refs 32275135 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5809455 # Number of branches executed +system.cpu0.iew.exec_stores 6240870 # Number of stores executed +system.cpu0.iew.exec_rate 0.258195 # Inst execution rate +system.cpu0.iew.wb_sent 60834498 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43799937 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23902926 # num instructions producing a value +system.cpu0.iew.wb_consumers 43468500 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184519 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.549578 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184053 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.549891 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11253313 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 719062 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 289317 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75822182 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.520093 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.499421 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11258567 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 718955 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 288860 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75721738 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.518964 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.500316 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61770131 81.47% 81.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6789372 8.95% 90.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2077521 2.74% 93.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1107875 1.46% 94.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1001712 1.32% 95.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 557795 0.74% 96.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 684831 0.90% 97.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 401810 0.53% 98.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1431135 1.89% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61785849 81.60% 81.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6716034 8.87% 90.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2031673 2.68% 93.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1100696 1.45% 94.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 996789 1.32% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 567209 0.75% 96.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 697121 0.92% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 401495 0.53% 98.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1424872 1.88% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75822182 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30629038 # Number of instructions committed -system.cpu0.commit.committedOps 39434598 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75721738 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30484303 # Number of instructions committed +system.cpu0.commit.committedOps 39296836 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13932896 # Number of memory references committed -system.cpu0.commit.loads 7948043 # Number of loads committed -system.cpu0.commit.membars 201908 # Number of memory barriers committed -system.cpu0.commit.branches 4992421 # Number of branches committed -system.cpu0.commit.fp_insts 5469 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34986832 # Number of committed integer instructions. -system.cpu0.commit.function_calls 490811 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1431135 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13890935 # Number of memory references committed +system.cpu0.commit.loads 7914672 # Number of loads committed +system.cpu0.commit.membars 201566 # Number of memory barriers committed +system.cpu0.commit.branches 4969836 # Number of branches committed +system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34871152 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489123 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1424872 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124149615 # The number of ROB reads -system.cpu0.rob.rob_writes 103265708 # The number of ROB writes -system.cpu0.timesIdled 892080 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 160264371 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2282472691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 30545540 # Number of Instructions Simulated -system.cpu0.committedOps 39351100 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 30545540 # Number of Instructions Simulated -system.cpu0.cpi 7.789030 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.789030 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.128386 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.128386 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 279175646 # number of integer regfile reads -system.cpu0.int_regfile_writes 45166448 # number of integer regfile writes -system.cpu0.fp_regfile_reads 23007 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19790 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15439802 # number of misc regfile reads -system.cpu0.misc_regfile_writes 404480 # number of misc regfile writes -system.cpu0.icache.replacements 984632 # number of replacements -system.cpu0.icache.tagsinuse 511.564307 # Cycle average of tags in use -system.cpu0.icache.total_refs 10914069 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 985144 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.078653 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6937099000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 153.323923 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 358.240384 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.299461 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.699688 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999149 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5710872 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5203197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10914069 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5710872 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5203197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10914069 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5710872 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5203197 # number of overall hits -system.cpu0.icache.overall_hits::total 10914069 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 548607 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 517852 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1066459 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 548607 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 517852 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1066459 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 548607 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 517852 # number of overall misses -system.cpu0.icache.overall_misses::total 1066459 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7528963984 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7029593986 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14558557970 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7528963984 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7029593986 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14558557970 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7528963984 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7029593986 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14558557970 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6259479 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5721049 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11980528 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6259479 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5721049 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11980528 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6259479 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5721049 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11980528 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.087644 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090517 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.089016 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.087644 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090517 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.089016 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087644 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090517 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.089016 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13723.784028 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13574.523196 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13651.305835 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13651.305835 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13651.305835 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7371 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 409 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.022005 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.rob.rob_reads 123917155 # The number of ROB reads +system.cpu0.rob.rob_writes 103001078 # The number of ROB writes +system.cpu0.timesIdled 891630 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 160418610 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2282332434 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 30404601 # Number of Instructions Simulated +system.cpu0.committedOps 39217134 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 30404601 # Number of Instructions Simulated +system.cpu0.cpi 7.826920 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.826920 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.127764 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.127764 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 278728087 # number of integer regfile reads +system.cpu0.int_regfile_writes 45052561 # number of integer regfile writes +system.cpu0.fp_regfile_reads 23012 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19792 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15437173 # number of misc regfile reads +system.cpu0.misc_regfile_writes 403324 # number of misc regfile writes +system.cpu0.icache.tags.replacements 984712 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.392135 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10916124 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 985224 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 11.079840 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6946570250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 153.798869 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 356.593266 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.300388 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.696471 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.996860 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5698838 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5217286 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10916124 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5698838 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5217286 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10916124 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5698838 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5217286 # number of overall hits +system.cpu0.icache.overall_hits::total 10916124 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 546469 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 520462 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1066931 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 546469 # 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number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7505000228 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7078718225 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14583718453 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6245307 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5737748 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11983055 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6245307 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5737748 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11983055 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6245307 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5737748 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10776141152 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 77981002 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68096502 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146077504 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 67000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 67000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 134000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8272921091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7745751501 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16018672592 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8272921091 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7745751501 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16018672592 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90317850501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 92017839000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182335689501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 18608772616 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14303930851 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32912703467 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 156000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 156000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 313405 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 321818 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635223 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 313405 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 321818 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635223 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2537438499 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2706851142 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5244289641 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5705098821 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5073968451 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10779067272 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78058501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68010500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146069001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 102498 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 168498 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8242537320 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7780819593 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16023356913 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8242537320 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7780819593 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16023356913 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90382122001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91936686500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182318808501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 18619452182 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14311531070 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32930983252 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 108926623117 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106321769851 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215248392968 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024709 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028567 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026587 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024933 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023757 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051475 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043710 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047379 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000043 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000038 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13896.184228 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13279.234055 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13573.459198 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43991.095531 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42494.536818 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43275.068377 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12463.001758 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11481.453718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11985.354775 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 109001574183 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106248217570 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215249791753 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024652 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028587 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026577 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025073 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051447 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043646 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047334 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000046 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025659 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025659 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13865.405311 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13318.627137 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13577.694977 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43750.757830 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42789.411798 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43292.904137 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12465.426541 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11476.628417 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11984.657122 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14642.571429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12961.384615 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1745,330 +1736,330 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7176614 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5748558 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 346164 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4712171 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3815419 # Number of BTB hits +system.cpu1.branchPred.lookups 7195832 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5758794 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 347995 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4705708 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3816103 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 80.969451 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 703194 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35756 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 81.095193 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 703176 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35899 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25652921 # DTB read hits -system.cpu1.dtb.read_misses 36442 # DTB read misses -system.cpu1.dtb.write_hits 5708219 # DTB write hits -system.cpu1.dtb.write_misses 9483 # DTB write misses +system.cpu1.dtb.read_hits 25676963 # DTB read hits +system.cpu1.dtb.read_misses 36626 # DTB read misses +system.cpu1.dtb.write_hits 5717501 # DTB write hits +system.cpu1.dtb.write_misses 9454 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5550 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1965 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25689363 # DTB read accesses -system.cpu1.dtb.write_accesses 5717702 # DTB write accesses +system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25713589 # DTB read accesses +system.cpu1.dtb.write_accesses 5726955 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31361140 # DTB hits -system.cpu1.dtb.misses 45925 # DTB misses -system.cpu1.dtb.accesses 31407065 # DTB accesses -system.cpu1.itb.inst_hits 5722854 # ITB inst hits -system.cpu1.itb.inst_misses 6790 # ITB inst misses +system.cpu1.dtb.hits 31394464 # DTB hits +system.cpu1.dtb.misses 46080 # DTB misses +system.cpu1.dtb.accesses 31440544 # DTB accesses +system.cpu1.itb.inst_hits 5739661 # ITB inst hits +system.cpu1.itb.inst_misses 6710 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2604 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2611 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1206 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1312 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5729644 # ITB inst accesses -system.cpu1.itb.hits 5722854 # DTB hits -system.cpu1.itb.misses 6790 # DTB misses -system.cpu1.itb.accesses 5729644 # DTB accesses -system.cpu1.numCycles 238719781 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5746371 # ITB inst accesses +system.cpu1.itb.hits 5739661 # DTB hits +system.cpu1.itb.misses 6710 # DTB misses +system.cpu1.itb.accesses 5746371 # DTB accesses +system.cpu1.numCycles 238752144 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14663434 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45610232 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7176614 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4518613 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10115214 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2414166 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 79241 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48437095 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 41135 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1402245 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5721051 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 343472 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3001 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76398004 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.741963 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.097795 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14725732 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45766952 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7195832 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4519279 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10135681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2420409 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 79807 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48403648 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1933 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42395 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1408034 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5737749 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 344300 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2901 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76459821 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.743283 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.100006 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66290194 86.77% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 639384 0.84% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 858446 1.12% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1141205 1.49% 90.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1054322 1.38% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 565766 0.74% 92.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1279029 1.67% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 372986 0.49% 94.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4196672 5.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66331645 86.75% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 641052 0.84% 87.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 862069 1.13% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1143637 1.50% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1042629 1.36% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 566145 0.74% 92.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1286339 1.68% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 374523 0.49% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4211782 5.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76398004 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030063 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.191062 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15662136 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49485106 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9174118 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 502006 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1572389 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 964164 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86078 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53732667 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 284993 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1572389 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16517156 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19371694 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27019391 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8745759 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3169437 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51316953 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13347 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 558580 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2084092 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 533 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53384018 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 234291448 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 234248948 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42500 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38701877 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14682140 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 422621 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 375998 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6399704 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9755366 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6540913 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 899316 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1131463 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47221133 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1016692 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 61223636 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 83704 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9695690 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24360360 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 252773 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76398004 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.801377 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.509980 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76459821 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030139 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.191692 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15725454 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49459208 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9192415 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 503929 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1576672 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 971007 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86673 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53874532 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286668 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1576672 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16583861 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19404823 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27005764 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8762969 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3123666 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51462507 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13354 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 564319 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2029977 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 529 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53559967 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 234998901 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 234956394 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42507 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38873752 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14686214 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 422468 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 375757 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6418869 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9803560 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6552959 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 903342 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1157992 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47368560 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1003626 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 61323847 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 88809 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9695135 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24547753 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 239591 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76459821 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.802040 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.511450 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54279894 71.05% 71.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6964982 9.12% 80.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3572105 4.68% 84.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2997144 3.92% 88.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6191464 8.10% 96.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1336331 1.75% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 781274 1.02% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 210623 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64187 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54334795 71.06% 71.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6963817 9.11% 80.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3541064 4.63% 84.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3011943 3.94% 88.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6202034 8.11% 96.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1339759 1.75% 98.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 792493 1.04% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 211144 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 62772 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76398004 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76459821 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28625 0.64% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4232850 94.77% 95.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 204916 4.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28001 0.63% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4231917 94.82% 95.44% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 203383 4.56% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 196253 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28636645 46.77% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45275 0.07% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1166 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26314487 42.98% 90.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6029771 9.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 195246 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28699765 46.80% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45365 0.07% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1174 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26341683 42.96% 90.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6040595 9.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 61223636 # Type of FU issued -system.cpu1.iq.rate 0.256467 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4466394 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072952 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 203430011 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57942058 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42278659 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11099 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5883 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4799 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65487820 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5957 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 306320 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 61323847 # Type of FU issued +system.cpu1.iq.rate 0.256852 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4463304 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072783 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203694277 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58075857 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42386346 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11257 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5873 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65585843 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6062 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 307143 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2045827 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3210 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14938 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 792022 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2060794 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3248 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14926 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 795522 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17238980 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 391927 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17225652 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 391932 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1572389 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14646185 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 228906 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48337037 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 102627 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9755366 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6540913 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 729665 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50173 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3845 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14938 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 169845 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 132330 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 302175 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60177661 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 26008514 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1045975 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1576672 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14666749 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48476685 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98660 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9803560 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6552959 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 716609 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50437 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 9701 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14926 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 170356 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133051 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 303407 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 60276255 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 26034557 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1047592 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 99212 # number of nop insts executed -system.cpu1.iew.exec_refs 31985233 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5705434 # Number of branches executed -system.cpu1.iew.exec_stores 5976719 # Number of stores executed -system.cpu1.iew.exec_rate 0.252085 # Inst execution rate -system.cpu1.iew.wb_sent 59667880 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42283458 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23216135 # num instructions producing a value -system.cpu1.iew.wb_consumers 42895102 # num instructions consuming a value +system.cpu1.iew.exec_nop 104499 # number of nop insts executed +system.cpu1.iew.exec_refs 32021114 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5717498 # Number of branches executed +system.cpu1.iew.exec_stores 5986557 # Number of stores executed +system.cpu1.iew.exec_rate 0.252464 # Inst execution rate +system.cpu1.iew.wb_sent 59765334 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42391160 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23307297 # num instructions producing a value +system.cpu1.iew.wb_consumers 43055480 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.177126 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.541230 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177553 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.541332 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9567940 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 763919 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 261423 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74825615 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.512228 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.487191 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9596314 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 764035 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 262671 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74883149 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.513666 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.490214 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61056295 81.60% 81.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6800068 9.09% 90.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1929591 2.58% 93.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1057405 1.41% 94.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1013455 1.35% 96.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 520209 0.70% 96.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 685711 0.92% 97.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 375889 0.50% 98.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1386992 1.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61098286 81.59% 81.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6805438 9.09% 90.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1903916 2.54% 93.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1064936 1.42% 94.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1018174 1.36% 96.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 531111 0.71% 96.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 691593 0.92% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 378534 0.51% 98.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1391161 1.86% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74825615 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29838157 # Number of instructions committed -system.cpu1.commit.committedOps 38327755 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74883149 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29982419 # Number of instructions committed +system.cpu1.commit.committedOps 38464913 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13458430 # Number of memory references committed -system.cpu1.commit.loads 7709539 # Number of loads committed -system.cpu1.commit.membars 201879 # Number of memory barriers committed -system.cpu1.commit.branches 4970440 # Number of branches committed -system.cpu1.commit.fp_insts 4743 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33879408 # Number of committed integer instructions. -system.cpu1.commit.function_calls 500692 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1386992 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13500203 # Number of memory references committed +system.cpu1.commit.loads 7742766 # Number of loads committed +system.cpu1.commit.membars 202217 # Number of memory barriers committed +system.cpu1.commit.branches 4992962 # Number of branches committed +system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33994528 # Number of committed integer instructions. +system.cpu1.commit.function_calls 502375 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1391161 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120414089 # The number of ROB reads -system.cpu1.rob.rob_writes 97409741 # The number of ROB writes -system.cpu1.timesIdled 885352 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 162321777 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2286481516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29771274 # Number of Instructions Simulated -system.cpu1.committedOps 38260872 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29771274 # Number of Instructions Simulated -system.cpu1.cpi 8.018460 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.018460 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124712 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124712 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 271859015 # number of integer regfile reads -system.cpu1.int_regfile_writes 43450852 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22226 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19958 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14811721 # number of misc regfile reads -system.cpu1.misc_regfile_writes 428358 # number of misc regfile writes -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.rob.rob_reads 120638730 # The number of ROB reads +system.cpu1.rob.rob_writes 97745041 # The number of ROB writes +system.cpu1.timesIdled 886317 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 162292323 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2286407630 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29911740 # Number of Instructions Simulated +system.cpu1.committedOps 38394234 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29911740 # Number of Instructions Simulated +system.cpu1.cpi 7.981888 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.981888 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.125284 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.125284 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 272364887 # number of integer regfile reads +system.cpu1.int_regfile_writes 43577017 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22187 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19914 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14848508 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429527 # number of misc regfile writes +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2077,17 +2068,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1456504103755 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1456504103755 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1453044953007 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1453044953007 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83064 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83067 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index fb76d8786..96aff7e7e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.627154 # Number of seconds simulated -sim_ticks 2627154206500 # Number of ticks simulated -final_tick 2627154206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.630645 # Number of seconds simulated +sim_ticks 2630645085500 # Number of ticks simulated +final_tick 2630645085500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 361221 # Simulator instruction rate (inst/s) -host_op_rate 459651 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15759970234 # Simulator tick rate (ticks/s) -host_mem_usage 398468 # Number of bytes of host memory used -host_seconds 166.70 # Real time elapsed on the host -sim_insts 60214798 # Number of instructions simulated -sim_ops 76622863 # Number of ops (including micro ops) simulated +host_inst_rate 281405 # Simulator instruction rate (inst/s) +host_op_rate 358084 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12294669184 # Simulator tick rate (ticks/s) +host_mem_usage 398476 # Number of bytes of host memory used +host_seconds 213.97 # Real time elapsed on the host +sim_insts 60211229 # Number of instructions simulated +sim_ops 76617937 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 292384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4914704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 305952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4748752 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 411968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4151472 # Number of bytes read from this memory -system.physmem.bytes_read::total 134026976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 292384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 411968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3695296 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1534856 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1481296 # Number of bytes written to this memory -system.physmem.bytes_written::total 6711448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 398080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4312560 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 305952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 398080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3690176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1535008 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1481144 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706328 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 76826 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10983 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 74233 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6437 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 64893 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690962 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57739 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 383714 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 370324 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811777 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47296902 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 67410 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690881 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57659 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 383752 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 370286 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811697 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47234139 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 111293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1870733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 116303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1805166 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 156812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1580216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51016029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 111293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 156812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1406578 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 584228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2554646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1406578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47296902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 151324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1639355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50946360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 116303 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 151324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1402765 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 583510 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 563035 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2549309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1402765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47234139 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 111293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2454961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 116303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2388676 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 156812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2144057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53570675 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690962 # Total number of read requests seen -system.physmem.writeReqs 811777 # Total number of write requests seen -system.physmem.cpureqs 214505 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1004221568 # Total number of bytes read from memory -system.physmem.bytesWritten 51953728 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 134026976 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6711448 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 151324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2202389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53495669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690881 # Total number of read requests seen +system.physmem.writeReqs 811697 # Total number of write requests seen +system.physmem.cpureqs 214350 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1004216384 # Total number of bytes read from memory +system.physmem.bytesWritten 51948608 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 134021792 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6706328 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 980549 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 980310 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 980142 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 980447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 986846 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 980559 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 980589 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 980289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 980613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 980424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 979732 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 979654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 980193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 980214 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 980246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 980129 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49129 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50872 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51073 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51427 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51034 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 50841 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50704 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 50829 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 4522 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 980391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 980205 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 980221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 980428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 986950 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 980709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 980611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 980417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 980615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 980431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 979815 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 979554 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 980154 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 980076 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 980169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 980109 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49026 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50948 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51094 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51463 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51294 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51194 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51021 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50517 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50336 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 50808 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50591 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50830 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 50810 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2627149788000 # Total gap between requests +system.physmem.totGap 2630640666000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6680 # Categorize read packet sizes system.physmem.readPktSize::3 15532032 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152250 # Categorize read packet sizes +system.physmem.readPktSize::6 152169 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754038 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57739 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1134037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 977508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1022657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3835405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2876027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2874808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2829459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 16845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 41555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 32 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57659 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1131442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 973737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1003950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3836084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2879069 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2878494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2847936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 16166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 44268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 29895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1039 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -152,30 +152,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -184,224 +184,196 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38107 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 27715.971974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2557.155392 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33302.761922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5424 14.23% 14.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3316 8.70% 22.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2198 5.77% 28.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1686 4.42% 33.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1157 3.04% 36.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1029 2.70% 38.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 812 2.13% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 726 1.91% 42.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 578 1.52% 44.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 463 1.21% 45.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 465 1.22% 46.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 413 1.08% 47.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 261 0.68% 48.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 269 0.71% 49.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 229 0.60% 49.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 239 0.63% 50.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 136 0.36% 51.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 99 0.26% 51.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 99 0.26% 51.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 86 0.23% 52.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 761 2.00% 54.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 211 0.55% 54.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 139 0.36% 55.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 123 0.32% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 64 0.17% 55.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 78 0.20% 56.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 56 0.15% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 58 0.15% 56.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 48 0.13% 56.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 69 0.18% 56.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 34 0.09% 56.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 27 0.07% 56.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 25 0.07% 56.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 9 0.02% 56.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 23 0.06% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 23 0.06% 57.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 14 0.04% 57.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 8 0.02% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 9 0.02% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 5 0.01% 57.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 6 0.02% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 4 0.01% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 8 0.02% 57.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 4 0.01% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 7 0.02% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 11 0.03% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 9 0.02% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 3 0.01% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 10 0.03% 57.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 6 0.02% 57.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 4 0.01% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 6 0.02% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 4 0.01% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 3 0.01% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 6 0.02% 57.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 5 0.01% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 3 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 1 0.00% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 3 0.01% 57.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 2 0.01% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 4 0.01% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 2 0.01% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 4 0.01% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 2 0.01% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 3 0.01% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 1 0.00% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 2 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 1 0.00% 57.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 23 0.06% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 4 0.01% 58.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 3 0.01% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 2 0.01% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 18 0.05% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 1 0.00% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 5 0.01% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 1 0.00% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 3 0.01% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 4 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 6 0.02% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 3 0.01% 58.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 5 0.01% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 310 0.81% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9471 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9855 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 17 0.04% 59.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 2 0.01% 59.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 2 0.01% 59.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12351 1 0.00% 59.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 2 0.01% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14655 1 0.00% 59.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14911 1 0.00% 59.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 2 0.01% 59.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18751 2 0.01% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 1 0.00% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-20031 1 0.00% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 59.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 3 0.01% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 3 0.01% 59.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 1 0.00% 59.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 1 0.00% 59.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25983 1 0.00% 59.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 59.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 2 0.01% 59.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 59.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 3 0.01% 59.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 1 0.00% 59.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 59.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 59.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 59.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31103 2 0.01% 59.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 1 0.00% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32575 1 0.00% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 1 0.00% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33535 2 0.01% 59.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 19 0.05% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35391 1 0.00% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36927 2 0.01% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38207 1 0.00% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-41023 1 0.00% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 1 0.00% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44095 2 0.01% 59.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 59.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48447 1 0.00% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50751 1 0.00% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51519 1 0.00% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52480-52543 1 0.00% 59.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54335 1 0.00% 59.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56128-56191 1 0.00% 59.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58624-58687 1 0.00% 59.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60032-60095 1 0.00% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60672-60735 1 0.00% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 1 0.00% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 15122 39.68% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::71808-71871 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::82176-82239 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::88064-88127 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::99712-99775 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131135 356 0.93% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37996 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 27796.675861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2568.021256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33333.179984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5396 14.20% 14.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3321 8.74% 22.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2191 5.77% 28.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1656 4.36% 33.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1158 3.05% 36.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1048 2.76% 38.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 789 2.08% 40.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 726 1.91% 42.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 577 1.52% 44.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 474 1.25% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 440 1.16% 46.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 388 1.02% 47.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 251 0.66% 48.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 273 0.72% 49.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 221 0.58% 49.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 258 0.68% 50.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 159 0.42% 50.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 126 0.33% 51.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 108 0.28% 51.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 95 0.25% 51.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 80 0.21% 51.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 156 0.41% 52.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 779 2.05% 54.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 205 0.54% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 146 0.38% 55.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 108 0.28% 55.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 84 0.22% 55.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 80 0.21% 56.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 53 0.14% 56.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 48 0.13% 56.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 45 0.12% 56.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 58 0.15% 56.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 47 0.12% 56.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 26 0.07% 56.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 22 0.06% 56.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 18 0.05% 56.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 19 0.05% 56.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 19 0.05% 57.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 11 0.03% 57.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 13 0.03% 57.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 9 0.02% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 10 0.03% 57.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 16 0.04% 57.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 3 0.01% 57.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 9 0.02% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 4 0.01% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 5 0.01% 57.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 5 0.01% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 15 0.04% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 13 0.03% 57.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 8 0.02% 57.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 34 0.09% 57.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 3 0.01% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 1 0.00% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 1 0.00% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 7 0.02% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 6 0.02% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 5 0.01% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 3 0.01% 57.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 6 0.02% 57.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 1 0.00% 57.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 4 0.01% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 2 0.01% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 3 0.01% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 6 0.02% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 3 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 2 0.01% 57.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 4 0.01% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 2 0.01% 57.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 1 0.00% 57.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 5 0.01% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 2 0.01% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 1 0.00% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 18 0.05% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 4 0.01% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 4 0.01% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 1 0.00% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 3 0.01% 57.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 3 0.01% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 1 0.00% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 2 0.01% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 17 0.04% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 1 0.00% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 1 0.00% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 5 0.01% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 7 0.02% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 3 0.01% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 6 0.02% 58.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 2 0.01% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 9 0.02% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 4 0.01% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 308 0.81% 58.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 58.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11071 2 0.01% 59.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 1 0.00% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14655 1 0.00% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17727 1 0.00% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-19007 1 0.00% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21311 2 0.01% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22079 1 0.00% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 1 0.00% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25151 1 0.00% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26175 1 0.00% 59.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 2 0.01% 59.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 2 0.01% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 1 0.00% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 1 0.00% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31039 1 0.00% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 2 0.01% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32831 2 0.01% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 3 0.01% 59.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 15 0.04% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41215 1 0.00% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46143 1 0.00% 59.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47423 1 0.00% 59.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52287 1 0.00% 59.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55872-55935 1 0.00% 59.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57984-58047 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58240-58303 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 15141 39.85% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::72832-72895 1 0.00% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::80704-80767 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::86848-86911 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::101184-101247 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129728-129791 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131135 356 0.94% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136639 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38107 # Bytes accessed per row activation -system.physmem.totQLat 304254816750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 398977768000 # Sum of mem lat for all requests -system.physmem.totBusLat 78454680000 # Total cycles spent in databus access -system.physmem.totBankLat 16268271250 # Total cycles spent in bank access -system.physmem.avgQLat 19390.48 # Average queueing delay per request -system.physmem.avgBankLat 1036.79 # Average bank access latency per request +system.physmem.bytesPerActivate::total 37996 # Bytes accessed per row activation +system.physmem.totQLat 300645538000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 395312713000 # Sum of mem lat for all requests +system.physmem.totBusLat 78454275000 # Total cycles spent in databus access +system.physmem.totBankLat 16212900000 # Total cycles spent in bank access +system.physmem.avgQLat 19160.56 # Average queueing delay per request +system.physmem.avgBankLat 1033.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25427.28 # Average memory access latency -system.physmem.avgRdBW 382.25 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.02 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 25193.83 # Average memory access latency +system.physmem.avgRdBW 381.74 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.75 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.95 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.55 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 1.26 # Average write queue length over time -system.physmem.readRowHits 15666209 # Number of row buffer hits during reads -system.physmem.writeRowHits 798397 # Number of row buffer hits during writes +system.physmem.readRowHits 15666172 # Number of row buffer hits during reads +system.physmem.writeRowHits 798379 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.35 # Row buffer hit rate for writes -system.physmem.avgGap 159194.77 # Average gap between requests +system.physmem.writeRowHitRate 98.36 # Row buffer hit rate for writes +system.physmem.avgGap 159407.86 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -414,259 +386,259 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54483503 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743616 # Transaction distribution -system.membus.trans_dist::ReadResp 16743616 # Transaction distribution +system.membus.throughput 54407285 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743607 # Transaction distribution +system.membus.trans_dist::ReadResp 16743607 # Transaction distribution system.membus.trans_dist::WriteReq 763392 # Transaction distribution system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57739 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution -system.membus.trans_dist::ReadExReq 131423 # Transaction distribution -system.membus.trans_dist::ReadExResp 131423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57659 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution +system.membus.trans_dist::ReadExReq 131350 # Transaction distribution +system.membus.trans_dist::ReadExResp 131350 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892707 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892477 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279337 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32956771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32956541 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343633 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35343401 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16482168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471864 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18880309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18870001 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 140738424 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 140728120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143136565 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143136565 # Total data (bytes) +system.membus.tot_pkt_size::total 143126257 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143126257 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225633000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1209137000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 18165198500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 18109692000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3755000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3744500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4987617364 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4946454076 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35065696500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35060518750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.replacements 62136 # number of replacements -system.l2c.tagsinuse 51567.664706 # Cycle average of tags in use -system.l2c.total_refs 1698783 # Total number of references to valid blocks. -system.l2c.sampled_refs 127519 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.321803 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2572304327500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 38171.110682 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000688 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2904.028598 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3024.624697 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4116.712903 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3351.186952 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.582445 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.044312 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.046152 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.062816 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.051135 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.786860 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9922 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419412 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 179877 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9880 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3503 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 425184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 190638 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242011 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596576 # number of Writeback hits -system.l2c.Writeback_hits::total 596576 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits +system.l2c.tags.replacements 62055 # number of replacements +system.l2c.tags.tagsinuse 51615.482729 # Cycle average of tags in use +system.l2c.tags.total_refs 1699189 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127440 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.333247 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2575816655500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38219.751550 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000690 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2839.791296 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3005.850612 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4181.982232 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3368.106163 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583187 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.043332 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045866 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.063812 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.051393 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787590 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 10006 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3588 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 435821 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 185768 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9923 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3635 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 408641 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 184604 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241986 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596408 # number of Writeback hits +system.l2c.Writeback_hits::total 596408 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56638 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57846 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114484 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9922 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 236515 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9880 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3503 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 425184 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 248484 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356495 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9922 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3595 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419412 # number of overall hits -system.l2c.overall_hits::cpu0.data 236515 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9880 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3503 # number of overall hits -system.l2c.overall_hits::cpu1.inst 425184 # number of overall hits -system.l2c.overall_hits::cpu1.data 248484 # number of overall hits -system.l2c.overall_hits::total 1356495 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 59901 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54618 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114519 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 10006 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3588 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 435821 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 245669 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9923 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3635 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 408641 # 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number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4367 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5353 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6437 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4901 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20827 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1388 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1493 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu1.inst 6220 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4876 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20819 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1448 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1433 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2881 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 72239 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 52339.077136 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57093.207395 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52130.681758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 52354.656011 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -814,45 +786,45 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52848676 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471696 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471696 # Transaction distribution +system.toL2Bus.throughput 52767546 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471907 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471907 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596576 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596408 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247542 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247542 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1725238 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5754024 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 19969 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50318 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7549549 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54758516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83805889 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28400 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79212 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 138672017 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138672017 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 169604 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4809056500 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadExReq 247510 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247510 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1724962 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5753498 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 20327 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50707 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7549494 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54749620 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83783741 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28900 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 138641981 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138641981 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 170704 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808390000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3862257000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865864500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4394586000 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4428402674 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12869000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13102500 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30515000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30777250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48206783 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution +system.iobus.throughput 48142811 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715359 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715359 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution system.iobus.trans_dist::WriteResp 8167 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -874,11 +846,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -901,9 +873,9 @@ system.iobus.pkt_count::system.realview.aaci_fake.pio 16 system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447052 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -925,11 +897,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -952,11 +924,11 @@ system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646653 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646649 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646649 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1002,141 +974,141 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374821000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 31064064000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42579543250 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7331530 # DTB read hits -system.cpu0.dtb.read_misses 6749 # DTB read misses -system.cpu0.dtb.write_hits 5629181 # DTB write hits -system.cpu0.dtb.write_misses 1838 # DTB write misses -system.cpu0.dtb.flush_tlb 1246 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7541054 # DTB read hits +system.cpu0.dtb.read_misses 7077 # DTB read misses +system.cpu0.dtb.write_hits 5712165 # DTB write hits +system.cpu0.dtb.write_misses 1789 # DTB write misses +system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6355 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6540 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 146 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 224 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7338279 # DTB read accesses -system.cpu0.dtb.write_accesses 5631019 # DTB write accesses +system.cpu0.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7548131 # DTB read accesses +system.cpu0.dtb.write_accesses 5713954 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12960711 # DTB hits -system.cpu0.dtb.misses 8587 # DTB misses -system.cpu0.dtb.accesses 12969298 # DTB accesses -system.cpu0.itb.inst_hits 29905877 # ITB inst hits -system.cpu0.itb.inst_misses 3541 # ITB inst misses +system.cpu0.dtb.hits 13253219 # DTB hits +system.cpu0.dtb.misses 8866 # DTB misses +system.cpu0.dtb.accesses 13262085 # DTB accesses +system.cpu0.itb.inst_hits 30586267 # ITB inst hits +system.cpu0.itb.inst_misses 3713 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1246 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2713 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2774 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29909418 # ITB inst accesses -system.cpu0.itb.hits 29905877 # DTB hits -system.cpu0.itb.misses 3541 # DTB misses -system.cpu0.itb.accesses 29909418 # DTB accesses -system.cpu0.numCycles 2625614654 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30589980 # ITB inst accesses +system.cpu0.itb.hits 30586267 # DTB hits +system.cpu0.itb.misses 3713 # DTB misses +system.cpu0.itb.accesses 30589980 # DTB accesses +system.cpu0.numCycles 2629433969 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29354437 # Number of instructions committed -system.cpu0.committedOps 37594269 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33819709 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4399 # Number of float alu accesses -system.cpu0.num_func_calls 1050996 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3901744 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33819709 # number of integer instructions -system.cpu0.num_fp_insts 4399 # number of float instructions -system.cpu0.num_int_register_reads 193860060 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36222671 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 2980 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1422 # number of times the floating registers were written -system.cpu0.num_mem_refs 13528220 # number of memory refs -system.cpu0.num_load_insts 7652095 # Number of load instructions -system.cpu0.num_store_insts 5876125 # Number of store instructions -system.cpu0.num_idle_cycles 3959269974.685009 # Number of idle cycles -system.cpu0.num_busy_cycles -1333655320.685009 # Number of busy cycles -system.cpu0.not_idle_fraction -0.507940 # Percentage of non-idle cycles -system.cpu0.idle_fraction 1.507940 # Percentage of idle cycles +system.cpu0.committedInsts 29984771 # Number of instructions committed +system.cpu0.committedOps 38337194 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34488518 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5157 # Number of float alu accesses +system.cpu0.num_func_calls 1080132 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3980914 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34488518 # number of integer instructions +system.cpu0.num_fp_insts 5157 # number of float instructions +system.cpu0.num_int_register_reads 197896297 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36953400 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3554 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1606 # number of times the floating registers were written +system.cpu0.num_mem_refs 13834370 # number of memory refs +system.cpu0.num_load_insts 7870253 # Number of load instructions +system.cpu0.num_store_insts 5964117 # Number of store instructions +system.cpu0.num_idle_cycles -1415422.936618 # Number of idle cycles +system.cpu0.num_busy_cycles 2630849391.936618 # Number of busy cycles +system.cpu0.not_idle_fraction 1.000538 # Percentage of non-idle cycles +system.cpu0.idle_fraction -0.000538 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83030 # number of quiesce instructions executed -system.cpu0.icache.replacements 856296 # number of replacements -system.cpu0.icache.tagsinuse 510.881527 # Cycle average of tags in use -system.cpu0.icache.total_refs 60652091 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 856808 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 70.788428 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 19951126000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 211.269662 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 299.611865 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.412636 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.585179 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.997815 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29481581 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 31170510 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60652091 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29481581 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 31170510 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60652091 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29481581 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 31170510 # number of overall hits -system.cpu0.icache.overall_hits::total 60652091 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 424296 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 432512 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856808 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 424296 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 432512 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856808 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 424296 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 432512 # number of overall misses -system.cpu0.icache.overall_misses::total 856808 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5770416000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6023307000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11793723000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5770416000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6023307000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11793723000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5770416000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6023307000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11793723000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29905877 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 31603022 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61508899 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29905877 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 31603022 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61508899 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29905877 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 31603022 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61508899 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013686 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013686 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013686 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13599.977374 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13926.334992 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13764.720918 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13599.977374 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13926.334992 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13764.720918 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13599.977374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13926.334992 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13764.720918 # average overall miss latency +system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 856159 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.881074 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60648644 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856671 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.795724 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 19966906250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 210.109344 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 300.771730 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.410370 # 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mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046412 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026043 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026043 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12804.377653 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.131709 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12708.568272 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41235.379455 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38410.705667 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39880.049431 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11481.052275 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12456.887299 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11955.351709 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596408 # number of writebacks +system.cpu0.dcache.writebacks::total 596408 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184928 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 184113 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369041 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131071 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119346 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250417 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6193 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5367 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11560 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 315999 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 303459 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619458 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 315999 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 303459 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619458 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2362872250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2333419750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4696292000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5228333691 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4754653787 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9982987478 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70279500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66466500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136746000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7591205941 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7088073537 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14679279478 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7591205941 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7088073537 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14679279478 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91858515750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90196579000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182055094750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13241304408 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12994136940 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235441348 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105099820158 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103190715940 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208290536098 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027268 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025202 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023753 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048585 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044617 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046658 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026297 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025768 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026297 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025768 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12777.255202 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12673.845682 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12725.664628 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39889.324801 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39839.238743 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39865.454334 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11348.215727 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12384.292901 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11829.238754 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24022.879633 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23357.598677 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23696.972963 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24022.879633 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23357.598677 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23696.972963 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1388,76 +1360,76 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7669515 # DTB read hits -system.cpu1.dtb.read_misses 7262 # DTB read misses -system.cpu1.dtb.write_hits 5604176 # DTB write hits -system.cpu1.dtb.write_misses 1826 # DTB write misses -system.cpu1.dtb.flush_tlb 1246 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7458653 # DTB read hits +system.cpu1.dtb.read_misses 7094 # DTB read misses +system.cpu1.dtb.write_hits 5520448 # DTB write hits +system.cpu1.dtb.write_misses 1859 # DTB write misses +system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6595 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6666 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7676777 # DTB read accesses -system.cpu1.dtb.write_accesses 5606002 # DTB write accesses +system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7465747 # DTB read accesses +system.cpu1.dtb.write_accesses 5522307 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13273691 # DTB hits -system.cpu1.dtb.misses 9088 # DTB misses -system.cpu1.dtb.accesses 13282779 # DTB accesses -system.cpu1.itb.inst_hits 31603022 # ITB inst hits -system.cpu1.itb.inst_misses 3724 # ITB inst misses +system.cpu1.dtb.hits 12979101 # DTB hits +system.cpu1.dtb.misses 8953 # DTB misses +system.cpu1.dtb.accesses 12988054 # DTB accesses +system.cpu1.itb.inst_hits 30919048 # ITB inst hits +system.cpu1.itb.inst_misses 3673 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1246 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2827 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2817 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31606746 # ITB inst accesses -system.cpu1.itb.hits 31603022 # DTB hits -system.cpu1.itb.misses 3724 # DTB misses -system.cpu1.itb.accesses 31606746 # DTB accesses -system.cpu1.numCycles 2628693759 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30922721 # ITB inst accesses +system.cpu1.itb.hits 30919048 # DTB hits +system.cpu1.itb.misses 3673 # DTB misses +system.cpu1.itb.accesses 30922721 # DTB accesses +system.cpu1.numCycles 2631856202 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30860361 # Number of instructions committed -system.cpu1.committedOps 39028594 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35068610 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5870 # Number of float alu accesses -system.cpu1.num_func_calls 1089512 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4048013 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35068610 # number of integer instructions -system.cpu1.num_fp_insts 5870 # number of float instructions -system.cpu1.num_int_register_reads 201015882 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37978161 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4513 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1358 # number of times the floating registers were written -system.cpu1.num_mem_refs 13873832 # number of memory refs -system.cpu1.num_load_insts 8013211 # Number of load instructions -system.cpu1.num_store_insts 5860621 # Number of store instructions -system.cpu1.num_idle_cycles 952679619.816103 # Number of idle cycles -system.cpu1.num_busy_cycles 1676014139.183897 # Number of busy cycles -system.cpu1.not_idle_fraction 0.637584 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.362416 # Percentage of idle cycles +system.cpu1.committedInsts 30226458 # Number of instructions committed +system.cpu1.committedOps 38280743 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34395206 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5112 # Number of float alu accesses +system.cpu1.num_func_calls 1060216 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3968456 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34395206 # number of integer instructions +system.cpu1.num_fp_insts 5112 # number of float instructions +system.cpu1.num_int_register_reads 196952140 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37242776 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3939 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1174 # number of times the floating registers were written +system.cpu1.num_mem_refs 13565505 # number of memory refs +system.cpu1.num_load_insts 7793640 # Number of load instructions +system.cpu1.num_store_insts 5771865 # Number of store instructions +system.cpu1.num_idle_cycles 4920851591.451757 # Number of idle cycles +system.cpu1.num_busy_cycles -2288995389.451757 # Number of busy cycles +system.cpu1.not_idle_fraction -0.869727 # Percentage of non-idle cycles +system.cpu1.idle_fraction 1.869727 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1466,10 +1438,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1482619780500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1482619780500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478947388250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1478947388250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478947388250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1478947388250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 369e97796..da1db81af 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.125717 # Number of seconds simulated -sim_ticks 5125716951000 # Number of ticks simulated -final_tick 5125716951000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133763 # Number of seconds simulated +sim_ticks 5133762710000 # Number of ticks simulated +final_tick 5133762710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 203249 # Simulator instruction rate (inst/s) -host_op_rate 401765 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2555120499 # Simulator tick rate (ticks/s) -host_mem_usage 728844 # Number of bytes of host memory used -host_seconds 2006.06 # Real time elapsed on the host -sim_insts 407728401 # Number of instructions simulated -sim_ops 805963181 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2441920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1027200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10734912 # Number of bytes read from this memory -system.physmem.bytes_read::total 14208320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1027200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1027200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9480000 # Number of bytes written to this memory -system.physmem.bytes_written::total 9480000 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38155 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167733 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222005 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148125 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148125 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 200401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2094324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2771967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 200401 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 200401 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1849497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1849497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1849497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 200401 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2094324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4621465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222005 # Total number of read requests seen -system.physmem.writeReqs 148125 # Total number of write requests seen -system.physmem.cpureqs 371863 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14208320 # Total number of bytes read from memory -system.physmem.bytesWritten 9480000 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14208320 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9480000 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 92 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 14596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 13757 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13936 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13920 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 13971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14183 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 13262 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9305 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 9392 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 9725 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 9208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 9142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8580 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8586 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9338 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 10150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9429 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 9215 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8819 # Track writes on a per bank basis +host_inst_rate 199223 # Simulator instruction rate (inst/s) +host_op_rate 393808 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2508257843 # Simulator tick rate (ticks/s) +host_mem_usage 730904 # Number of bytes of host memory used +host_seconds 2046.74 # Real time elapsed on the host +sim_insts 407759186 # Number of instructions simulated +sim_ops 806023868 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2444032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1025408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10767936 # Number of bytes read from this memory +system.physmem.bytes_read::total 14241664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1025408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1025408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9508160 # Number of bytes written to this memory +system.physmem.bytes_written::total 9508160 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16022 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168249 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222526 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148565 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148565 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2097474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2774118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2097474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4626202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222526 # Total number of read requests seen +system.physmem.writeReqs 148565 # Total number of write requests seen +system.physmem.cpureqs 372829 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14241664 # Total number of bytes read from memory +system.physmem.bytesWritten 9508160 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14241664 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9508160 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1733 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14338 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13735 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 14393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 13573 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13175 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 13794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13620 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13949 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 13975 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 14441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14348 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 14346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 13392 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9773 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 9207 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 9622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 9014 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 9405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 9183 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8703 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 9156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 9240 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 9684 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9527 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 9658 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8799 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 5125716897500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry +system.physmem.totGap 5133762656000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 222005 # Categorize read packet sizes +system.physmem.readPktSize::6 222526 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 148125 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 174153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 864 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148565 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 174531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 849 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see @@ -136,247 +136,244 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 754 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.447836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.150732 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1279.689060 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 27741 44.45% 44.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 9677 15.51% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 5899 9.45% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 3942 6.32% 75.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2509 4.02% 79.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 2016 3.23% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1522 2.44% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1230 1.97% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 938 1.50% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 940 1.51% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 553 0.89% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 567 0.91% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 409 0.66% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 381 0.61% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 350 0.56% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 427 0.68% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 299 0.48% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 221 0.35% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 165 0.26% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 170 0.27% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 190 0.30% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 458 0.73% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 188 0.30% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 102 0.16% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 75 0.12% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 65 0.10% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 60 0.10% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 37 0.06% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 23 0.04% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 21 0.03% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 32 0.05% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 22 0.04% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 13 0.02% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 21 0.03% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 12 0.02% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 13 0.02% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 12 0.02% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 9 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 5 0.01% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 7 0.01% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 4 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 9 0.01% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 9 0.01% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 9 0.01% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 2 0.00% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 3 0.00% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 13 0.02% 98.70% # Bytes accessed per row activation +system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62801 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 377.966975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.936826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1272.632195 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 27908 44.44% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 9784 15.58% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 5938 9.46% 69.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 3957 6.30% 75.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2545 4.05% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2018 3.21% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1524 2.43% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1187 1.89% 87.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 1022 1.63% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 897 1.43% 90.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 594 0.95% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 559 0.89% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 423 0.67% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 383 0.61% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 375 0.60% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 421 0.67% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 292 0.46% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 205 0.33% 95.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 163 0.26% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 146 0.23% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 144 0.23% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 476 0.76% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 183 0.29% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 124 0.20% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 88 0.14% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 60 0.10% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 51 0.08% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 42 0.07% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 29 0.05% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 32 0.05% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 30 0.05% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 17 0.03% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 11 0.02% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 16 0.03% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 17 0.03% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 10 0.02% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 13 0.02% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 7 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 8 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 3 0.00% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 6 0.01% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 6 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 8 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 4 0.01% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 8 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 4 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.00% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 3 0.00% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 8 0.01% 98.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 5 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 4 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.00% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 22 0.04% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 5 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.00% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 5 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 3 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 3 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 6 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 5 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 3 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 7 0.01% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 4 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 4 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 3 0.00% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 4 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 5 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 27 0.04% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 3 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 4 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 3 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 3 0.00% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 8 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 3 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 3 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 2 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 2 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 4 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 3 0.00% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 3 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 3 0.00% 98.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.00% 98.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 4 0.01% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8195 337 0.54% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 7 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 10 0.02% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 3 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12995 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 3 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 34 0.05% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 5 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 3 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 7 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 7 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 6 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 11 0.02% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 13 0.02% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 65 0.10% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62409 # Bytes accessed per row activation -system.physmem.totQLat 4001177249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8265005999 # Sum of mem lat for all requests -system.physmem.totBusLat 1109565000 # Total cycles spent in databus access -system.physmem.totBankLat 3154263750 # Total cycles spent in bank access -system.physmem.avgQLat 18030.39 # Average queueing delay per request -system.physmem.avgBankLat 14213.97 # Average bank access latency per request +system.physmem.bytesPerActivate::14464-14467 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 3 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 33 0.05% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 11 0.02% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 12 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 9 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 6 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 5 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 3 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 7 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 6 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 3 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 10 0.02% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 5 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 10 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 6 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 10 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 63 0.10% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17155 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17859 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18371 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62801 # Bytes accessed per row activation +system.physmem.totQLat 4020206249 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8301079999 # Sum of mem lat for all requests +system.physmem.totBusLat 1112255000 # Total cycles spent in databus access +system.physmem.totBankLat 3168618750 # Total cycles spent in bank access +system.physmem.avgQLat 18072.32 # Average queueing delay per request +system.physmem.avgBankLat 14244.12 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37244.35 # Average memory access latency +system.physmem.avgMemAccLat 37316.44 # Average memory access latency system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s @@ -384,99 +381,99 @@ system.physmem.avgConsumedWrBW 1.85 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.40 # Average write queue length over time -system.physmem.readRowHits 198637 # Number of row buffer hits during reads -system.physmem.writeRowHits 108987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads +system.physmem.avgWrQLen 13.16 # Average write queue length over time +system.physmem.readRowHits 198897 # Number of row buffer hits during reads +system.physmem.writeRowHits 109310 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes -system.physmem.avgGap 13848423.25 # Average gap between requests -system.membus.throughput 5098961 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662131 # Transaction distribution -system.membus.trans_dist::ReadResp 662131 # Transaction distribution -system.membus.trans_dist::WriteReq 13694 # Transaction distribution -system.membus.trans_dist::WriteResp 13694 # Transaction distribution -system.membus.trans_dist::Writeback 148125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1745 # Transaction distribution -system.membus.trans_dist::ReadExReq 179249 # Transaction distribution -system.membus.trans_dist::ReadExResp 179246 # Transaction distribution -system.membus.trans_dist::MessageReq 1640 # Transaction distribution -system.membus.trans_dist::MessageResp 1640 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473788 # Packet count per connected master and slave (bytes) +system.physmem.avgGap 13834241.89 # Average gap between requests +system.membus.throughput 5102506 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662304 # Transaction distribution +system.membus.trans_dist::ReadResp 662304 # Transaction distribution +system.membus.trans_dist::WriteReq 13698 # Transaction distribution +system.membus.trans_dist::WriteResp 13698 # Transaction distribution +system.membus.trans_dist::Writeback 148565 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2229 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1751 # Transaction distribution +system.membus.trans_dist::ReadExReq 179560 # Transaction distribution +system.membus.trans_dist::ReadExResp 179558 # Transaction distribution +system.membus.trans_dist::MessageReq 1642 # Transaction distribution +system.membus.trans_dist::MessageResp 1642 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719634 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 606242 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 607688 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1855368 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18259712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1856826 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20051511 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5428608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5428608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 23688320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20110919 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5430720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5430720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 23749824 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25486679 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25486679 # Total data (bytes) -system.membus.snoop_data_through_bus 649152 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1603689497 # Layer occupancy (ticks) +system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25548207 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25548207 # Total data (bytes) +system.membus.snoop_data_through_bus 646848 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1608355497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 250319000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 250293000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 583198000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 583289000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3280000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3284000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1640000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3152452403 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3156883661 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429424246 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429399995 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 47577 # number of replacements -system.iocache.tagsinuse 0.079131 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4992752531000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.079131 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.004946 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.004946 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses -system.iocache.ReadReq_misses::total 912 # number of ReadReq misses +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103958 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006497 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses -system.iocache.demand_misses::total 47632 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses -system.iocache.overall_misses::total 47632 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152414185 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 152414185 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10346136346 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10346136346 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10498550531 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10498550531 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10498550531 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10498550531 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses +system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses +system.iocache.overall_misses::total 47629 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151796185 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151796185 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10322328602 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10322328602 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10474124787 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10474124787 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10474124787 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10474124787 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -485,40 +482,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167120.816886 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167120.816886 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221449.836173 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 221449.836173 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220409.609737 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220409.609737 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 148997 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166992.502750 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166992.502750 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 220940.252611 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 220940.252611 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 219910.659199 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 219910.659199 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 219910.659199 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 219910.659199 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 148616 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13662 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13635 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.905943 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.899597 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104973685 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104973685 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7915976600 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7915976600 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8020950285 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8020950285 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104494685 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104494685 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7891444112 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7891444112 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7995938797 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7995938797 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7995938797 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7995938797 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -527,14 +524,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115102.724781 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115102.724781 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169434.430651 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 169434.430651 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114955.649065 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114955.649065 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 168909.334589 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 168909.334589 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 167879.627895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 167879.627895 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -548,13 +545,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 639145 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225496 # Transaction distribution -system.iobus.trans_dist::ReadResp 225496 # Transaction distribution +system.iobus.throughput 638140 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225493 # Transaction distribution +system.iobus.trans_dist::ReadResp 225493 # Transaction distribution system.iobus.trans_dist::WriteReq 57527 # Transaction distribution system.iobus.trans_dist::WriteResp 57527 # Transaction distribution -system.iobus.trans_dist::MessageReq 1640 # Transaction distribution -system.iobus.trans_dist::MessageResp 1640 # Transaction distribution +system.iobus.trans_dist::MessageReq 1642 # Transaction distribution +system.iobus.trans_dist::MessageResp 1642 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) @@ -574,11 +571,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95264 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3280 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) @@ -596,9 +593,9 @@ system.iobus.pkt_count::system.pc.fake_com_2.pio 12 system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569326 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569324 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -618,11 +615,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027840 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -640,11 +637,11 @@ system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276074 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3909656 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 3276058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276058 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3920600 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -680,154 +677,154 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424474531 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424430792 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52352000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53423005 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1640000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85601186 # Number of BP lookups -system.cpu.branchPred.condPredicted 85601186 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 878782 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79197718 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77534768 # Number of BTB hits +system.cpu.branchPred.lookups 85618831 # Number of BP lookups +system.cpu.branchPred.condPredicted 85618831 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 881906 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79126559 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77540225 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.900255 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1440711 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 178764 # Number of incorrect RAS predictions. -system.cpu.numCycles 453375451 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.995194 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1441540 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180626 # Number of incorrect RAS predictions. +system.cpu.numCycles 453839632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25513858 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422800544 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85601186 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78975479 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162663365 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3996734 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 101966 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 70853615 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 42658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89309 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8479708 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 381834 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2341 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262338796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.182647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25514423 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422776164 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85618831 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78981765 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162666633 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3997481 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 100403 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71304729 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 44393 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94570 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 219 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8483452 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 380361 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2201 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262796476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.177336 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411374 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100089762 38.15% 38.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1543248 0.59% 38.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71824716 27.38% 66.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 898472 0.34% 66.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1568808 0.60% 67.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2394853 0.91% 67.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1014354 0.39% 68.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1328708 0.51% 68.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81675875 31.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100544783 38.26% 38.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1535684 0.58% 38.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71830288 27.33% 66.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 894888 0.34% 66.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1570094 0.60% 67.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2394528 0.91% 68.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1014297 0.39% 68.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1322217 0.50% 68.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81689697 31.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262338796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188809 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.932562 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29417456 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68001358 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158506679 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3339559 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3073744 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832592947 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 926 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3073744 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32109829 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 42827309 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12461023 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158801746 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13065145 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829696742 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21430 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6044181 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5137835 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 10653 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 991365298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800497636 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1800497180 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963871300 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27493996 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 453983 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 458205 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29510312 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16729516 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9820056 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1138043 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 956999 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824928716 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1184630 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820966425 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 150849 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19304203 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29360127 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 130755 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262338796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.129413 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.399539 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262796476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188654 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931554 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29415381 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68460720 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158509709 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3339560 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3071106 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832655242 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 935 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3071106 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32114015 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43120028 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12611794 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158799152 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13080381 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829727330 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21673 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6047730 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5146675 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 9377 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 991375726 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800594508 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1800594068 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 440 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963942859 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27432865 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 453030 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459006 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29568179 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16736842 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9827220 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1098890 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 921986 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824947174 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1184809 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820992991 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 145624 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19292542 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29357019 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 130694 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262796476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.124064 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.400943 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75996420 28.97% 28.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15740261 6.00% 34.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10531012 4.01% 38.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7367834 2.81% 41.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75736075 28.87% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3750663 1.43% 72.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72297854 27.56% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 773517 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 145160 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76438982 29.09% 29.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15751400 5.99% 35.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10538627 4.01% 39.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7358771 2.80% 41.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75737390 28.82% 70.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3750331 1.43% 72.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72306613 27.51% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 767765 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 146597 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262338796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262796476 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 351269 33.33% 33.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 200 0.02% 33.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1810 0.17% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547247 51.93% 85.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153387 14.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 351017 33.38% 33.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 33.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 348 0.03% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547344 52.04% 85.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152992 14.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 304863 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793498796 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149830 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124227 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308184 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793508376 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149615 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124401 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -854,280 +851,280 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17669358 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9219351 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17677574 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9224841 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820966425 # Type of FU issued -system.cpu.iq.rate 1.810787 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1053913 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905583532 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845427964 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817056658 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821715388 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1694689 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820992991 # Type of FU issued +system.cpu.iq.rate 1.808994 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1051702 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001281 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906088677 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845434927 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817071068 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 189 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821736420 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 89 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1694381 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2746767 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18051 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1403061 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2750139 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17720 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12102 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1408836 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931249 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12313 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931381 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3073744 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30976434 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2152665 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826113346 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 242094 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16729516 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9820056 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 689859 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1619870 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14784 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 494405 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508019 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1002424 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819559028 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17368747 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1407396 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3071106 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31257120 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2152669 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826131983 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 242676 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16736842 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9827220 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 690491 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620064 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13028 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12102 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 497258 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506632 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1003890 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819577252 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17369785 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1415738 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26403485 # number of memory reference insts executed -system.cpu.iew.exec_branches 83095032 # Number of branches executed -system.cpu.iew.exec_stores 9034738 # Number of stores executed -system.cpu.iew.exec_rate 1.807683 # Inst execution rate -system.cpu.iew.wb_sent 819157526 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817056708 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638600685 # num instructions producing a value -system.cpu.iew.wb_consumers 1043925557 # num instructions consuming a value +system.cpu.iew.exec_refs 26409608 # number of memory reference insts executed +system.cpu.iew.exec_branches 83098710 # Number of branches executed +system.cpu.iew.exec_stores 9039823 # Number of stores executed +system.cpu.iew.exec_rate 1.805874 # Inst execution rate +system.cpu.iew.wb_sent 819172462 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817071124 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638600161 # num instructions producing a value +system.cpu.iew.wb_consumers 1043929120 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.802164 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800352 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 20041054 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1053875 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 888667 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259265052 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.108646 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863485 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19998846 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054115 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 892238 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259725370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.103370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863932 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87759364 33.85% 33.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11842879 4.57% 38.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3826328 1.48% 39.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74742270 28.83% 68.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2381968 0.92% 69.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1473831 0.57% 70.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 858574 0.33% 70.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70846339 27.33% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5533499 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88203628 33.96% 33.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11848657 4.56% 38.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3832219 1.48% 40.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74739253 28.78% 68.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2381920 0.92% 69.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1474779 0.57% 70.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 859132 0.33% 70.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70849609 27.28% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5536173 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259265052 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407728401 # Number of instructions committed -system.cpu.commit.committedOps 805963181 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259725370 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407759186 # Number of instructions committed +system.cpu.commit.committedOps 806023868 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22399743 # Number of memory references committed -system.cpu.commit.loads 13982748 # Number of loads committed -system.cpu.commit.membars 474399 # Number of memory barriers committed -system.cpu.commit.branches 82153759 # Number of branches committed +system.cpu.commit.refs 22405086 # Number of memory references committed +system.cpu.commit.loads 13986702 # Number of loads committed +system.cpu.commit.membars 474409 # Number of memory barriers committed +system.cpu.commit.branches 82159690 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734952654 # Number of committed integer instructions. -system.cpu.commit.function_calls 1154691 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5533499 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 735008844 # Number of committed integer instructions. +system.cpu.commit.function_calls 1154896 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5536173 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079657633 # The number of ROB reads -system.cpu.rob.rob_writes 1655096826 # The number of ROB writes -system.cpu.timesIdled 1258785 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 191036655 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9798064041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407728401 # Number of Instructions Simulated -system.cpu.committedOps 805963181 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407728401 # Number of Instructions Simulated -system.cpu.cpi 1.111955 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.111955 # CPI: Total CPI of All Threads -system.cpu.ipc 0.899317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.899317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1504349061 # number of integer regfile reads -system.cpu.int_regfile_writes 975319683 # number of integer regfile writes -system.cpu.fp_regfile_reads 50 # number of floating regfile reads -system.cpu.misc_regfile_reads 264080509 # number of misc regfile reads -system.cpu.misc_regfile_writes 401987 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53625221 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3010668 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3010129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13694 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13694 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1578360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334262 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287551 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1907708 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6121795 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 17377 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 150658 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 8197538 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61043136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207549047 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 553408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5256448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 274402039 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274377591 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 490112 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4031070918 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1080133651 # The number of ROB reads +system.cpu.rob.rob_writes 1655131261 # The number of ROB writes +system.cpu.timesIdled 1259877 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 191043156 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9813691352 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407759186 # Number of Instructions Simulated +system.cpu.committedOps 806023868 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407759186 # Number of Instructions Simulated +system.cpu.cpi 1.113009 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.113009 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898465 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898465 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1504423855 # number of integer regfile reads +system.cpu.int_regfile_writes 975340027 # number of integer regfile writes +system.cpu.fp_regfile_reads 56 # number of floating regfile reads +system.cpu.misc_regfile_reads 264091330 # number of misc regfile reads +system.cpu.misc_regfile_writes 402284 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53596956 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3010019 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3009469 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1583020 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288025 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1906694 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6122854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 16266 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 154977 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 8200791 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61010496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207591623 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 510912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5512832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 274625863 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274602311 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 551744 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4037956918 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 552000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1431698822 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1434043234 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3102593965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3142652791 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 13102485 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 12430241 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 102839393 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 103328135 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 953322 # number of replacements -system.cpu.icache.tagsinuse 510.127378 # Cycle average of tags in use -system.cpu.icache.total_refs 7473092 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 953834 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.834793 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 147390294000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.127378 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996343 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996343 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7473092 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7473092 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7473092 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7473092 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7473092 # number of overall hits -system.cpu.icache.overall_hits::total 7473092 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1006614 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1006614 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1006614 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1006614 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1006614 # number of overall misses -system.cpu.icache.overall_misses::total 1006614 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14222924496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14222924496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14222924496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14222924496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14222924496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14222924496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8479706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8479706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8479706 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8479706 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8479706 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8479706 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118709 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118709 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118709 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118709 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118709 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118709 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14129.472167 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14129.472167 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14129.472167 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14129.472167 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8172 # number of cycles access was blocked +system.cpu.icache.tags.replacements 952820 # number of replacements +system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7477461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7477461 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7477461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7477461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7477461 # number of overall hits +system.cpu.icache.overall_hits::total 7477461 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1005989 # number of overall misses +system.cpu.icache.overall_misses::total 1005989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14232079935 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14232079935 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14232079935 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14232079935 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14232079935 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14232079935 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8483450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8483450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8483450 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8483450 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8483450 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8483450 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118583 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.118583 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.118583 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.118583 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.118583 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.118583 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14147.351447 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14147.351447 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14147.351447 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14147.351447 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14147.351447 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14147.351447 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 174 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.238095 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35.580460 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52705 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52705 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52705 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52705 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52705 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52705 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953909 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 953909 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 953909 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 953909 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 953909 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 953909 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11745970674 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11745970674 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11745970674 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11745970674 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11745970674 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11745970674 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112493 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112493 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112493 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12313.512792 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12313.512792 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52584 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 52584 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 52584 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 52584 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 52584 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 52584 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953405 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 953405 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 953405 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 953405 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 953405 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 953405 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11737352011 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11737352011 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11737352011 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11737352011 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11737352011 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11737352011 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112384 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112384 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112384 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12310.982228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12310.982228 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12310.982228 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12310.982228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 7857 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.317656 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 21864 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 7868 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.778851 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5104284128000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.317656 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.394853 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.394853 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21875 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 21875 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 7402 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 7416 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5104253177000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006857 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375429 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.375429 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21911 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21911 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21877 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 21877 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21877 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 21877 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8730 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 8730 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8730 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 8730 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8730 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 8730 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 99800500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 99800500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 99800500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 99800500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 99800500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 99800500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30605 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30605 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21913 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 21913 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21913 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21913 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8283 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8283 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8283 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8283 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8283 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8283 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 92582993 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 92582993 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 92582993 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 92582993 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 92582993 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 92582993 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30194 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30194 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30607 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30607 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30607 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30607 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285248 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285248 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285229 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.285229 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285229 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.285229 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11431.901489 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11431.901489 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11431.901489 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11431.901489 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30196 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30196 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30196 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30196 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.274326 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.274326 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.274308 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.274308 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.274308 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.274308 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11177.471085 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11177.471085 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11177.471085 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11177.471085 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11177.471085 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11177.471085 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1136,78 +1133,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1569 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1569 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8730 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8730 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8730 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 8730 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8730 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 8730 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 82333015 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 82333015 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 82333015 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 82333015 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 82333015 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 82333015 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285248 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285248 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9431.044101 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1499 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1499 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8283 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8283 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8283 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 8283 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8283 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 8283 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 76005511 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 76005511 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 76005511 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 76005511 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 76005511 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 76005511 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.274326 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.274326 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.274308 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.274308 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.274308 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.274308 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9176.084873 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 67431 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 14.830291 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 90986 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 67447 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.349000 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 4994048518000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.830291 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.926893 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.926893 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90986 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 90986 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90986 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 90986 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90986 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 90986 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68526 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 68526 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68526 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 68526 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68526 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 68526 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854232500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854232500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854232500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 854232500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854232500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 854232500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 159512 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 159512 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 159512 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 159512 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 159512 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 159512 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429598 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429598 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429598 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429598 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429598 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429598 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.815895 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.815895 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.815895 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.815895 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 67804 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 13.886481 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 92487 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 67819 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.363733 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101460528500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.886481 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.867905 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.867905 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92498 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92498 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92498 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92498 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92498 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92498 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68839 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 68839 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68839 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 68839 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68839 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 68839 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 851625712 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 851625712 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 851625712 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 851625712 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 851625712 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 851625712 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161337 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 161337 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161337 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 161337 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161337 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 161337 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.426678 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.426678 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.426678 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.426678 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.426678 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.426678 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12371.267915 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12371.267915 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12371.267915 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12371.267915 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12371.267915 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12371.267915 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1216,146 +1213,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 18479 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 18479 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68526 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68526 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68526 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 68526 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68526 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 68526 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 717130107 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 717130107 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 717130107 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 717130107 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 717130107 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 717130107 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429598 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429598 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429598 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.080510 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 23017 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 23017 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68839 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68839 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68839 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 68839 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68839 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 68839 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 713808442 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 713808442 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 713808442 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 713808442 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 713808442 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 713808442 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.426678 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.426678 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.426678 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10369.244789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1656381 # number of replacements -system.cpu.dcache.tagsinuse 511.996762 # Cycle average of tags in use -system.cpu.dcache.total_refs 18981789 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1656893 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.456255 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 37864000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.996762 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10887156 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10887156 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8091896 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8091896 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18979052 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18979052 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18979052 # number of overall hits -system.cpu.dcache.overall_hits::total 18979052 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2237799 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2237799 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315625 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315625 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2553424 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2553424 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2553424 # number of overall misses -system.cpu.dcache.overall_misses::total 2553424 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33108471000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33108471000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12021128996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12021128996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45129599996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45129599996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45129599996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45129599996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13124955 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13124955 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8407521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8407521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21532476 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21532476 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21532476 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21532476 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170500 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170500 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037541 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037541 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118585 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118585 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118585 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118585 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14795.104922 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14795.104922 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38086.745334 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38086.745334 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17674.150472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17674.150472 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 405217 # number of cycles access was blocked +system.cpu.dcache.tags.replacements 1656828 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18985847 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657340 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.455614 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10890330 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10890330 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8092849 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8092849 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18983179 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18983179 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18983179 # number of overall hits +system.cpu.dcache.overall_hits::total 18983179 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2236067 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2236067 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316060 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316060 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2552127 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2552127 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2552127 # number of overall misses +system.cpu.dcache.overall_misses::total 2552127 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33180539725 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33180539725 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12164482246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12164482246 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45345021971 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45345021971 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45345021971 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45345021971 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13126397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13126397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8408909 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8408909 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21535306 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21535306 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21535306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21535306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170349 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170349 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037586 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037586 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118509 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118509 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118509 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118509 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.794958 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.794958 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38487.889154 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38487.889154 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17767.541337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17767.541337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17767.541337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17767.541337 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 401774 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42719 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42434 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.485639 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.468209 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558312 # number of writebacks -system.cpu.dcache.writebacks::total 1558312 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868331 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 868331 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25900 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25900 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 894231 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 894231 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 894231 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 894231 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1369468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289725 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289725 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1659193 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1659193 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1659193 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1659193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17883109030 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17883109030 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11189452001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11189452001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29072561031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29072561031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29072561031 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29072561031 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349104500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349104500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2521383000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2521383000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99870487500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99870487500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104341 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104341 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034460 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034460 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077055 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077055 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077055 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077055 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13058.435122 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13058.435122 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38620.940551 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38620.940551 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17522.109261 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17522.109261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17522.109261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17522.109261 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1558504 # number of writebacks +system.cpu.dcache.writebacks::total 1558504 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866614 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 866614 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3778363799 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15641444 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15641444 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7710305096 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7710305096 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6018750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 353750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1186972764 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10295323631 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11488668895 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91593812000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91593812000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000771 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016807 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026358 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.828895 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.828895 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.462230 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.462230 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000771 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016807 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102129 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069148 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000771 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016807 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102129 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.069148 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74083.932343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71652.813011 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72429.624641 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.349282 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.349282 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57917.349699 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57917.349699 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74083.932343 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60845.987548 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62003.048675 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74083.932343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60845.987548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62003.048675 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 0632af65b..551b52f89 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,150 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.143601 # Number of seconds simulated -sim_ticks 5143601047500 # Number of ticks simulated -final_tick 5143601047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.139589 # Number of seconds simulated +sim_ticks 5139589353000 # Number of ticks simulated +final_tick 5139589353000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 255414 # Simulator instruction rate (inst/s) -host_op_rate 507504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5398723492 # Simulator tick rate (ticks/s) -host_mem_usage 908456 # Number of bytes of host memory used -host_seconds 952.74 # Real time elapsed on the host -sim_insts 243343656 # Number of instructions simulated -sim_ops 483521256 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2435392 # Number of bytes read from this memory +host_inst_rate 286755 # Simulator instruction rate (inst/s) +host_op_rate 569759 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6048900638 # Simulator tick rate (ticks/s) +host_mem_usage 936564 # Number of bytes of host memory used +host_seconds 849.67 # Real time elapsed on the host +sim_insts 243647713 # Number of instructions simulated +sim_ops 484108731 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2450688 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6105280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 134592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1637632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 319296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2611264 # Number of bytes read from this memory -system.physmem.bytes_read::total 13733504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 134592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 319296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 942336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9060160 # Number of bytes written to this memory -system.physmem.bytes_written::total 9060160 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38053 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 424832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5722240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 151040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1810944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 372032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2837824 # Number of bytes read from this memory +system.physmem.bytes_read::total 13771904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 424832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 372032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 947904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9105344 # Number of bytes written to this memory +system.physmem.bytes_written::total 9105344 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38292 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 95395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2103 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 25588 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 40801 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214586 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141565 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141565 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 473480 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6638 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 89410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 28296 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 30 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5813 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 44341 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215186 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142271 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142271 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476826 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 94962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1186966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 318382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 62076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 507672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2670017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 94962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 62076 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 183205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1761443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1761443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1761443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 473480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1113365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 352352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 72386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 552150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2679573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82659 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29388 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 72386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 184432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1771609 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1771609 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1771609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476826 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 94962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1186966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 318382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 62076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 507672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4431460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 90446 # Total number of read requests seen -system.physmem.writeReqs 70433 # Total number of write requests seen -system.physmem.cpureqs 161351 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 5788544 # Total number of bytes read from memory -system.physmem.bytesWritten 4507712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 5788544 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4507712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 472 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 5853 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 5374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 5163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 5410 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5863 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 5951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6069 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 4669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 5184 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 5694 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 5914 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 5934 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4493 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4309 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4025 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4752 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4893 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3464 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 3572 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4337 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4609 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4582 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4499 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 82659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1113365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 352352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 72386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 552150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4451182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 96603 # Total number of read requests seen +system.physmem.writeReqs 74912 # Total number of write requests seen +system.physmem.cpureqs 172248 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 6182592 # Total number of bytes read from memory +system.physmem.bytesWritten 4794368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6182592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 4794368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 732 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 5743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 5750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 5839 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6289 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 5688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 5956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 5856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 5878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 6204 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6230 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 5996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6119 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4526 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4556 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4674 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4937 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4457 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4557 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4265 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4556 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5050 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4641 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4582 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4382 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 5140092000000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry +system.physmem.totGap 5136024228000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 90446 # Categorize read packet sizes +system.physmem.readPktSize::6 96603 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 70433 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 70577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 74912 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 77105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,522 +160,533 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 30233 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.294645 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 151.805560 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1124.042449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13536 44.77% 44.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 4627 15.30% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 2854 9.44% 69.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 1864 6.17% 75.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1230 4.07% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1007 3.33% 83.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 772 2.55% 85.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 598 1.98% 87.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 458 1.51% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 438 1.45% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 281 0.93% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 279 0.92% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 209 0.69% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 207 0.68% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 177 0.59% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 236 0.78% 95.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 132 0.44% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 98 0.32% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 103 0.34% 96.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 81 0.27% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 87 0.29% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 80 0.26% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 236 0.78% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 88 0.29% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 47 0.16% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 40 0.13% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 31 0.10% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 30 0.10% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 19 0.06% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 16 0.05% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 8 0.03% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 13 0.04% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 5 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 8 0.03% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 4 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 5 0.02% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 9 0.03% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 4 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 4 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 2 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 4 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 2 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 4 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 5 0.02% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 2 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 5 0.02% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 7 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 6 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 12 0.04% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 2 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 3 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 3 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 4 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 2 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 29 0.10% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 3 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 2 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 2 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 2 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 15 0.05% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 11 0.04% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 6 0.02% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 3 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 33252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.902562 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.864384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1038.972369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14693 44.19% 44.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5121 15.40% 59.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3144 9.46% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2114 6.36% 75.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1414 4.25% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1109 3.34% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 834 2.51% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 672 2.02% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 527 1.58% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 500 1.50% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 311 0.94% 91.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 308 0.93% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 231 0.69% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 204 0.61% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 157 0.47% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 279 0.84% 95.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 147 0.44% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 117 0.35% 95.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 74 0.22% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 80 0.24% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 100 0.30% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 111 0.33% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 291 0.88% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 116 0.35% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 63 0.19% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 43 0.13% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 35 0.11% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 34 0.10% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 18 0.05% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 13 0.04% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 14 0.04% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 17 0.05% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 9 0.03% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 4 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 7 0.02% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 10 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 7 0.02% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.02% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 8 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 9 0.03% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 6 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 2 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 2 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 6 0.02% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 5 0.02% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 2 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 3 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 3 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 5 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 5 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 4 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 2 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 3 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 29 0.09% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 2 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 2 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 2 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 2 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 2 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 11 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 4 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 2 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 2 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 2 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 5 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 2 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 5 0.02% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 2 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 3 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 21 0.07% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 30233 # Bytes accessed per row activation -system.physmem.totQLat 1718746250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3502520000 # Sum of mem lat for all requests -system.physmem.totBusLat 452100000 # Total cycles spent in databus access -system.physmem.totBankLat 1331673750 # Total cycles spent in bank access -system.physmem.avgQLat 19008.47 # Average queueing delay per request -system.physmem.avgBankLat 14727.65 # Average bank access latency per request +system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 2 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 5 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 2 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 5 0.02% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 2 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 27 0.08% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 33252 # Bytes accessed per row activation +system.physmem.totQLat 1788062000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3723402000 # Sum of mem lat for all requests +system.physmem.totBusLat 482955000 # Total cycles spent in databus access +system.physmem.totBankLat 1452385000 # Total cycles spent in bank access +system.physmem.avgQLat 18511.68 # Average queueing delay per request +system.physmem.avgBankLat 15036.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38736.12 # Average memory access latency -system.physmem.avgRdBW 1.13 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.88 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1.13 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.88 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38548.13 # Average memory access latency +system.physmem.avgRdBW 1.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.93 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.11 # Average write queue length over time -system.physmem.readRowHits 78857 # Number of row buffer hits during reads -system.physmem.writeRowHits 51763 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.49 # Row buffer hit rate for writes -system.physmem.avgGap 31950049.42 # Average gap between requests -system.membus.throughput 6398386 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 425816 # Transaction distribution -system.membus.trans_dist::ReadResp 425816 # Transaction distribution -system.membus.trans_dist::WriteReq 5631 # Transaction distribution -system.membus.trans_dist::WriteResp 5631 # Transaction distribution -system.membus.trans_dist::Writeback 70433 # Transaction distribution -system.membus.trans_dist::UpgradeReq 476 # Transaction distribution -system.membus.trans_dist::UpgradeResp 476 # Transaction distribution -system.membus.trans_dist::ReadExReq 69519 # Transaction distribution -system.membus.trans_dist::ReadExResp 69519 # Transaction distribution -system.membus.trans_dist::MessageReq 269 # Transaction distribution -system.membus.trans_dist::MessageResp 269 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 197349 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1007895 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 60171 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 60171 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 257520 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 312424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu0.interrupts.pio 498122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu0.interrupts.int_slave 538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1068604 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 1076 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 1076 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7851072 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159641 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996241 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9006954 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2445184 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2445184 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 10296256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 159641 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996241 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 1076 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 11453214 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32574935 # Total data (bytes) -system.membus.snoop_data_through_bus 335808 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 770602000 # Layer occupancy (ticks) +system.physmem.readRowHits 84146 # Number of row buffer hits during reads +system.physmem.writeRowHits 54105 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.22 # Row buffer hit rate for writes +system.physmem.avgGap 29945044.04 # Average gap between requests +system.membus.throughput 6414834 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 427545 # Transaction distribution +system.membus.trans_dist::ReadResp 427545 # Transaction distribution +system.membus.trans_dist::WriteReq 5661 # Transaction distribution +system.membus.trans_dist::WriteResp 5661 # Transaction distribution +system.membus.trans_dist::Writeback 74912 # Transaction distribution +system.membus.trans_dist::UpgradeReq 735 # Transaction distribution +system.membus.trans_dist::UpgradeResp 735 # Transaction distribution +system.membus.trans_dist::ReadExReq 72970 # Transaction distribution +system.membus.trans_dist::ReadExResp 72970 # Transaction distribution +system.membus.trans_dist::MessageReq 216 # Transaction distribution +system.membus.trans_dist::MessageResp 216 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312952 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1030222 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 54502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 54502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 273592 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 312952 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1085156 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9889556 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2243648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2243648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 10976960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12134068 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32713165 # Total data (bytes) +system.membus.snoop_data_through_bus 256448 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 793885999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 164025500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 164366000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 314786000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 314753000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 538000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 432000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 269000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 216000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1575668988 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1632166487 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 198012000 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 175306750 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.replacements 103562 # number of replacements -system.l2c.tagsinuse 64796.800964 # Cycle average of tags in use -system.l2c.total_refs 3619781 # Total number of references to valid blocks. -system.l2c.sampled_refs 167743 # Sample count of references to valid blocks. -system.l2c.avg_refs 21.579327 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 51276.359665 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.126176 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 1273.083994 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4560.482374 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 265.925814 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 1312.167499 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 5.741812 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1370.746219 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 4732.167410 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.782415 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.019426 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.069587 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.004058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.020022 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000088 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.020916 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.072207 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.988721 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 380736 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 540863 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5306 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2771 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 154822 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 225347 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 39624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 7543 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 294341 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 531967 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2216094 # number of ReadReq hits +system.l2c.tags.replacements 104154 # number of replacements +system.l2c.tags.tagsinuse 64818.882502 # Cycle average of tags in use +system.l2c.tags.total_refs 3632248 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168346 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.576087 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 51171.986670 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125486 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1262.785068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4574.642727 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 231.301246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1356.639626 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.163681 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.039070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1464.364249 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4745.834679 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.780823 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.019269 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.069804 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.020701 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.022344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.072416 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989058 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 20178 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11162 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 357762 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 528228 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4903 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 153273 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 226490 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 46782 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 8793 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 321700 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 546165 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2227865 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1541993 # number of Writeback hits -system.l2c.Writeback_hits::total 1541993 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 185 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 34 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 34 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 253 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 81134 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 39930 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 50435 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171499 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11249 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 380736 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 621997 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5306 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2771 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 154822 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 265277 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 39624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 7543 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 294341 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 582402 # number of demand (read+write) hits -system.l2c.demand_hits::total 2387595 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21527 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11249 # number of overall hits -system.l2c.overall_hits::cpu0.inst 380736 # number of overall hits -system.l2c.overall_hits::cpu0.data 621997 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5306 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2771 # number of overall hits -system.l2c.overall_hits::cpu1.inst 154822 # number of overall hits -system.l2c.overall_hits::cpu1.data 265277 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 39624 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 7543 # number of overall hits -system.l2c.overall_hits::cpu2.inst 294341 # number of overall hits -system.l2c.overall_hits::cpu2.data 582402 # number of overall hits -system.l2c.overall_hits::total 2387595 # number of overall hits +system.l2c.Writeback_hits::writebacks 1544497 # number of Writeback hits +system.l2c.Writeback_hits::total 1544497 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 143 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 76 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 255 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 71037 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 43117 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 57018 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 171172 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 20178 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 11164 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 357762 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 599265 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4903 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 153273 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 269607 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 46782 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 8793 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 321700 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 603183 # number of demand (read+write) hits +system.l2c.demand_hits::total 2399039 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 20178 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 11164 # number of overall hits +system.l2c.overall_hits::cpu0.inst 357762 # number of overall hits +system.l2c.overall_hits::cpu0.data 599265 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4903 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits +system.l2c.overall_hits::cpu1.inst 153273 # number of overall hits +system.l2c.overall_hits::cpu1.data 269607 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 46782 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 8793 # number of overall hits +system.l2c.overall_hits::cpu2.inst 321700 # number of overall hits +system.l2c.overall_hits::cpu2.data 603183 # number of overall hits +system.l2c.overall_hits::total 2399039 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7632 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 14556 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2103 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4151 # 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number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47634 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47634 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -844,60 +874,60 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145447.587912 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145447.587912 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 99235.135595 # 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number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 701 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 701 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 21264 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 21264 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 21965 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 21965 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 21965 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 21965 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95889055 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 95889055 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3530226785 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3530226785 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3626115840 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3626115840 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.770330 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.770330 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.455137 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.455137 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.461159 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.461159 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 136788.951498 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136788.951498 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 166018.942109 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 166018.942109 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 165086.084225 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 165086.084225 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 149 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 149 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 19296 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 19296 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 19445 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 19445 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 19445 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 19445 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 9180907 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 9180907 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3283180510 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3283180510 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3292361417 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3292361417 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3292361417 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3292361417 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.163020 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.163020 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.413014 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.413014 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.408217 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.408217 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.408217 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.408217 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 61616.825503 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 61616.825503 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 170148.243677 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 170148.243677 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169316.606686 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 169316.606686 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169316.606686 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 169316.606686 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -907,488 +937,488 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52020310 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1696057 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1695532 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 5631 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 5631 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 870189 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 384 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 384 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 160044 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 138785 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 912543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3510594 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 23321 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 95695 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 4542153 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29200384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 115384682 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 82512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 359600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 145027178 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 267476487 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 95232 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4838788408 # Layer occupancy (ticks) +system.toL2Bus.throughput 52172743 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1753367 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1753366 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 5661 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 5661 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 894976 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 745 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 745 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 173207 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 153920 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 966317 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3599461 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 26176 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 114965 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 4706919 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 30921472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118979348 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 89784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 413728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 150404332 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 267998065 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 148408 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4987080585 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 814500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 706500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2054232112 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2176927347 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4517736918 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4676438168 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13025458 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 14970214 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 50823334 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 63358037 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1261125 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 151553 # Transaction distribution -system.iobus.trans_dist::ReadResp 151553 # Transaction distribution -system.iobus.trans_dist::WriteReq 26624 # Transaction distribution -system.iobus.trans_dist::WriteResp 26624 # Transaction distribution -system.iobus.trans_dist::MessageReq 269 # Transaction distribution -system.iobus.trans_dist::MessageResp 269 # Transaction distribution +system.iobus.throughput 1260736 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 151186 # Transaction distribution +system.iobus.trans_dist::ReadResp 151186 # Transaction distribution +system.iobus.trans_dist::WriteReq 24735 # Transaction distribution +system.iobus.trans_dist::WriteResp 24735 # Transaction distribution +system.iobus.trans_dist::MessageReq 216 # Transaction distribution +system.iobus.trans_dist::MessageResp 216 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 290304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 312424 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 43930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 43930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 538 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 538 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 312952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 38890 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 432 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.com_1.pio 15696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 43930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 356892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 352274 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 145152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 108 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 159641 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1396968 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1396968 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1076 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 1076 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 1076 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 159887 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1236136 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 864 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 108 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.com_1.pio 7848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 1396968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1557685 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6486722 # Total data (bytes) -system.iobus.reqLayer0.occupancy 624016 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 1396887 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6479664 # Total data (bytes) +system.iobus.reqLayer0.occupancy 492564 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3409000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 3525000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 24000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 145153000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 145313000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 43000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11757000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11833000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 193475840 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 175039167 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 307064000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 307513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 26474000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 20042250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 269000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 216000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1771999673 # number of cpu cycles simulated +system.cpu0.numCycles 1821353005 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 74314462 # Number of instructions committed -system.cpu0.committedOps 150407349 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 138687072 # Number of integer alu accesses +system.cpu0.committedInsts 73292155 # Number of instructions committed +system.cpu0.committedOps 148692338 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136997121 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1088594 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14472613 # number of instructions that are conditional controls -system.cpu0.num_int_insts 138687072 # number of integer instructions +system.cpu0.num_func_calls 1072392 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14299557 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136997121 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 341744011 # number of times the integer registers were read -system.cpu0.num_int_register_writes 175930003 # number of times the integer registers were written +system.cpu0.num_int_register_reads 337067923 # number of times the integer registers were read +system.cpu0.num_int_register_writes 173978676 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 15165282 # number of memory refs -system.cpu0.num_load_insts 10883561 # Number of load instructions -system.cpu0.num_store_insts 4281721 # Number of store instructions -system.cpu0.num_idle_cycles 1050845405256.983643 # Number of idle cycles -system.cpu0.num_busy_cycles -1049073405583.983643 # Number of busy cycles -system.cpu0.not_idle_fraction -592.027991 # Percentage of non-idle cycles -system.cpu0.idle_fraction 593.027991 # Percentage of idle cycles +system.cpu0.num_mem_refs 14736464 # number of memory refs +system.cpu0.num_load_insts 10677140 # Number of load instructions +system.cpu0.num_store_insts 4059324 # Number of store instructions +system.cpu0.num_idle_cycles 1078995887905.232788 # Number of idle cycles +system.cpu0.num_busy_cycles -1077174534900.232788 # Number of busy cycles +system.cpu0.not_idle_fraction -591.414477 # Percentage of non-idle cycles +system.cpu0.idle_fraction 592.414477 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.replacements 844132 # number of replacements -system.cpu0.icache.tagsinuse 510.847733 # Cycle average of tags in use -system.cpu0.icache.total_refs 131418089 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 844644 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 155.589916 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 147339657000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 322.177037 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 98.355742 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 90.314955 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.629252 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.192101 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.176396 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.997749 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 90666828 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38386818 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2364443 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 131418089 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 90666828 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38386818 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2364443 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 131418089 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 90666828 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38386818 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2364443 # number of overall hits -system.cpu0.icache.overall_hits::total 131418089 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 388368 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 156925 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 315252 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 860545 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 388368 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 156925 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 315252 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 860545 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 388368 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 156925 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 315252 # number of overall misses -system.cpu0.icache.overall_misses::total 860545 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2194798000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4530444487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6725242487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2194798000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4530444487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6725242487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2194798000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4530444487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6725242487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 91055196 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 38543743 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2679695 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 132278634 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 91055196 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 38543743 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2679695 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 132278634 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 91055196 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 38543743 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2679695 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 132278634 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004265 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004071 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117645 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006506 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004265 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004071 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117645 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006506 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004265 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004071 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117645 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006506 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13986.286443 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14370.866757 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7815.096813 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13986.286443 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14370.866757 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7815.096813 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13986.286443 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14370.866757 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7815.096813 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6390 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 847048 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.817647 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129995405 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 847560 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 153.376050 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147328649500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.566465 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 97.238420 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 93.012763 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.626106 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.189919 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.181666 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997691 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 89325030 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38126450 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2543925 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 129995405 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 89325030 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38126450 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2543925 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 129995405 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 89325030 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38126450 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2543925 # number of overall hits +system.cpu0.icache.overall_hits::total 129995405 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 364401 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 155633 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 345614 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 865648 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 364401 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 155633 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 345614 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 865648 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 364401 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 155633 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 345614 # number of overall misses +system.cpu0.icache.overall_misses::total 865648 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2193404000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5014378720 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7207782720 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2193404000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5014378720 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7207782720 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2193404000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5014378720 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7207782720 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 89689431 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38282083 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2889539 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130861053 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 89689431 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38282083 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2889539 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130861053 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 89689431 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38282083 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2889539 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130861053 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004063 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004065 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.119609 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006615 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004063 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004065 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.119609 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006615 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004063 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004065 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.119609 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006615 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14093.437767 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14508.609952 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8326.459161 # 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number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33915259000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65373414500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.094111 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.121016 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.059786 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.041955 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031820 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018396 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.073535 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087809 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.043719 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.073535 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087809 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.043719 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12423.553814 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14864.727994 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14151.930803 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32464.052346 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33520.670986 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33061.650711 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16934.259250 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17381.606187 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17240.578184 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16934.259250 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17381.606187 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17240.578184 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1399,303 +1429,303 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608004713 # number of cpu cycles simulated +system.cpu1.numCycles 2606005785 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34942757 # Number of instructions committed -system.cpu1.committedOps 68016284 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 63114732 # Number of integer alu accesses +system.cpu1.committedInsts 34706075 # Number of instructions committed +system.cpu1.committedOps 67513326 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 62627092 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 430753 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6467325 # number of instructions that are conditional controls -system.cpu1.num_int_insts 63114732 # number of integer instructions +system.cpu1.num_func_calls 413647 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6441517 # number of instructions that are conditional controls +system.cpu1.num_int_insts 62627092 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 152021040 # number of times the integer registers were read -system.cpu1.num_int_register_writes 81233840 # number of times the integer registers were written +system.cpu1.num_int_register_reads 150899030 # number of times the integer registers were read +system.cpu1.num_int_register_writes 80614256 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 4322210 # number of memory refs -system.cpu1.num_load_insts 2726743 # Number of load instructions -system.cpu1.num_store_insts 1595467 # Number of store instructions -system.cpu1.num_idle_cycles 9296961839.327438 # Number of idle cycles -system.cpu1.num_busy_cycles -6688957126.327438 # Number of busy cycles -system.cpu1.not_idle_fraction -2.564780 # Percentage of non-idle cycles -system.cpu1.idle_fraction 3.564780 # Percentage of idle cycles +system.cpu1.num_mem_refs 4252332 # number of memory refs +system.cpu1.num_load_insts 2649427 # Number of load instructions +system.cpu1.num_store_insts 1602905 # Number of store instructions +system.cpu1.num_idle_cycles 9584663693.774578 # Number of idle cycles +system.cpu1.num_busy_cycles -6978657908.774579 # Number of busy cycles +system.cpu1.not_idle_fraction -2.677913 # Percentage of non-idle cycles +system.cpu1.idle_fraction 3.677913 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28107723 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28107723 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 253065 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 25890078 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25466613 # Number of BTB hits +system.cpu2.branchPred.lookups 28549199 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28549199 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 285864 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26202333 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25707724 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.364373 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 482621 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 53231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 150677905 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 98.112347 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 509000 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 57796 # Number of incorrect RAS predictions. +system.cpu2.numCycles 153739924 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8157389 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 138649085 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28107723 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 25949234 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 53330196 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1190060 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 46897 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 22689996 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 1645 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6110 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 10082 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2679696 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 114342 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1368 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 85168083 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.213895 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.414010 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8861182 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 140768018 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28549199 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26216724 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54013734 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1344784 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 58192 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 24037963 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 3706 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6519 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 19114 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 569 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2889543 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 128346 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1609 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 88045773 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.152898 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.410636 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 31941663 37.50% 37.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 506826 0.60% 38.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23646883 27.76% 65.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 259157 0.30% 66.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 526154 0.62% 66.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 751269 0.88% 67.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 273870 0.32% 67.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 459070 0.54% 68.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 26803191 31.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 34147694 38.78% 38.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 547423 0.62% 39.41% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23764633 26.99% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 284582 0.32% 66.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 557969 0.63% 67.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 795617 0.90% 68.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 319692 0.36% 68.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 484471 0.55% 69.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27143692 30.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 85168083 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.186542 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.920169 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9520844 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 21607924 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 39424228 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1229084 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 928772 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 273051293 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 4 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 928772 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10439907 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13089260 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 3699901 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 39570553 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 4982521 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 272244708 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6270 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2417106 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 1932594 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 1355 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 325535285 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 590374943 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 590374855 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 88 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 317221539 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 8313746 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 122579 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 123510 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 10816950 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 5506267 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2968253 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 324837 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 268098 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 270840712 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 382144 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 269680817 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 48233 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 5882884 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 8996381 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 45929 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 85168083 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.166454 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.381789 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 88045773 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.185698 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.915624 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10285454 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 22943626 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 41627806 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1270133 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1048147 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 276853450 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 7 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1048147 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11254615 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 13961054 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 3963789 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 41762702 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5184927 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 275944284 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 6769 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2459328 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2061675 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 2717 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 329857779 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 599690764 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 599690564 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 200 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320509391 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 9348388 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 136043 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 137064 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11288733 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 5902057 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3230740 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 354441 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 291130 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 274390669 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 398438 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 272978735 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 57079 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 6609909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10125547 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 50893 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 88045773 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.100418 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.393656 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 23491447 27.58% 27.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5639421 6.62% 34.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3592727 4.22% 38.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2433201 2.86% 41.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 24826332 29.15% 70.43% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1184872 1.39% 71.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23718098 27.85% 99.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 237817 0.28% 99.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44168 0.05% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 25312226 28.75% 28.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5904467 6.71% 35.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3803238 4.32% 39.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2580509 2.93% 42.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25019730 28.42% 71.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1259471 1.43% 72.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23861754 27.10% 99.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 255558 0.29% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 48820 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 85168083 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 88045773 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 103037 31.19% 31.19% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 241 0.07% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 181800 55.03% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 45300 13.71% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 115953 32.52% 32.52% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 120 0.03% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 188030 52.73% 85.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 52485 14.72% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 57001 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 260895656 96.74% 96.76% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 47542 0.02% 96.78% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 43696 0.02% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 5855050 2.17% 98.97% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2781872 1.03% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 70354 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263570476 96.55% 96.58% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 51118 0.02% 96.60% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 46597 0.02% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6213747 2.28% 98.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3026443 1.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 269680817 # Type of FU issued -system.cpu2.iq.rate 1.789783 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 330378 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001225 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 624940807 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 277108342 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 268465757 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 40 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 38 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 269954173 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 21 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 584645 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 272978735 # Type of FU issued +system.cpu2.iq.rate 1.775588 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 356588 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001306 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 634455588 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 281402142 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 271688146 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 29 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 273264957 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 12 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 613124 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 814531 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6351 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3024 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 433740 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 928259 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6814 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3642 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 478181 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 655738 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10426 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656152 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10356 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 928772 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 8598252 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 798569 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 271222856 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 58264 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 5506267 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2968253 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 206333 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 621407 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3570 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3024 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 146514 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 137704 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 284218 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 269282728 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 5768116 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 398089 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1048147 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9348181 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 808638 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 274789107 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 65396 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 5902057 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3230758 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 220588 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 626855 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4558 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3642 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 161804 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 161245 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 323049 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 272529284 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6113028 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 449451 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 8495654 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27379135 # Number of branches executed -system.cpu2.iew.exec_stores 2727538 # Number of stores executed -system.cpu2.iew.exec_rate 1.787141 # Inst execution rate -system.cpu2.iew.wb_sent 269160909 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 268465771 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 209852405 # num instructions producing a value -system.cpu2.iew.wb_consumers 343221010 # num instructions consuming a value +system.cpu2.iew.exec_refs 9080043 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27720555 # Number of branches executed +system.cpu2.iew.exec_stores 2967015 # Number of stores executed +system.cpu2.iew.exec_rate 1.772664 # Inst execution rate +system.cpu2.iew.wb_sent 272391201 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 271688152 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212092617 # num instructions producing a value +system.cpu2.iew.wb_consumers 346983399 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.781720 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611421 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.767193 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611247 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 6125563 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 336215 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 254201 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 84239311 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.146959 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.869440 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 6884729 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 347545 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 288057 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 86997626 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.079430 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.871941 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 28027655 33.27% 33.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 3948624 4.69% 37.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1090324 1.29% 39.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24397189 28.96% 68.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 757994 0.90% 69.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 507340 0.60% 69.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 301970 0.36% 70.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23269432 27.62% 97.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1938783 2.30% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 29972174 34.45% 34.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4215922 4.85% 39.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1166731 1.34% 40.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24592469 28.27% 68.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 801811 0.92% 69.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 544306 0.63% 70.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 310409 0.36% 70.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23365384 26.86% 97.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2028420 2.33% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 84239311 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 134086437 # Number of instructions committed -system.cpu2.commit.committedOps 265097623 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 86997626 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135649483 # Number of instructions committed +system.cpu2.commit.committedOps 267903067 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7226249 # Number of memory references committed -system.cpu2.commit.loads 4691736 # Number of loads committed -system.cpu2.commit.membars 162513 # Number of memory barriers committed -system.cpu2.commit.branches 27101249 # Number of branches committed +system.cpu2.commit.refs 7726375 # Number of memory references committed +system.cpu2.commit.loads 4973798 # Number of loads committed +system.cpu2.commit.membars 163952 # Number of memory barriers committed +system.cpu2.commit.branches 27408076 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 241753447 # Number of committed integer instructions. -system.cpu2.commit.function_calls 394614 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1938783 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 244468826 # Number of committed integer instructions. +system.cpu2.commit.function_calls 411685 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2028420 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 353502675 # The number of ROB reads -system.cpu2.rob.rob_writes 543377618 # The number of ROB writes -system.cpu2.timesIdled 448607 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65509822 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4919608430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 134086437 # Number of Instructions Simulated -system.cpu2.committedOps 265097623 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 134086437 # Number of Instructions Simulated -system.cpu2.cpi 1.123737 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.123737 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.889888 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.889888 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 494284042 # number of integer regfile reads -system.cpu2.int_regfile_writes 320739139 # number of integer regfile writes -system.cpu2.fp_regfile_reads 62606 # number of floating regfile reads -system.cpu2.fp_regfile_writes 62592 # number of floating regfile writes -system.cpu2.misc_regfile_reads 86693613 # number of misc regfile reads -system.cpu2.misc_regfile_writes 110320 # number of misc regfile writes +system.cpu2.rob.rob_reads 359731311 # The number of ROB reads +system.cpu2.rob.rob_writes 550627170 # The number of ROB writes +system.cpu2.timesIdled 462650 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65694151 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4912523731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135649483 # Number of Instructions Simulated +system.cpu2.committedOps 267903067 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 135649483 # Number of Instructions Simulated +system.cpu2.cpi 1.133362 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.133362 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.882331 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.882331 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 500765277 # number of integer regfile reads +system.cpu2.int_regfile_writes 324464285 # number of integer regfile writes +system.cpu2.fp_regfile_reads 62550 # number of floating regfile reads +system.cpu2.fp_regfile_writes 62544 # number of floating regfile writes +system.cpu2.misc_regfile_reads 88091146 # number of misc regfile reads +system.cpu2.misc_regfile_writes 122333 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 9627a30de..307f030d7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.026877 # Number of seconds simulated -sim_ticks 26876770500 # Number of ticks simulated -final_tick 26876770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26877484000 # Number of ticks simulated +final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124105 # Simulator instruction rate (inst/s) -host_op_rate 124996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36820237 # Simulator tick rate (ticks/s) -host_mem_usage 379416 # Number of bytes of host memory used -host_seconds 729.95 # Real time elapsed on the host +host_inst_rate 175198 # Simulator instruction rate (inst/s) +host_op_rate 176456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51980195 # Simulator tick rate (ticks/s) +host_mem_usage 379404 # Number of bytes of host memory used +host_seconds 517.07 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 992448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1666867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35258998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36925865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1666867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1666867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1666867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35258998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36925865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15507 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory +system.physmem.bytes_read::total 992384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 702 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15506 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1671585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35250919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36922504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1671585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1671585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15506 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15509 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 992448 # Total number of bytes read from memory +system.physmem.cpureqs 15508 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 992384 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 992448 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1078 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1079 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 934 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26876578500 # Total gap between requests +system.physmem.totGap 26877282500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15507 # Categorize read packet sizes +system.physmem.readPktSize::6 15506 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 11266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 11153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,17 +150,17 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3465.175627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 823.608896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3831.300006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 3465.405018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 823.463699 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3831.282142 # Bytes accessed per row activation system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 21 7.53% 31.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 17 6.09% 37.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 11 3.94% 41.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 11 3.94% 45.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 5 1.79% 47.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1 0.36% 48.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 3 1.08% 49.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 22 7.89% 32.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 15 5.38% 37.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 12 4.30% 41.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 10 3.58% 45.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 6 2.15% 47.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2 0.72% 48.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 2 0.72% 49.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation @@ -178,7 +178,7 @@ system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.36% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.36% 59.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation @@ -186,53 +186,53 @@ system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation -system.physmem.totQLat 33774250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 291406750 # Sum of mem lat for all requests -system.physmem.totBusLat 77535000 # Total cycles spent in databus access -system.physmem.totBankLat 180097500 # Total cycles spent in bank access -system.physmem.avgQLat 2178.00 # Average queueing delay per request -system.physmem.avgBankLat 11613.95 # Average bank access latency per request +system.physmem.totQLat 38456500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 288012750 # Sum of mem lat for all requests +system.physmem.totBusLat 77530000 # Total cycles spent in databus access +system.physmem.totBankLat 172026250 # Total cycles spent in bank access +system.physmem.avgQLat 2480.10 # Average queueing delay per request +system.physmem.avgBankLat 11094.17 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18791.95 # Average memory access latency -system.physmem.avgRdBW 36.93 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 18574.28 # Average memory access latency +system.physmem.avgRdBW 36.92 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 36.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 36.92 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15228 # Number of row buffer hits during reads +system.physmem.readRowHits 15227 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1733190.08 # Average gap between requests -system.membus.throughput 36925865 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 969 # Transaction distribution -system.membus.trans_dist::ReadResp 969 # Transaction distribution +system.physmem.avgGap 1733347.25 # Average gap between requests +system.membus.throughput 36922504 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 968 # Transaction distribution +system.membus.trans_dist::ReadResp 968 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 31018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 31018 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 992448 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992448 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 31016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 31016 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992384 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 992384 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992384 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19245500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145771998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145109998 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.branchPred.lookups 26679971 # Number of BP lookups -system.cpu.branchPred.condPredicted 21999923 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 841486 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11361779 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11280277 # Number of BTB hits +system.cpu.branchPred.lookups 26677800 # Number of BP lookups +system.cpu.branchPred.condPredicted 21997882 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 841974 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11370900 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11281126 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.282665 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69760 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 186 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.210493 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69875 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 190 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -276,239 +276,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53753542 # number of cpu cycles simulated +system.cpu.numCycles 53754969 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14168054 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127857393 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26679971 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11350037 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24029267 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4759146 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11320906 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14167360 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127859416 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26677800 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11351001 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24030535 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4760658 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11306613 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13839868 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53419540 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.409911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214764 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13839893 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329843 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53406892 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.410540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214942 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29428601 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3388763 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2027589 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1554197 2.91% 68.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1665441 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2919869 5.47% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1510771 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090381 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9833928 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29414657 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389704 6.35% 61.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028213 3.80% 65.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1552667 2.91% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1667858 3.12% 71.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2917621 5.46% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1511775 2.83% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090045 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9834352 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53419540 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.496339 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.378585 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16932063 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9167037 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22428085 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 999775 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3892580 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442872 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8651 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126035469 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42652 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3892580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18713289 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3601391 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 176810 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21544043 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5491427 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123129214 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 413620 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4613636 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1365 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143579054 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536328979 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536324233 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4746 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53406892 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.496285 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.378560 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16930336 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9153085 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22398033 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1031812 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3893626 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4442083 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8660 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126043342 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3893626 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18711323 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3589161 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 177598 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21546569 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5488615 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123125799 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 427703 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4597767 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1304 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143579240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536319966 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536314240 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5726 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36164868 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4608 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4606 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12537284 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29472276 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5518407 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2148723 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1268677 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118148285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105144607 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78560 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26719178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65548353 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53419540 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968280 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.909780 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36165054 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4615 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4613 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12549588 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29468785 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5519570 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2135216 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1252898 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118144684 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8486 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105149299 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79112 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26716988 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65524839 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 268 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53406892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.968834 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.909318 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15372134 28.78% 28.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11649287 21.81% 50.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8266991 15.48% 66.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6802353 12.73% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4948394 9.26% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2939644 5.50% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2464571 4.61% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 534271 1.00% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 441895 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15356551 28.75% 28.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11649216 21.81% 50.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8254544 15.46% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6822524 12.77% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4944372 9.26% 88.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2950581 5.52% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2452903 4.59% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 533996 1.00% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442205 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53419540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53406892 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45832 6.94% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 339714 51.41% 58.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 275235 41.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45764 6.91% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 341696 51.58% 58.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 274978 41.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74415665 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 126 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 171 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25604813 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5112854 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74418524 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 156 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 210 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25604703 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5114728 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105144607 # Type of FU issued -system.cpu.iq.rate 1.956050 # Inst issue rate -system.cpu.iq.fu_busy_cnt 660808 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006285 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264447444 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144880593 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102675373 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 678 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 959 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105805083 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 332 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 440146 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105149299 # Type of FU issued +system.cpu.iq.rate 1.956085 # Inst issue rate +system.cpu.iq.fu_busy_cnt 662465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264446249 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144874513 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102679810 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 818 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1193 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 350 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105811363 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 401 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 442313 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6898310 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6801 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6412 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 773563 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6894819 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6564 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6306 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 774726 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31426 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31505 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3892580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 959936 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127408 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118169460 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 310371 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29472276 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5518407 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66175 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6842 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6412 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 445895 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445553 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 891448 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104166950 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25284184 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 977657 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3893626 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 957081 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126869 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118165864 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309166 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29468785 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5519570 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4598 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6306 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446848 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 444951 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 891799 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104175749 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25286286 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 973550 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12698 # number of nop insts executed -system.cpu.iew.exec_refs 30340262 # number of memory reference insts executed -system.cpu.iew.exec_branches 21325081 # Number of branches executed -system.cpu.iew.exec_stores 5056078 # Number of stores executed -system.cpu.iew.exec_rate 1.937862 # Inst execution rate -system.cpu.iew.wb_sent 102951696 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102675661 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62239721 # num instructions producing a value -system.cpu.iew.wb_consumers 104280591 # num instructions consuming a value +system.cpu.iew.exec_nop 12694 # number of nop insts executed +system.cpu.iew.exec_refs 30344072 # number of memory reference insts executed +system.cpu.iew.exec_branches 21323909 # Number of branches executed +system.cpu.iew.exec_stores 5057786 # Number of stores executed +system.cpu.iew.exec_rate 1.937974 # Inst execution rate +system.cpu.iew.wb_sent 102957516 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102680160 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62240823 # num instructions producing a value +system.cpu.iew.wb_consumers 104288348 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.910119 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596849 # average fanout of values written-back +system.cpu.iew.wb_rate 1.910152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596815 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26919455 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26915742 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 832928 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49526960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842491 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540649 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 833391 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49513266 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.843000 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540951 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20031869 40.45% 40.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13152738 26.56% 67.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4167621 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3431174 6.93% 82.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1533592 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 731516 1.48% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 947722 1.91% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 252646 0.51% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5278082 10.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20021121 40.44% 40.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13151741 26.56% 67.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4165163 8.41% 75.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3429722 6.93% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1536672 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 726445 1.47% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 951437 1.92% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253528 0.51% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5277437 10.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49526960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49513266 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -519,97 +519,97 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5278082 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5277437 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162415559 # The number of ROB reads -system.cpu.rob.rob_writes 240257118 # The number of ROB writes -system.cpu.timesIdled 46037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 334002 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162398797 # The number of ROB reads +system.cpu.rob.rob_writes 240250691 # The number of ROB writes +system.cpu.timesIdled 46136 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 348077 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.593373 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.593373 # CPI: Total CPI of All Threads -system.cpu.ipc 1.685281 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.685281 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495496517 # number of integer regfile reads -system.cpu.int_regfile_writes 120533542 # number of integer regfile writes -system.cpu.fp_regfile_reads 149 # number of floating regfile reads -system.cpu.fp_regfile_writes 362 # number of floating regfile writes -system.cpu.misc_regfile_reads 29086571 # number of misc regfile reads +system.cpu.cpi 0.593389 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.593389 # CPI: Total CPI of All Threads +system.cpu.ipc 1.685236 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.685236 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495533268 # number of integer regfile reads +system.cpu.int_regfile_writes 120542090 # number of integer regfile writes +system.cpu.fp_regfile_reads 173 # number of floating regfile reads +system.cpu.fp_regfile_writes 448 # number of floating regfile writes +system.cpu.misc_regfile_reads 29087390 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4503595847 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942920 # Transaction distribution +system.cpu.toL2Bus.throughput 4503454862 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942919 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43775 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1457 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 2839649 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120995392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 121041920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121041920 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1454 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838179 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 2839633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120994944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 121041344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888563000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1095499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1225499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1421456489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 627.794494 # Cycle average of tags in use -system.cpu.icache.total_refs 13838883 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 727 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19035.602476 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 627.794494 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306540 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13838883 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13838883 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13838883 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13838883 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13838883 # number of overall hits -system.cpu.icache.overall_hits::total 13838883 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses -system.cpu.icache.overall_misses::total 984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66043999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66043999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66043999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66043999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66043999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66043999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13839867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13839867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13839867 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13839867 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13839867 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13839867 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13838909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13838909 # number of overall hits +system.cpu.icache.overall_hits::total 13838909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses +system.cpu.icache.overall_misses::total 983 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64555998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64555998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64555998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64555998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64555998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64555998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13839892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13839892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13839892 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13839892 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13839892 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13839892 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67117.885163 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67117.885163 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67117.885163 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67117.885163 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65672.429298 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65672.429298 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65672.429298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65672.429298 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 629 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.300000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.900000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -619,122 +619,122 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 254 system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 730 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 730 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 730 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 730 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 730 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 730 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49961500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49961500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49961500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49961500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49961500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49961500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 729 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 729 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 729 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 729 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 729 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 729 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49190750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49190750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49190750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49190750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49190750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49190750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68440.410959 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68440.410959 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68440.410959 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68440.410959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68440.410959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68440.410959 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67477.023320 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67477.023320 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10730.679646 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1831381 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15490 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.229890 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 9888.279908 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 613.185142 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 229.214596 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.301766 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.006995 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.327474 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903579 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903605 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942920 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942920 # number of Writeback hits +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # 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number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932816 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932842 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932816 # number of overall hits -system.cpu.l2cache.overall_hits::total 932842 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 701 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 980 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 29198 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 29198 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932813 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932836 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932813 # number of overall hits +system.cpu.l2cache.overall_hits::total 932836 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 703 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 276 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 979 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15518 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses -system.cpu.l2cache.overall_misses::total 15518 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48961500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19173000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 68134500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 895149000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 895149000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 48961500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 914322000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 963283500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 48961500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 914322000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 963283500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 727 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 903858 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904585 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942920 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942920 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 703 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15517 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 703 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 727 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947633 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948360 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 727 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947633 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948360 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964237 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001083 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43736 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43736 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 726 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947627 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948353 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 726 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947627 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948353 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968320 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000305 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001082 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.666667 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.666667 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332107 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.332107 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964237 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016363 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964237 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016363 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69845.221113 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68720.430108 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69525 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015633 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016362 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968320 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015633 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016362 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.086771 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70012.681159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69007.660878 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61715.418214 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61715.418214 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68613.086771 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61870.004725 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 62175.501063 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68613.086771 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61870.004725 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 62175.501063 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -752,184 +752,184 @@ system.cpu.l2cache.demand_mshr_hits::total 11 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15507 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15507 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40240750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15233500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55474250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 702 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15506 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 702 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15506 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39349250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15357000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54706250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 714861250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 714861250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40240750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730094750 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730171750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 769521000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39349250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 730171750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 769521000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001070 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016351 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016351 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57486.785714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56630.111524 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57733.082707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56514.721074 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49171.911542 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49171.911542 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49168.713028 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49168.713028 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943537 # number of replacements -system.cpu.dcache.tagsinuse 3672.136580 # Cycle average of tags in use -system.cpu.dcache.total_refs 28138091 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947633 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.693026 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7986158000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3672.136580 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.896518 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.896518 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23597541 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23597541 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532751 # 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number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173737 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202230 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202230 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1375967 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1375967 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1375967 # number of overall misses -system.cpu.dcache.overall_misses::total 1375967 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887682000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13887682000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7842358356 # 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number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28130035 # number of overall hits +system.cpu.dcache.overall_hits::total 28130035 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173788 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173788 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202076 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202076 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1375864 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1375864 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1375864 # number of overall misses +system.cpu.dcache.overall_misses::total 1375864 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887695479 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13887695479 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7918602355 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7918602355 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 251250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21806297834 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21806297834 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21806297834 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21806297834 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24770918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24770918 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3913 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3913 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3923 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29506259 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29506259 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29506259 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29506259 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047383 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047383 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042710 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042710 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11832.021995 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11832.021995 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38779.401454 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38779.401454 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33714.285714 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33714.285714 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15792.559237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15792.559237 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 153985 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29505899 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29505899 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29505899 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29505899 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047386 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047386 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042677 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042677 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046630 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046630 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046630 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046630 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.519388 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.519388 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39186.258413 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39186.258413 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31406.250000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31406.250000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15849.166657 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15849.166657 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154131 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23865 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23950 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.452336 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.435532 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942920 # number of writebacks -system.cpu.dcache.writebacks::total 942920 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269859 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269859 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158472 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158472 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428331 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428331 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428331 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428331 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903878 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903878 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43758 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43758 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947636 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947636 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947636 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947636 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9991782011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9991782011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1252450464 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1252450464 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11244232475 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11244232475 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11244232475 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11244232475 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036489 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009241 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.348055 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.348055 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28622.205402 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28622.205402 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942919 # number of writebacks +system.cpu.dcache.writebacks::total 942919 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269877 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269877 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158357 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158357 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 428234 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428234 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428234 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428234 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903911 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903911 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43719 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43719 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947630 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947630 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947630 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9992457010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9992457010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254142688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254142688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11246599698 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11246599698 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11246599698 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11246599698 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036491 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036491 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009233 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009233 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.691236 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.691236 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28686.444978 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28686.444978 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index bffef2d47..5c365748d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 294271952 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 510.071144 # Cycle average of tags in use -system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 119.244078 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.291909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 942702 # number of replacements -system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use -system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 942702 # number of replacements +system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b41c1d4fe..2c81bb996 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 722977060 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 725.412977 # Cycle average of tags in use -system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 25 # number of replacements +system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 116.340947 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.296955 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits @@ -279,15 +279,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 935475 # number of replacements -system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use -system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 935475 # number of replacements +system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index a8ad328fe..eb92ec68e 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065490 # Number of seconds simulated -sim_ticks 65489948000 # Number of ticks simulated -final_tick 65489948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065502 # Number of seconds simulated +sim_ticks 65501881000 # Number of ticks simulated +final_tick 65501881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99083 # Simulator instruction rate (inst/s) -host_op_rate 174470 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41072394 # Simulator tick rate (ticks/s) -host_mem_usage 386708 # Number of bytes of host memory used -host_seconds 1594.50 # Real time elapsed on the host +host_inst_rate 72627 # Simulator instruction rate (inst/s) +host_op_rate 127885 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30111215 # Simulator tick rate (ticks/s) +host_mem_usage 386704 # Number of bytes of host memory used +host_seconds 2175.33 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882624 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10112 # Number of bytes written to this memory -system.physmem.bytes_written::total 10112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29416 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 158 # Number of write requests responded to by this memory -system.physmem.num_writes::total 158 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 975295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28746763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29722057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 154405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 154405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 154405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28746763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29876463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30415 # Total number of read requests seen -system.physmem.writeReqs 158 # Total number of write requests seen +system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882496 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10432 # Number of bytes written to this memory +system.physmem.bytes_written::total 10432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29414 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30408 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 971209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28739572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29710780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 971209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 971209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 159263 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 159263 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 159263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 971209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28739572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29870043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30410 # Total number of read requests seen +system.physmem.writeReqs 163 # Total number of write requests seen system.physmem.cpureqs 30573 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1946496 # Total number of bytes read from memory -system.physmem.bytesWritten 10112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 10112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 47 # Number of read reqs serviced by write Q +system.physmem.bytesRead 1946112 # Total number of bytes read from memory +system.physmem.bytesWritten 10432 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1946112 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1921 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1927 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1901 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 2030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1898 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1939 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1934 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1796 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1821 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1818 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 13 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 13 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis @@ -77,26 +77,26 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 65489931000 # Total gap between requests +system.physmem.totGap 65501859000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30415 # Categorize read packet sizes +system.physmem.readPktSize::6 30410 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 158 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 163 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,8 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see @@ -144,9 +144,9 @@ system.physmem.wrQLenPdf::16 7 # Wh system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -156,231 +156,231 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 551 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3522.090744 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 829.782913 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3844.695710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 143 25.95% 25.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 46 8.35% 34.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 23 4.17% 38.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 15 2.72% 41.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 11 2.00% 43.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10 1.81% 45.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 9 1.63% 46.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 5 0.91% 47.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.91% 48.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 10 1.81% 50.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.73% 51.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 1.09% 52.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 2 0.36% 52.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1 0.18% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.54% 53.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1 0.18% 53.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.18% 55.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.54% 56.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.36% 56.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.18% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.18% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.36% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.18% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.18% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.18% 58.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.18% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.36% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.18% 59.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.18% 59.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.18% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 216 39.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 551 # Bytes accessed per row activation -system.physmem.totQLat 7172750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 582609000 # Sum of mem lat for all requests -system.physmem.totBusLat 151840000 # Total cycles spent in databus access -system.physmem.totBankLat 423596250 # Total cycles spent in bank access -system.physmem.avgQLat 236.19 # Average queueing delay per request -system.physmem.avgBankLat 13948.77 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 552 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 3503.884058 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 832.064707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3839.690246 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 138 25.00% 25.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 47 8.51% 33.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 28 5.07% 38.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 12 2.17% 40.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 14 2.54% 43.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 11 1.99% 45.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 8 1.45% 46.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 4 0.72% 47.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.63% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 7 1.27% 50.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.72% 51.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 7 1.27% 52.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 2 0.36% 52.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 2 0.36% 53.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.54% 53.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.18% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.18% 56.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.36% 56.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.18% 56.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.18% 57.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.36% 57.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.36% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.18% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.18% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.18% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.18% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.18% 59.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.18% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.36% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.18% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 215 38.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 552 # Bytes accessed per row activation +system.physmem.totQLat 7596000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 583088500 # Sum of mem lat for all requests +system.physmem.totBusLat 151800000 # Total cycles spent in databus access +system.physmem.totBankLat 423692500 # Total cycles spent in bank access +system.physmem.avgQLat 250.20 # Average queueing delay per request +system.physmem.avgBankLat 13955.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19184.96 # Average memory access latency -system.physmem.avgRdBW 29.72 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.72 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 19205.81 # Average memory access latency +system.physmem.avgRdBW 29.71 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.71 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 0.64 # Average write queue length over time -system.physmem.readRowHits 29867 # Number of row buffer hits during reads -system.physmem.writeRowHits 88 # Number of row buffer hits during writes -system.physmem.readRowHitRate 98.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.70 # Row buffer hit rate for writes -system.physmem.avgGap 2142083.90 # Average gap between requests -system.membus.throughput 29875486 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1414 # Transaction distribution -system.membus.trans_dist::ReadResp 1412 # Transaction distribution -system.membus.trans_dist::Writeback 158 # Transaction distribution -system.membus.trans_dist::ReadExReq 29001 # Transaction distribution -system.membus.trans_dist::ReadExResp 29001 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 60986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60986 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1956544 # Total data (bytes) +system.physmem.avgWrQLen 12.43 # Average write queue length over time +system.physmem.readRowHits 29868 # Number of row buffer hits during reads +system.physmem.writeRowHits 101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 98.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.96 # Row buffer hit rate for writes +system.physmem.avgGap 2142474.05 # Average gap between requests +system.membus.throughput 29869066 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1406 # Transaction distribution +system.membus.trans_dist::ReadResp 1403 # Transaction distribution +system.membus.trans_dist::Writeback 163 # Transaction distribution +system.membus.trans_dist::ReadExReq 29004 # Transaction distribution +system.membus.trans_dist::ReadExResp 29004 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 60980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60980 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1956480 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 34719000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 35091000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 283984750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284259500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.branchPred.lookups 33857873 # Number of BP lookups -system.cpu.branchPred.condPredicted 33857873 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 774323 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19304335 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19204317 # Number of BTB hits +system.cpu.branchPred.lookups 33859772 # Number of BP lookups +system.cpu.branchPred.condPredicted 33859772 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 774888 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19298286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19204033 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.481888 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5017100 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5401 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.511599 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5017180 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5379 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 130979906 # number of cpu cycles simulated +system.cpu.numCycles 131003766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26132901 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182254705 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33857873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24221417 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55457387 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5351238 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44744671 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 26135908 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182273755 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33859772 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24221213 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55461769 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5355546 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44756866 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 388 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25573947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 166608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 130876974 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.455077 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.315032 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 25575264 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 165870 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 130900361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.454854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314999 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77895599 59.52% 59.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1961064 1.50% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2941506 2.25% 63.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3833280 2.93% 66.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7768261 5.94% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757709 3.64% 75.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2666396 2.04% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1316117 1.01% 78.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27737042 21.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77915453 59.52% 59.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1959993 1.50% 61.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2942167 2.25% 63.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3834775 2.93% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7768215 5.93% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757692 3.63% 75.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2664580 2.04% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1316041 1.01% 78.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27741445 21.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 130876974 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258497 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.391471 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36825046 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36962033 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43884335 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8664000 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4541560 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318828995 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4541560 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42312169 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9511401 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7346 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46756594 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27747904 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 314994654 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26642 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25895040 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 476 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 317170346 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836475154 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 836474392 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 762 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 130900361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258464 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.391363 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36822089 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36980976 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43893831 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8658090 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4545375 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318858939 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4545375 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42309692 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9552635 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7405 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46756316 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27728938 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 315018359 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 180 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26669 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25876041 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 477 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 317189446 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836531493 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 836530400 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1093 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37957599 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 473 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 471 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62618763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101546098 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34776490 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39628981 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5872628 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311460641 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1620 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300263242 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 89194 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32692736 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46075932 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1175 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 130876974 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.294240 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.698248 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37976699 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 479 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 477 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62612991 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101555768 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34778786 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39638216 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5865755 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311479938 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1623 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300277679 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 89964 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32707513 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46093052 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1178 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 130900361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.293941 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.699121 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24131864 18.44% 18.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23200747 17.73% 36.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25515846 19.50% 55.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25800196 19.71% 75.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18908821 14.45% 89.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8226578 6.29% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3966533 3.03% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 948269 0.72% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 178120 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24175636 18.47% 18.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23209060 17.73% 36.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25458730 19.45% 55.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25817772 19.72% 75.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18910783 14.45% 89.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8235477 6.29% 96.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3954804 3.02% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 956290 0.73% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181809 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 130876974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 130900361 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31350 1.52% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1914118 93.02% 94.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 112203 5.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31412 1.53% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1912178 93.02% 94.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 111979 5.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31269 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169831463 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11173 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169839925 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11359 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 330 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued @@ -406,84 +406,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97296683 32.40% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33092294 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97303672 32.40% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33091082 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300263242 # Type of FU issued -system.cpu.iq.rate 2.292437 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2057671 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006853 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733550061 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344187115 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298012847 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 328 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302289511 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54160833 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300277679 # Type of FU issued +system.cpu.iq.rate 2.292130 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2055569 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006846 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733600907 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344221068 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298025850 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 456 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302301800 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54184658 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10766713 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30678 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33261 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3336738 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10776383 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 30894 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33570 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3339034 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3210 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8599 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3237 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8568 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4541560 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2575832 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 162156 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311462261 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 197211 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101546098 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34776490 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 463 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2580 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73528 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33261 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393064 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 427262 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 820326 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298861022 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96886540 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1402220 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4545375 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2618322 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 161863 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311481561 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 197279 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101555768 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34778786 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73457 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33570 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393653 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 427979 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 821632 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298876380 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96891177 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1401299 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129814002 # number of memory reference insts executed -system.cpu.iew.exec_branches 30818579 # Number of branches executed -system.cpu.iew.exec_stores 32927462 # Number of stores executed -system.cpu.iew.exec_rate 2.281732 # Inst execution rate -system.cpu.iew.wb_sent 298381528 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298012951 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218258094 # num instructions producing a value -system.cpu.iew.wb_consumers 296763752 # num instructions consuming a value +system.cpu.iew.exec_refs 129818452 # number of memory reference insts executed +system.cpu.iew.exec_branches 30820594 # Number of branches executed +system.cpu.iew.exec_stores 32927275 # Number of stores executed +system.cpu.iew.exec_rate 2.281433 # Inst execution rate +system.cpu.iew.wb_sent 298395371 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298025973 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218267458 # num instructions producing a value +system.cpu.iew.wb_consumers 296778027 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.275257 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735461 # average fanout of values written-back +system.cpu.iew.wb_rate 2.274942 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735457 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33282582 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33301924 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 774373 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126335414 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.202015 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.972310 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 774937 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126354986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.201674 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.972574 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58023185 45.93% 45.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19157211 15.16% 61.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11690918 9.25% 70.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9453779 7.48% 77.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1822705 1.44% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2075367 1.64% 80.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1288633 1.02% 81.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 696301 0.55% 82.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22127315 17.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58072502 45.96% 45.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19158205 15.16% 61.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11637077 9.21% 70.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9445238 7.48% 77.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1852713 1.47% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2072442 1.64% 80.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1294957 1.02% 81.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 693229 0.55% 82.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22128623 17.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126335414 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126354986 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -494,212 +494,212 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22127315 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22128623 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415683145 # The number of ROB reads -system.cpu.rob.rob_writes 627495486 # The number of ROB writes -system.cpu.timesIdled 13953 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 102932 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415720751 # The number of ROB reads +system.cpu.rob.rob_writes 627537958 # The number of ROB writes +system.cpu.timesIdled 13918 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 103405 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.829047 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.829047 # CPI: Total CPI of All Threads -system.cpu.ipc 1.206204 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.206204 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 590786274 # number of integer regfile reads -system.cpu.int_regfile_writes 298589380 # number of integer regfile writes -system.cpu.fp_regfile_reads 94 # number of floating regfile reads -system.cpu.fp_regfile_writes 64 # number of floating regfile writes -system.cpu.misc_regfile_reads 191820132 # number of misc regfile reads +system.cpu.cpi 0.829198 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.829198 # CPI: Total CPI of All Threads +system.cpu.ipc 1.205985 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.205985 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 590807496 # number of integer regfile reads +system.cpu.int_regfile_writes 298603166 # number of integer regfile writes +system.cpu.fp_regfile_reads 109 # number of floating regfile reads +system.cpu.fp_regfile_writes 74 # number of floating regfile writes +system.cpu.misc_regfile_reads 191829835 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4049838977 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995271 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995269 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066544 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82308 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82308 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2026 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 6221700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265158912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 265223744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265223744 # Total data (bytes) +system.cpu.toL2Bus.throughput 4049183259 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82305 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 6221783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265164480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 265229120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265229120 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4138605500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4138734000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1519500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1707500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3114846499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3122065000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.replacements 52 # number of replacements -system.cpu.icache.tagsinuse 824.208577 # Cycle average of tags in use -system.cpu.icache.total_refs 25572646 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1013 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25244.467917 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 824.208577 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.402446 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.402446 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25572646 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25572646 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25572646 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25572646 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25572646 # number of overall hits -system.cpu.icache.overall_hits::total 25572646 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1301 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1301 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1301 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1301 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1301 # number of overall misses -system.cpu.icache.overall_misses::total 1301 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 86424000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 86424000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 86424000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 86424000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 86424000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 86424000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25573947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25573947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25573947 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25573947 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25573947 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25573947 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 57 # number of replacements +system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25573967 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25573967 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25573967 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25573967 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25573967 # number of overall hits +system.cpu.icache.overall_hits::total 25573967 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1297 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1297 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1297 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1297 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1297 # number of overall misses +system.cpu.icache.overall_misses::total 1297 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 86393250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 86393250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 86393250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 86393250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 86393250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 86393250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25575264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25575264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25575264 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25575264 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25575264 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25575264 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66428.900846 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66428.900846 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66428.900846 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66428.900846 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66428.900846 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66428.900846 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66610.061681 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66610.061681 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66610.061681 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66610.061681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66610.061681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66610.061681 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 288 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 288 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 288 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 288 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 288 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1013 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1013 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1013 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68779000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68779000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68779000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68779000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68779000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68779000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67896.347483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67896.347483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67896.347483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67896.347483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67896.347483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67896.347483 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 287 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 287 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 287 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 287 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 287 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1010 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1010 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1010 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68485500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 68485500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68485500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 68485500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68485500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 68485500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67807.425743 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67807.425743 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 473 # number of replacements -system.cpu.l2cache.tagsinuse 20826.388210 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4029249 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30396 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.558527 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19907.583487 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 670.159667 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 248.645055 # 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average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014637 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55141.851107 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56828.883495 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55636.201991 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48889.170459 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48889.170459 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55141.851107 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49000.373946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49201.118053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55141.851107 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49000.373946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49201.118053 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072468 # number of replacements -system.cpu.dcache.tagsinuse 4069.997432 # Cycle average of tags in use -system.cpu.dcache.total_refs 71397556 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076564 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.382545 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 20655836000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4069.997432 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.993652 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.993652 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40055849 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40055849 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71397556 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71397556 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71397556 # number of overall hits -system.cpu.dcache.overall_hits::total 71397556 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2625767 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2625767 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98045 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98045 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2723812 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2723812 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2723812 # number of overall misses -system.cpu.dcache.overall_misses::total 2723812 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31384094500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31384094500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2663792498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2663792498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34047886998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34047886998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34047886998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34047886998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42681616 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42681616 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 2072469 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.884717 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71377775 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076565 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.373003 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20648680250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.884717 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40036076 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40036076 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341699 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341699 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71377775 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71377775 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71377775 # number of overall hits +system.cpu.dcache.overall_hits::total 71377775 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2626397 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2626397 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98053 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98053 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2724450 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2724450 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2724450 # number of overall misses +system.cpu.dcache.overall_misses::total 2724450 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31390082250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31390082250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2686066747 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2686066747 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34076148997 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34076148997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34076148997 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34076148997 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42662473 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42662473 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74121368 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74121368 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74121368 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74121368 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061520 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061520 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74102225 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74102225 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74102225 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74102225 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061562 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061562 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036748 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036748 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036748 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036748 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11952.353160 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11952.353160 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.080504 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.080504 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12500.087010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12500.087010 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32905 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036766 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036766 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036766 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11951.765955 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11951.765955 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27394.029219 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27394.029219 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12507.533262 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12507.533262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12507.533262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12507.533262 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32680 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9507 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9460 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.461134 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.454545 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066544 # number of writebacks -system.cpu.dcache.writebacks::total 2066544 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631390 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631390 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15856 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647246 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647246 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647246 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647246 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994377 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994377 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82189 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82189 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076566 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076566 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994900501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994900501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2389827998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2389827998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24384728499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24384728499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24384728499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24384728499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046727 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046727 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066630 # number of writebacks +system.cpu.dcache.writebacks::total 2066630 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632021 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 632021 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15861 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15861 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647882 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647882 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647882 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647882 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994376 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994376 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82192 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82192 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076568 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076568 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076568 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076568 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397806497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397806497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392651497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24392651497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392651497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24392651497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046748 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046748 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.456757 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.456757 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29077.224422 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29077.224422 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028023 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028023 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028023 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028023 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.434458 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.434458 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29173.234585 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29173.234585 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.618217 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.618217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.618217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.618217 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index c0ade68d4..d47d4ffea 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 731978130 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.632508 # Cycle average of tags in use -system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 24 # number of replacements +system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits @@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 318 # number of replacements -system.cpu.l2cache.tagsinuse 20041.899765 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.611630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 318 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits @@ -293,15 +293,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.488619 # Cycle average of tags in use -system.cpu.dcache.total_refs 120152370 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2062733 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c258cba07..d43c28cd4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202255 # Number of seconds simulated -sim_ticks 202254809500 # Number of ticks simulated -final_tick 202254809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202350 # Number of seconds simulated +sim_ticks 202349747500 # Number of ticks simulated +final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148306 # Simulator instruction rate (inst/s) -host_op_rate 167206 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59369383 # Simulator tick rate (ticks/s) -host_mem_usage 288744 # Number of bytes of host memory used -host_seconds 3406.72 # Real time elapsed on the host +host_inst_rate 166059 # Simulator instruction rate (inst/s) +host_op_rate 187221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66507382 # Simulator tick rate (ticks/s) +host_mem_usage 250660 # Number of bytes of host memory used +host_seconds 3042.52 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9266496 # Number of bytes read from this memory -system.physmem.bytes_read::total 9482560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6247616 # Number of bytes written to this memory -system.physmem.bytes_written::total 6247616 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144789 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148165 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97619 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97619 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1068276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45815949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46884225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1068276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1068276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30889827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30889827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30889827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1068276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45815949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77774052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148166 # Total number of read requests seen -system.physmem.writeReqs 97619 # Total number of write requests seen -system.physmem.cpureqs 245800 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9482560 # Total number of bytes read from memory -system.physmem.bytesWritten 6247616 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9482560 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6247616 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 82 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 10 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9223 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9810 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9620 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8798 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9719 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9635 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9444 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6145 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9268224 # Number of bytes read from this memory +system.physmem.bytes_read::total 9485120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6250688 # Number of bytes written to this memory +system.physmem.bytes_written::total 6250688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144816 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148205 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97667 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97667 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1071887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45802993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46874879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1071887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1071887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30890515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30890515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30890515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1071887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45802993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77765395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148206 # Total number of read requests seen +system.physmem.writeReqs 97667 # Total number of write requests seen +system.physmem.cpureqs 245886 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9485120 # Total number of bytes read from memory +system.physmem.bytesWritten 6250688 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9485120 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6250688 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9580 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9117 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8328 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8806 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9634 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 8963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9453 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6146 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 6093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5883 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6272 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6268 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5542 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5814 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5893 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5986 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6510 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6050 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5891 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6270 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6047 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5559 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5812 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5895 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6360 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6066 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6146 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry -system.physmem.totGap 202254789500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry +system.physmem.totGap 202349728000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148166 # Categorize read packet sizes +system.physmem.readPktSize::6 148206 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97619 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 138581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97667 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 138524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,31 +124,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see @@ -156,167 +156,166 @@ system.physmem.wrQLenPdf::28 7 # Wh system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 56237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 279.600690 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.370876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 689.275557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 28174 50.10% 50.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 10389 18.47% 68.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4755 8.46% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2751 4.89% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1840 3.27% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1148 2.04% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 864 1.54% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 636 1.13% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 440 0.78% 90.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 367 0.65% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 311 0.55% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 257 0.46% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 204 0.36% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 168 0.30% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 168 0.30% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 154 0.27% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 160 0.28% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 140 0.25% 94.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 187 0.33% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 266 0.47% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 973 1.73% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 245 0.44% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 154 0.27% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 175 0.31% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 98 0.17% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 108 0.19% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 69 0.12% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 37 0.07% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 38 0.07% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 29 0.05% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 23 0.04% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 13 0.02% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 16 0.03% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 14 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 7 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 15 0.03% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 12 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 9 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 15 0.03% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 6 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 12 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 5 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 6 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 8 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 3 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 4 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 4 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 8 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 3 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 56168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.051275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.674597 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 689.024149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 28075 49.98% 49.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 10399 18.51% 68.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4642 8.26% 76.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2823 5.03% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1837 3.27% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1236 2.20% 87.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 832 1.48% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 663 1.18% 89.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 489 0.87% 90.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 349 0.62% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 274 0.49% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 236 0.42% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 206 0.37% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 181 0.32% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 152 0.27% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 162 0.29% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 167 0.30% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 157 0.28% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 185 0.33% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 244 0.43% 95.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 965 1.72% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 247 0.44% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 159 0.28% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 168 0.30% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 90 0.16% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 119 0.21% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 59 0.11% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 42 0.07% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 39 0.07% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 20 0.04% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 31 0.06% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.03% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 11 0.02% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 21 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 16 0.03% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 11 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 15 0.03% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 11 0.02% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 8 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 7 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 8 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 7 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 7 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 6 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 4 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 8 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 8 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 4 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 257 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 56237 # Bytes accessed per row activation -system.physmem.totQLat 1508178750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4631350000 # Sum of mem lat for all requests -system.physmem.totBusLat 740420000 # Total cycles spent in databus access -system.physmem.totBankLat 2382751250 # Total cycles spent in bank access -system.physmem.avgQLat 10184.62 # Average queueing delay per request -system.physmem.avgBankLat 16090.54 # Average bank access latency per request +system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 56168 # Bytes accessed per row activation +system.physmem.totQLat 1531991500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4652987750 # Sum of mem lat for all requests +system.physmem.totBusLat 740665000 # Total cycles spent in databus access +system.physmem.totBankLat 2380331250 # Total cycles spent in bank access +system.physmem.avgQLat 10342.00 # Average queueing delay per request +system.physmem.avgBankLat 16068.88 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31275.15 # Average memory access latency -system.physmem.avgRdBW 46.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 31410.88 # Average memory access latency +system.physmem.avgRdBW 46.87 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 30.89 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 46.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 46.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 30.89 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.03 # Average write queue length over time -system.physmem.readRowHits 130565 # Number of row buffer hits during reads -system.physmem.writeRowHits 58894 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.33 # Row buffer hit rate for writes -system.physmem.avgGap 822893.14 # Average gap between requests -system.membus.throughput 77774052 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46889 # Transaction distribution -system.membus.trans_dist::ReadResp 46888 # Transaction distribution -system.membus.trans_dist::Writeback 97619 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 101277 # Transaction distribution -system.membus.trans_dist::ReadExResp 101277 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 393970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 393970 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15730176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 15730176 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15730176 # Total data (bytes) +system.physmem.avgWrQLen 8.35 # Average write queue length over time +system.physmem.readRowHits 130665 # Number of row buffer hits during reads +system.physmem.writeRowHits 58958 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.37 # Row buffer hit rate for writes +system.physmem.avgGap 822984.74 # Average gap between requests +system.membus.throughput 77765395 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46900 # Transaction distribution +system.membus.trans_dist::ReadResp 46899 # Transaction distribution +system.membus.trans_dist::Writeback 97667 # Transaction distribution +system.membus.trans_dist::UpgradeReq 7 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 101306 # Transaction distribution +system.membus.trans_dist::ReadExResp 101306 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 394092 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 394092 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15735808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 15735808 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15735808 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1080021750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1084180500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1400430490 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1402154244 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 182798066 # Number of BP lookups -system.cpu.branchPred.condPredicted 143118312 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265128 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93487974 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87210419 # Number of BTB hits +system.cpu.branchPred.lookups 182791904 # Number of BP lookups +system.cpu.branchPred.condPredicted 143107699 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265665 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 92799489 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87211157 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.285174 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12673306 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 115887 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.978057 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12678036 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116300 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -360,136 +359,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 404509620 # number of cpu cycles simulated +system.cpu.numCycles 404699496 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119370691 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761605740 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182798066 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99883725 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170135363 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35678308 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77091190 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 441 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 119376230 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761574875 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182791904 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99889193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170142836 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35680693 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77102658 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 212 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114522071 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2438323 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394207776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166768 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.987550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 114526886 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2438240 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394234025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.166653 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.987457 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224085033 56.84% 56.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14184034 3.60% 60.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22893795 5.81% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22742785 5.77% 72.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20889438 5.30% 77.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11596058 2.94% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13058827 3.31% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11996655 3.04% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52761151 13.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224103808 56.85% 56.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14182639 3.60% 60.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22897810 5.81% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22745771 5.77% 72.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20892648 5.30% 77.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11601037 2.94% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13057020 3.31% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11991400 3.04% 86.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52761892 13.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394207776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.451900 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.882788 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129058894 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 72583383 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158800998 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6228602 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27535899 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26119356 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76952 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825527591 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 297029 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27535899 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135653385 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10117573 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47448086 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158253744 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15199089 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800585743 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1337 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3048778 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8951135 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 327 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954274745 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500443085 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500441750 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1335 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394234025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.451673 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.881828 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129061557 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 72597650 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158807244 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6229539 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27538035 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26120872 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76664 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825542137 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 294964 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27538035 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135654542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10112461 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47476958 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158262389 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15189640 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800582614 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3045147 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8947899 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 349 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954230037 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500483849 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500482489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288022454 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292887 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292884 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41810314 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170245714 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73473402 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28600787 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15864837 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755023538 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775253 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665282495 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1376367 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187359932 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479861351 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797621 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394207776 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.687644 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734895 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 287977746 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292997 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292995 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41790364 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170263021 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73493180 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28522055 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15837658 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755040585 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775393 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665344412 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1377558 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187353857 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479696912 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797761 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394234025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.687689 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735339 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 138685304 35.18% 35.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69974148 17.75% 52.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71487489 18.13% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53410155 13.55% 84.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31169458 7.91% 92.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15996787 4.06% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8767931 2.22% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2898481 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1818023 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 138748910 35.19% 35.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69932496 17.74% 52.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71500115 18.14% 71.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53381002 13.54% 84.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31138415 7.90% 92.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15994110 4.06% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8838982 2.24% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2889382 0.73% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1810613 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394207776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394234025 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 480591 5.01% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6540572 68.21% 73.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2567937 26.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 479873 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6514297 68.24% 73.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2551723 26.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447761903 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383485 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447783022 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383422 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -515,84 +514,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153367544 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63769466 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153378055 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63799818 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665282495 # Type of FU issued -system.cpu.iq.rate 1.644664 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9589100 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014414 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1735738010 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 946965616 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646015342 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665344412 # Type of FU issued +system.cpu.iq.rate 1.644046 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9545893 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014347 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1735846081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 946976022 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646072801 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674871482 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8586210 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674890194 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8556478 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44216159 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41012 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810921 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16612925 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44233466 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41675 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810117 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16632703 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19492 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6939 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19496 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 7207 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27535899 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5281663 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 386285 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760357745 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1115007 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170245714 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73473402 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286711 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219038 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12304 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810921 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4337552 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4003513 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8341065 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655860831 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150086003 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9421664 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27538035 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5291148 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 386655 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760374882 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1114721 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170263021 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73493180 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286851 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219754 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12032 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810117 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4339015 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4002364 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655919187 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150094220 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9425225 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558954 # number of nop insts executed -system.cpu.iew.exec_refs 212560295 # number of memory reference insts executed -system.cpu.iew.exec_branches 138490949 # Number of branches executed -system.cpu.iew.exec_stores 62474292 # Number of stores executed -system.cpu.iew.exec_rate 1.621373 # Inst execution rate -system.cpu.iew.wb_sent 650984327 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646015358 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374693412 # num instructions producing a value -system.cpu.iew.wb_consumers 646299598 # num instructions consuming a value +system.cpu.iew.exec_nop 1558904 # number of nop insts executed +system.cpu.iew.exec_refs 212597859 # number of memory reference insts executed +system.cpu.iew.exec_branches 138494490 # Number of branches executed +system.cpu.iew.exec_stores 62503639 # Number of stores executed +system.cpu.iew.exec_rate 1.620756 # Inst execution rate +system.cpu.iew.wb_sent 651040733 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646072817 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374723288 # num instructions producing a value +system.cpu.iew.wb_consumers 646307001 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.597033 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579752 # average fanout of values written-back +system.cpu.iew.wb_rate 1.596426 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579791 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189415917 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189435177 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7190999 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 366671877 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.230606 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7191667 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 366695990 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.557061 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.231965 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 158948889 43.35% 43.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98517703 26.87% 70.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33831327 9.23% 79.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18775088 5.12% 84.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16222583 4.42% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7456199 2.03% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6938304 1.89% 92.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3192877 0.87% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22788907 6.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159030399 43.37% 43.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98569557 26.88% 70.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33781130 9.21% 79.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18728324 5.11% 84.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16185625 4.41% 88.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7417790 2.02% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6942685 1.89% 92.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3160022 0.86% 93.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22880458 6.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366671877 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 366695990 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,221 +602,221 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22788907 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22880458 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104259916 # The number of ROB reads -system.cpu.rob.rob_writes 1548425259 # The number of ROB writes -system.cpu.timesIdled 328032 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10301844 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104211738 # The number of ROB reads +system.cpu.rob.rob_writes 1548465628 # The number of ROB writes +system.cpu.timesIdled 328564 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10465471 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.800632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.800632 # CPI: Total CPI of All Threads -system.cpu.ipc 1.249013 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.249013 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058504664 # number of integer regfile reads -system.cpu.int_regfile_writes 751970917 # number of integer regfile writes +system.cpu.cpi 0.801008 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.801008 # CPI: Total CPI of All Threads +system.cpu.ipc 1.248427 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.248427 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058780194 # number of integer regfile reads +system.cpu.int_regfile_writes 751998753 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210811449 # number of misc regfile reads +system.cpu.misc_regfile_reads 210849013 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 735317990 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1110574 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348852 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3503354 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3537044 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1075520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147641024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148716544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148716544 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2272504241 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 735301298 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1111058 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348843 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348843 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33804 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3504826 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3538630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1079232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147703872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148783104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148783104 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 4928 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273504243 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25334982 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 26125731 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1794529465 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1828577727 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.replacements 14954 # number of replacements -system.cpu.icache.tagsinuse 1101.424981 # Cycle average of tags in use -system.cpu.icache.total_refs 114501007 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16812 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6810.671366 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1101.424981 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537805 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537805 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114501007 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114501007 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114501007 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114501007 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114501007 # number of overall hits -system.cpu.icache.overall_hits::total 114501007 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21063 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21063 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21063 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21063 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21063 # number of overall misses -system.cpu.icache.overall_misses::total 21063 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 592520500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 592520500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 592520500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 592520500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 592520500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 592520500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114522070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114522070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114522070 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114522070 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114522070 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114522070 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 15008 # number of replacements +system.cpu.icache.tags.tagsinuse 1099.436561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114505770 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16868 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6788.343016 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1099.436561 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.536834 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.536834 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114505770 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114505770 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114505770 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114505770 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114505770 # number of overall hits +system.cpu.icache.overall_hits::total 114505770 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21115 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21115 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21115 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21115 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21115 # number of overall misses +system.cpu.icache.overall_misses::total 21115 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 590629979 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 590629979 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 590629979 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 590629979 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 590629979 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 590629979 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114526885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114526885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114526885 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114526885 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114526885 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114526885 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28130.869297 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28130.869297 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28130.869297 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28130.869297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28130.869297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28130.869297 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 770 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27972.056784 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27972.056784 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27972.056784 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27972.056784 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 633 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 64.166667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.300000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4178 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4178 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4178 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4178 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4178 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4178 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16885 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16885 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16885 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16885 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16885 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16885 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 427572518 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 427572518 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 427572518 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 427572518 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 427572518 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 427572518 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000147 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000147 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000147 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25322.624696 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25322.624696 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25322.624696 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25322.624696 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25322.624696 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25322.624696 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4174 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4174 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4174 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4174 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4174 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4174 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16941 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16941 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16941 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16941 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16941 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16941 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 425273769 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 425273769 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 425273769 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 425273769 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 425273769 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 425273769 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25103.227023 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25103.227023 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25103.227023 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 25103.227023 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25103.227023 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 25103.227023 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115420 # number of replacements -system.cpu.l2cache.tagsinuse 27103.497670 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1780537 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 146672 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 12.139584 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 102160649500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23017.556020 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 361.817862 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3724.123788 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.702440 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.011042 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.113651 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.827133 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13425 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 803929 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817354 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1110574 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1110574 # number of Writeback hits +system.cpu.l2cache.tags.replacements 115462 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27105.054655 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1782175 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 146717 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.147025 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 102215583000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23019.815136 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 365.213065 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3720.026454 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.702509 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011145 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113526 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.827181 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13469 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 804438 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 817907 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1111058 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1111058 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 63 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 63 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247575 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247575 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13425 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1051504 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1064929 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192221 # number of replacements -system.cpu.dcache.tagsinuse 4057.785515 # Cycle average of tags in use -system.cpu.dcache.total_refs 190145872 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196317 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.942715 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4220492000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4057.785515 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136179358 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136179358 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50988931 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50988931 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488837 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488837 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1192719 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.784175 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190184088 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196815 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.908510 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4223544250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.784175 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990670 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136217061 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136217061 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50989456 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50989456 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488807 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488807 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187168289 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187168289 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187168289 # number of overall hits -system.cpu.dcache.overall_hits::total 187168289 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1699578 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1699578 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3250375 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3250375 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4949953 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4949953 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4949953 # number of overall misses -system.cpu.dcache.overall_misses::total 4949953 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29584540500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29584540500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 69108485945 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 69108485945 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 701500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 701500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 98693026445 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 98693026445 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 98693026445 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 98693026445 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137878936 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137878936 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187206517 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187206517 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187206517 # number of overall hits +system.cpu.dcache.overall_hits::total 187206517 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1700496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1700496 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3249850 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3249850 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4950346 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4950346 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4950346 # number of overall misses +system.cpu.dcache.overall_misses::total 4950346 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29799414454 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29799414454 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 69603685702 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 69603685702 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 646250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 646250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 99403100156 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 99403100156 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 99403100156 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 99403100156 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137917557 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137917557 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488874 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488874 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488848 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488848 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192118242 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192118242 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192118242 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192118242 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012327 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012327 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059927 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059927 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025765 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025765 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025765 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17406.991912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17406.991912 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21261.696249 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21261.696249 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18959.459459 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18959.459459 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19938.174452 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19938.174452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19938.174452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19938.174452 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19233 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40481 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1722 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 665 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.168990 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 60.873684 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192156863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192156863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192156863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192156863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059917 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025762 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025762 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025762 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025762 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17523.954454 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17523.954454 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21417.507178 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21417.507178 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15762.195122 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15762.195122 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20080.030801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20080.030801 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21739 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 43165 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1718 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 667 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.653667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 64.715142 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110574 # number of writebacks -system.cpu.dcache.writebacks::total 1110574 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851549 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 851549 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902014 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2902014 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3753563 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3753563 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3753563 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3753563 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848029 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848029 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348361 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348361 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196390 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196390 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196390 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196390 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12568519034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12568519034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9922118995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9922118995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22490638029 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22490638029 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22490638029 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22490638029 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1111058 # number of writebacks +system.cpu.dcache.writebacks::total 1111058 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851983 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 851983 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2901479 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2901479 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3753462 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3753462 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3753462 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3753462 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348371 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348371 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196884 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196884 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196884 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196884 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12602071778 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12602071778 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9955936491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9955936491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22558008269 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22558008269 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22558008269 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22558008269 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14820.859940 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14820.859940 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28482.289909 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28482.289909 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18798.751268 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18798.751268 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18798.751268 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18798.751268 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14851.948972 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14851.948972 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28578.545548 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28578.545548 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 0fce97b03..b28088e7d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1434732024 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 9788 # number of replacements -system.cpu.icache.tagsinuse 982.663229 # Cycle average of tags in use -system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 9788 # number of replacements +system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 109895 # number of replacements -system.cpu.l2cache.tagsinuse 27243.192324 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1668833 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 141072 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.831396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 109895 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1134822 # number of replacements -system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use -system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1134822 # number of replacements +system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index d96ed8e27..d91a5905c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458090 # Number of seconds simulated -sim_ticks 458090415000 # Number of ticks simulated -final_tick 458090415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458202 # Number of seconds simulated +sim_ticks 458201684000 # Number of ticks simulated +final_tick 458201684000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88483 # Simulator instruction rate (inst/s) -host_op_rate 163615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49019747 # Simulator tick rate (ticks/s) -host_mem_usage 344468 # Number of bytes of host memory used -host_seconds 9345.02 # Real time elapsed on the host +host_inst_rate 111882 # Simulator instruction rate (inst/s) +host_op_rate 206882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61997502 # Simulator tick rate (ticks/s) +host_mem_usage 341328 # Number of bytes of host memory used +host_seconds 7390.65 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 202496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24476544 # Number of bytes read from this memory -system.physmem.bytes_read::total 24679040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18790272 # Number of bytes written to this memory -system.physmem.bytes_written::total 18790272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382446 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385610 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293598 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293598 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53431688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53873731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41018697 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41018697 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41018697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53431688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94892429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385610 # Total number of read requests seen -system.physmem.writeReqs 293598 # Total number of write requests seen -system.physmem.cpureqs 811581 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24679040 # Total number of bytes read from memory -system.physmem.bytesWritten 18790272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24679040 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18790272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 158 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 132366 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 26444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24212 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24050 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 23243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 22960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 23768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23988 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 18530 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18950 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18922 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18033 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18983 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18535 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17707 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 16952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 17709 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 17824 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 201408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24476096 # Number of bytes read from this memory +system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 201408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 201408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18788864 # Number of bytes written to this memory +system.physmem.bytes_written::total 18788864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3147 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293576 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293576 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 439562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53417735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53857297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 439562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41005663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41005663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41005663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 439562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53417735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94862960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385586 # Total number of read requests seen +system.physmem.writeReqs 293576 # Total number of write requests seen +system.physmem.cpureqs 810414 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24677504 # Total number of bytes read from memory +system.physmem.bytesWritten 18788864 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24677504 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18788864 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 131239 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 26436 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24489 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24210 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24783 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24073 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 23240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 22943 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 23791 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24001 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 18525 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 19821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18940 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18028 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18411 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18544 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17724 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 17345 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 16945 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 17717 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 17828 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 458090389000 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry +system.physmem.totGap 458201657000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385610 # Categorize read packet sizes +system.physmem.readPktSize::6 385586 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293598 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293576 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,347 +124,347 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12732 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 12733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 126022 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.851534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 161.962358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 666.348366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 54057 42.89% 42.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 23501 18.65% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 10538 8.36% 69.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 6321 5.02% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 4049 3.21% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2993 2.37% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 2158 1.71% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1750 1.39% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1435 1.14% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1167 0.93% 85.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 1218 0.97% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1087 0.86% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 749 0.59% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 671 0.53% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 595 0.47% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 568 0.45% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 568 0.45% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 525 0.42% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 573 0.45% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 736 0.58% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 592 0.47% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 743 0.59% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6177 4.90% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 481 0.38% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 330 0.26% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 288 0.23% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 210 0.17% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 190 0.15% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 142 0.11% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 147 0.12% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 96 0.08% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 92 0.07% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 69 0.05% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 52 0.04% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 45 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 44 0.03% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 35 0.03% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 33 0.03% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 28 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 24 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 31 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 21 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 18 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 25 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 20 0.02% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 17 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 13 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 15 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 13 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 16 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 6 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 9 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 7 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 17 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 9 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 8 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 13 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 9 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation +system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 125877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.228437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.863436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 669.217085 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 54117 42.99% 42.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 23349 18.55% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 10530 8.37% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 6425 5.10% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 4023 3.20% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 2874 2.28% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2162 1.72% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1748 1.39% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 1399 1.11% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 1145 0.91% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 1227 0.97% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1117 0.89% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 747 0.59% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 630 0.50% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 615 0.49% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 623 0.49% 89.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 541 0.43% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 508 0.40% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 588 0.47% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 726 0.58% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 627 0.50% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 694 0.55% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6218 4.94% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 497 0.39% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 336 0.27% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 279 0.22% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 216 0.17% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 162 0.13% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 151 0.12% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 121 0.10% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 106 0.08% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 85 0.07% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 80 0.06% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 63 0.05% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 52 0.04% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 41 0.03% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 42 0.03% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 32 0.03% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 20 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 25 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 22 0.02% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 23 0.02% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 19 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 14 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 22 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 12 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 19 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 11 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 20 0.02% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 17 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 11 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 14 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 8 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 8 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 8 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 7 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 14 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 8 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 5 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 13 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 4 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 8 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 5 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 4 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 8 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 6 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 6 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 3 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 6 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 5 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 5 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 9 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 9 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 4 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 4 0.00% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 7 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 9 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 3 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 8 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 11 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 5 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 5 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 5 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 4 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 4 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 8 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 5 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 5 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 5 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 10 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 5 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 4 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 4 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 4 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 4 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 373 0.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 126022 # Bytes accessed per row activation -system.physmem.totQLat 3040953000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11219526750 # Sum of mem lat for all requests -system.physmem.totBusLat 1927260000 # Total cycles spent in databus access -system.physmem.totBankLat 6251313750 # Total cycles spent in bank access -system.physmem.avgQLat 7889.32 # Average queueing delay per request -system.physmem.avgBankLat 16218.14 # Average bank access latency per request +system.physmem.bytesPerActivate::8192-8193 377 0.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 125877 # Bytes accessed per row activation +system.physmem.totQLat 3046093750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11221540000 # Sum of mem lat for all requests +system.physmem.totBusLat 1927185000 # Total cycles spent in databus access +system.physmem.totBankLat 6248261250 # Total cycles spent in bank access +system.physmem.avgQLat 7902.96 # Average queueing delay per request +system.physmem.avgBankLat 16210.85 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29107.46 # Average memory access latency -system.physmem.avgRdBW 53.87 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 41.02 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.87 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 41.02 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29113.81 # Average memory access latency +system.physmem.avgRdBW 53.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.25 # Average write queue length over time -system.physmem.readRowHits 346179 # Number of row buffer hits during reads -system.physmem.writeRowHits 206846 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.45 # Row buffer hit rate for writes -system.physmem.avgGap 674447.87 # Average gap between requests -system.membus.throughput 94892429 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178764 # Transaction distribution -system.membus.trans_dist::ReadResp 178764 # Transaction distribution -system.membus.trans_dist::Writeback 293598 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132366 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132366 # Transaction distribution -system.membus.trans_dist::ReadExReq 206846 # Transaction distribution -system.membus.trans_dist::ReadExResp 206846 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1329550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1329550 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43469312 # Total data (bytes) +system.physmem.avgWrQLen 9.78 # Average write queue length over time +system.physmem.readRowHits 346233 # Number of row buffer hits during reads +system.physmem.writeRowHits 206899 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.48 # Row buffer hit rate for writes +system.physmem.avgGap 674657.38 # Average gap between requests +system.membus.throughput 94862960 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178738 # Transaction distribution +system.membus.trans_dist::ReadResp 178738 # Transaction distribution +system.membus.trans_dist::Writeback 293576 # Transaction distribution +system.membus.trans_dist::UpgradeReq 131239 # Transaction distribution +system.membus.trans_dist::UpgradeResp 131239 # Transaction distribution +system.membus.trans_dist::ReadExReq 206848 # Transaction distribution +system.membus.trans_dist::ReadExResp 206848 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1327226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1327226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1327226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1327226 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43466368 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3305392000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3389530500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3861844643 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.branchPred.lookups 205596082 # Number of BP lookups -system.cpu.branchPred.condPredicted 205596082 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9898225 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117113450 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114684719 # Number of BTB hits +system.membus.respLayer1.occupancy 3902075273 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.branchPred.lookups 205568854 # Number of BP lookups +system.cpu.branchPred.condPredicted 205568854 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9898045 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117107860 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114698140 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.926172 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25065236 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1793499 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.942307 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25050036 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1792384 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 916341755 # number of cpu cycles simulated +system.cpu.numCycles 916561947 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167380851 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131684299 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205596082 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139749955 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352238514 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71080243 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 303608780 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49221 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 257762 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162013900 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2533511 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 884463501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.380571 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325217 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167337624 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131632693 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205568854 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139748176 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352252174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71070724 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 303559378 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 256407 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 161987307 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2533545 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 884373851 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.380748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536297540 60.64% 60.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23375974 2.64% 63.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25249823 2.85% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27885460 3.15% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17746776 2.01% 71.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22912915 2.59% 73.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29432713 3.33% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26649868 3.01% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174912432 19.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536185326 60.63% 60.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23385873 2.64% 63.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25265986 2.86% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27892803 3.15% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17753666 2.01% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22918818 2.59% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29434810 3.33% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26635470 3.01% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174901099 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 884463501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224366 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.235002 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222590662 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258678079 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295142458 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47123970 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60928332 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071292159 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60928332 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256060013 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 114129471 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306672128 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146656444 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035150603 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19208 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24905685 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106527720 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 191 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2137983705 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150412052 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5150294631 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 117421 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 884373851 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224283 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.234649 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222568980 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258608644 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295229836 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 47046921 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60919470 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071205121 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60919470 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 255995647 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 114297250 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16886 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306709824 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146434774 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035062210 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18307 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24837229 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106300367 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 277 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2137993094 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150291705 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5150182226 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 109479 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523942851 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1169 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1101 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 347123881 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495862419 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194434977 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195681210 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55050050 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975391803 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13688 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772107860 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 473436 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441529176 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734849750 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13136 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 884463501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.003596 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883133 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 523952240 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1150 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1079 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346047502 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495816702 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194427613 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195309908 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54766711 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975264807 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13440 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772060023 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484597 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441400489 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 734643480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12888 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 884373851 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.003745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883277 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 267821241 30.28% 30.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151877147 17.17% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137227346 15.52% 62.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131884953 14.91% 77.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91607169 10.36% 88.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55986805 6.33% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34422638 3.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11866983 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1769219 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 267848230 30.29% 30.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151701849 17.15% 47.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137335256 15.53% 62.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131820581 14.91% 77.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91575970 10.35% 88.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56038061 6.34% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34420312 3.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11858874 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1774718 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 884463501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 884373851 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4968361 32.63% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7638299 50.16% 82.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2620527 17.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4913366 32.39% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7647346 50.41% 82.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2610757 17.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2623300 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165765153 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352884 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880872 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2623506 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165695577 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352860 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880836 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -491,84 +491,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429256529 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170229122 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429278718 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170228526 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772107860 # Type of FU issued -system.cpu.iq.rate 1.933894 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15227187 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008593 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4444363529 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417156929 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744871940 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 16315 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 34548 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3820 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784704039 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7708 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172523009 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772060023 # Type of FU issued +system.cpu.iq.rate 1.933377 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15171469 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008561 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4444135081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2416902562 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744830840 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 32680 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3547 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784600923 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7063 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172561564 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111760262 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 384025 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 328721 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45275855 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111714545 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 391852 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328370 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45268501 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15305 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 564 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14755 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 580 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60928332 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 66654454 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7158115 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975405491 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 788328 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495862419 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194436041 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3451 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4460839 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82816 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 328721 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5900080 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4426535 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10326615 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1752972690 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424121378 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19135170 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60919470 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 66677729 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7180416 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975278247 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 784703 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495816702 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194428687 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3345 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4482902 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83440 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328370 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5898868 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4425517 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10324385 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1752929949 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424141217 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19130074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590916604 # number of memory reference insts executed -system.cpu.iew.exec_branches 167471832 # Number of branches executed -system.cpu.iew.exec_stores 166795226 # Number of stores executed -system.cpu.iew.exec_rate 1.913012 # Inst execution rate -system.cpu.iew.wb_sent 1749734148 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744875760 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325266031 # num instructions producing a value -system.cpu.iew.wb_consumers 1946145137 # num instructions consuming a value +system.cpu.iew.exec_refs 590928526 # number of memory reference insts executed +system.cpu.iew.exec_branches 167466016 # Number of branches executed +system.cpu.iew.exec_stores 166787309 # Number of stores executed +system.cpu.iew.exec_rate 1.912506 # Inst execution rate +system.cpu.iew.wb_sent 1749673980 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744834387 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325007870 # num instructions producing a value +system.cpu.iew.wb_consumers 1945707966 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.904176 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680970 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903673 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680990 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446445392 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446317369 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9927956 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823535169 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856616 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.436023 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9927482 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823454381 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.436978 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331309797 40.23% 40.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193436575 23.49% 63.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63121599 7.66% 71.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92647186 11.25% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25073312 3.04% 85.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27553603 3.35% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9217324 1.12% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11404021 1.38% 91.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69771752 8.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 331487662 40.26% 40.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193224596 23.47% 63.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63171510 7.67% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92561504 11.24% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24941236 3.03% 85.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27475920 3.34% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9375370 1.14% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11392855 1.38% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69823728 8.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823535169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823454381 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,226 +579,226 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69771752 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69823728 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2729197510 # The number of ROB reads -system.cpu.rob.rob_writes 4011957603 # The number of ROB writes -system.cpu.timesIdled 3360338 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31878254 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2728936723 # The number of ROB reads +system.cpu.rob.rob_writes 4011692646 # The number of ROB writes +system.cpu.timesIdled 3353511 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32188096 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.108196 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108196 # CPI: Total CPI of All Threads -system.cpu.ipc 0.902368 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.902368 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3313525285 # number of integer regfile reads -system.cpu.int_regfile_writes 1825886137 # number of integer regfile writes -system.cpu.fp_regfile_reads 3803 # number of floating regfile reads -system.cpu.fp_regfile_writes 18 # number of floating regfile writes -system.cpu.misc_regfile_reads 964657168 # number of misc regfile reads +system.cpu.cpi 1.108462 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108462 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902151 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3313440054 # number of integer regfile reads +system.cpu.int_regfile_writes 1825840966 # number of integer regfile writes +system.cpu.fp_regfile_reads 3533 # number of floating regfile reads +system.cpu.fp_regfile_writes 16 # number of floating regfile writes +system.cpu.misc_regfile_reads 964658774 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 699341277 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1903111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1903110 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330801 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 133805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 133805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771738 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771738 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 147545 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7666657 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7814202 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 436416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311355136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 311791552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311791552 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8569984 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4904454883 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 698991407 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1901821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1901820 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 132628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 132628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771784 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771784 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 146337 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7664164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7810501 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 435712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311349248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 311784960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311784960 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8494080 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4903151186 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 211090494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 209959241 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3868088996 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.icache.replacements 5303 # number of replacements -system.cpu.icache.tagsinuse 1039.981291 # Cycle average of tags in use -system.cpu.icache.total_refs 161869191 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6885 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 23510.412636 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1039.981291 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.507803 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.507803 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161871216 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161871216 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161871216 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161871216 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161871216 # number of overall hits -system.cpu.icache.overall_hits::total 161871216 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 142683 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 142683 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 142683 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 142683 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 142683 # number of overall misses -system.cpu.icache.overall_misses::total 142683 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 931781000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 931781000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 931781000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 931781000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 931781000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 931781000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162013899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162013899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162013899 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162013899 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162013899 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162013899 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000881 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000881 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000881 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000881 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000881 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000881 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6530.427591 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6530.427591 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6530.427591 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6530.427591 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6530.427591 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6530.427591 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 250 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer1.occupancy 3959772656 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 5293 # number of replacements +system.cpu.icache.tags.tagsinuse 1036.459072 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161843741 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6867 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23568.332751 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1036.459072 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506084 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506084 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161845824 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161845824 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161845824 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161845824 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161845824 # number of overall hits +system.cpu.icache.overall_hits::total 161845824 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 141483 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 141483 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 141483 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 141483 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 141483 # number of overall misses +system.cpu.icache.overall_misses::total 141483 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 929611982 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 929611982 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 929611982 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 929611982 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 929611982 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 929611982 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161987307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161987307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161987307 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161987307 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161987307 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161987307 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000873 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000873 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000873 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000873 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000873 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000873 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6570.485373 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6570.485373 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6570.485373 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6570.485373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6570.485373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6570.485373 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 250 # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1957 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1957 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1957 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1957 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1957 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1957 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 140726 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 140726 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 140726 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 140726 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 140726 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 140726 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 559745506 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 559745506 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 559745506 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 559745506 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 559745506 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 559745506 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000869 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000869 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000869 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3977.555718 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3977.555718 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3977.555718 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3977.555718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3977.555718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3977.555718 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1954 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1954 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1954 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1954 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1954 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1954 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382459 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385607 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3148 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382459 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385607 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205059000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10984214957 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11189273957 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1316213142 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1316213142 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11623719520 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11623719520 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205059000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22607934477 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22812993477 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205059000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22607934477 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22812993477 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462329 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099638 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101043 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989081 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989081 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268055 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268055 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.464076 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150927 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151768 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.464076 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150927 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151768 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65108.767773 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62563.391002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62608.456409 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.562194 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.562194 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56169.333933 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56169.333933 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65108.767773 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59104.995011 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59154.269686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65108.767773 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59104.995011 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59154.269686 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101034 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989376 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989376 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268039 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268039 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462329 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151761 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462329 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151761 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65139.453621 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62555.683133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62601.189203 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.659752 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.659752 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56189.065104 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56189.065104 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65139.453621 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59112.047244 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59161.253496 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65139.453621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59112.047244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59161.253496 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2530027 # number of replacements -system.cpu.dcache.tagsinuse 4088.382661 # Cycle average of tags in use -system.cpu.dcache.total_refs 396086661 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2534123 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 156.301277 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1759751000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.382661 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998140 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998140 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247356702 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247356702 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148237858 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148237858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395594560 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395594560 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395594560 # number of overall hits -system.cpu.dcache.overall_hits::total 395594560 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2862804 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2862804 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 922344 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 922344 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3785148 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3785148 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3785148 # number of overall misses -system.cpu.dcache.overall_misses::total 3785148 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57011675000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57011675000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25670326998 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25670326998 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 82682001998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 82682001998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 82682001998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 82682001998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250219506 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250219506 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 2529980 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.352551 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 396070659 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534076 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.297861 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.352551 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 247340077 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247340077 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148239061 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148239061 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395579138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395579138 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395579138 # number of overall hits +system.cpu.dcache.overall_hits::total 395579138 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2863342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2863342 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 921141 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 921141 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3784483 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3784483 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3784483 # number of overall misses +system.cpu.dcache.overall_misses::total 3784483 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57420164907 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57420164907 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25863644657 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25863644657 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83283809564 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83283809564 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83283809564 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83283809564 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250203419 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250203419 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399379708 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399379708 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399379708 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399379708 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011441 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011441 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006184 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006184 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009478 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009478 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009478 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009478 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19914.627407 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19914.627407 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27831.619220 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27831.619220 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21843.796332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21843.796332 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6595 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399363621 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399363621 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399363621 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399363621 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011444 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011444 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006176 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006176 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009476 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009476 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009476 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009476 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.547535 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.547535 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28077.834617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28077.834617 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22006.654427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22006.654427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22006.654427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22006.654427 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7199 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.828614 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.571219 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330801 # number of writebacks -system.cpu.dcache.writebacks::total 2330801 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100153 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1100153 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17067 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17067 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1117220 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1117220 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1117220 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1117220 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762651 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762651 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 905277 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 905277 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2667928 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2667928 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2667928 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2667928 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30822255503 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30822255503 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23648350501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23648350501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54470606004 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 54470606004 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54470606004 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 54470606004 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2330756 # number of writebacks +system.cpu.dcache.writebacks::total 2330756 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100793 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1100793 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16986 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16986 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1117779 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1117779 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1117779 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1117779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762549 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762549 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 904155 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 904155 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2666704 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2666704 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2666704 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2666704 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30902624251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30902624251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23743181593 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23743181593 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54645805844 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54645805844 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54645805844 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54645805844 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006069 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006069 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006680 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006680 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17486.306423 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17486.306423 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26122.778444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26122.778444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006062 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006062 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006677 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006677 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006677 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006677 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17532.916390 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17532.916390 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26260.078850 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26260.078850 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20491.890305 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20491.890305 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20491.890305 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20491.890305 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 3dc840346..5255bf68c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 3295745698 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.356491 # Cycle average of tags in use -system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1253 # number of replacements +system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits @@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 348459 # number of replacements -system.cpu.l2cache.tagsinuse 29286.402664 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.893750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 348459 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits @@ -293,15 +293,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.415783 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743930 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2514362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index dfb21513b..3f8921752 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139913 # Number of seconds simulated -sim_ticks 139912878500 # Number of ticks simulated -final_tick 139912878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139916 # Number of seconds simulated +sim_ticks 139916242500 # Number of ticks simulated +final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81894 # Simulator instruction rate (inst/s) -host_op_rate 81894 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28740964 # Simulator tick rate (ticks/s) -host_mem_usage 231128 # Number of bytes of host memory used -host_seconds 4868.07 # Real time elapsed on the host +host_inst_rate 84616 # Simulator instruction rate (inst/s) +host_op_rate 84616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29697100 # Simulator tick rate (ticks/s) +host_mem_usage 231112 # Number of bytes of host memory used +host_seconds 4711.44 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1536499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1815530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3352029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1536499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1536499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1536499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1815530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3352029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1536462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1815486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3351948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1536462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1536462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 139912806500 # Total gap between requests +system.physmem.totGap 139916169000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 186 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -219,14 +219,14 @@ system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation -system.physmem.totQLat 37727500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 172831250 # Sum of mem lat for all requests +system.physmem.totQLat 39772250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 175041000 # Sum of mem lat for all requests system.physmem.totBusLat 36640000 # Total cycles spent in databus access -system.physmem.totBankLat 98463750 # Total cycles spent in bank access -system.physmem.avgQLat 5148.40 # Average queueing delay per request -system.physmem.avgBankLat 13436.65 # Average bank access latency per request +system.physmem.totBankLat 98628750 # Total cycles spent in bank access +system.physmem.avgQLat 5427.44 # Average queueing delay per request +system.physmem.avgBankLat 13459.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23585.05 # Average memory access latency +system.physmem.avgMemAccLat 23886.60 # Average memory access latency system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s @@ -239,8 +239,8 @@ system.physmem.readRowHits 6626 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19092904.82 # Average gap between requests -system.membus.throughput 3352029 # Throughput (bytes/s) +system.physmem.avgGap 19093363.67 # Average gap between requests +system.membus.throughput 3351948 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution system.membus.trans_dist::ReadExReq 3145 # Transaction distribution @@ -251,39 +251,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992 system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 468992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8784000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68408750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68414000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 53489761 # Number of BP lookups -system.cpu.branchPred.condPredicted 30685482 # Number of conditional branches predicted +system.cpu.branchPred.lookups 53489675 # Number of BP lookups +system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882438 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits +system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15212540 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263416 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263540 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754611 # DTB read hits +system.cpu.dtb.read_hits 94754653 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754632 # DTB read accesses -system.cpu.dtb.write_hits 73521122 # DTB write hits +system.cpu.dtb.read_accesses 94754674 # DTB read accesses +system.cpu.dtb.write_hits 73521120 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521157 # DTB write accesses -system.cpu.dtb.data_hits 168275733 # DTB hits +system.cpu.dtb.write_accesses 73521155 # DTB write accesses +system.cpu.dtb.data_hits 168275773 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275789 # DTB accesses -system.cpu.itb.fetch_hits 48611325 # ITB hits +system.cpu.dtb.data_accesses 168275829 # DTB accesses +system.cpu.itb.fetch_hits 48611327 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655845 # ITB accesses +system.cpu.itb.fetch_accesses 48655847 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -297,18 +297,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279825758 # number of cpu cycles simulated +system.cpu.numCycles 279832486 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24259255 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386575 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 29230507 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722434 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631956 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828437 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484572 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484570 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -319,12 +319,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279401420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400467 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7883 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13519017 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306741 # Number of cycles cpu stages are processed. -system.cpu.activity 95.168773 # Percentage of cycles cpu is active +system.cpu.timesIdled 7142 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13525828 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306658 # Number of cycles cpu stages are processed. +system.cpu.activity 95.166455 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -336,112 +336,112 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701908 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701925 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701908 # CPI: Total CPI of All Threads -system.cpu.ipc 1.424689 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701925 # CPI: Total CPI of All Threads +system.cpu.ipc 1.424654 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.424689 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78078009 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747749 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.097633 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107174029 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.424654 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78084810 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747676 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.095874 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107180757 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.699727 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102610556 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215202 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.330554 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181081179 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744579 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.287880 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90357849 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467909 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.709245 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1975 # number of replacements -system.cpu.icache.tagsinuse 1830.982662 # Cycle average of tags in use -system.cpu.icache.total_refs 48606794 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12453.700743 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1830.982662 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894035 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894035 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48606794 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606794 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606794 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606794 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606794 # number of overall hits -system.cpu.icache.overall_hits::total 48606794 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4531 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4531 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4531 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4531 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4531 # number of overall misses -system.cpu.icache.overall_misses::total 4531 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 268165000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 268165000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 268165000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 268165000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 268165000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 268165000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611325 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611325 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611325 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611325 # number of overall (read+write) accesses +system.cpu.stage1.utilization 61.698244 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102617259 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215227 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.329040 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181087860 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744626 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.287049 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 1975 # number of replacements +system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606795 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606795 # number of overall hits +system.cpu.icache.overall_hits::total 48606795 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4532 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4532 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4532 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4532 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4532 # number of overall misses +system.cpu.icache.overall_misses::total 4532 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 272220250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 272220250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 272220250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 272220250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 272220250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 272220250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611327 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611327 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611327 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611327 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611327 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611327 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59184.506731 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59184.506731 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59184.506731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59184.506731 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 326 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60066.251103 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60066.251103 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60066.251103 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60066.251103 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 108.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 110 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 628 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 628 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 628 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 628 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 628 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 629 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 629 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 629 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 629 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234852500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 234852500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234852500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 234852500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234852500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 234852500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 236384250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 236384250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 236384250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 236384250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 236384250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 236384250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60172.303356 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60172.303356 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60564.757879 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60564.757879 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 3981449 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 3981353 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -457,23 +457,23 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 5854500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6540750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6228499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6779999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3906.975758 # Cycle average of tags in use -system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.554458 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2908.829780 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.591520 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019153 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119231 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 370.550028 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -498,17 +498,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 225463500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 58932500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 284396000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 213301500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 213301500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 225463500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 272234000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 497697500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 225463500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 272234000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 497697500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 226995250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59463500 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -533,17 +533,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67122.208991 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71520.024272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67988.524982 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67822.416534 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67822.416534 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67122.208991 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68590.073066 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67917.235262 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67122.208991 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68590.073066 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67917.235262 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67578.222685 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72164.441748 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68481.651924 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68248.092210 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68248.092210 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68381.413755 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68381.413755 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,17 +563,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183879500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 48740750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 232620250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 174684500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 174684500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183879500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 223425250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 407304750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183879500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 223425250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 407304750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 184726250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49135000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 233861250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175601750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175601750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184726250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 224736750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 409463000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184726250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 224736750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 409463000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -585,51 +585,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54742.334028 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59151.395631 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55610.865408 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55543.561208 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55543.561208 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54742.334028 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56292.579995 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55581.980076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54742.334028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56292.579995 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55581.980076 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54994.417982 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59629.854369 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55907.542434 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55835.214626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55835.214626 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.992544 # Cycle average of tags in use -system.cpu.dcache.total_refs 168254254 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40523.664258 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.992544 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802000 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802000 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501073 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501073 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254254 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254254 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254254 # number of overall hits -system.cpu.dcache.overall_hits::total 168254254 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501075 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501075 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254256 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254256 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254256 # number of overall hits +system.cpu.dcache.overall_hits::total 168254256 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19656 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19656 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20964 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20964 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20964 # number of overall misses -system.cpu.dcache.overall_misses::total 20964 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84017000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84017000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1065172500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1065172500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1149189500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1149189500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1149189500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1149189500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 19654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19654 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20962 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20962 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20962 # number of overall misses +system.cpu.dcache.overall_misses::total 20962 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 85220999 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 85220999 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1076127000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1076127000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1161347999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1161347999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1161347999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1161347999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -646,19 +646,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64233.180428 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64233.180428 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54190.705128 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54190.705128 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54817.282007 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54817.282007 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28818 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65153.668960 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65153.668960 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54753.587056 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54753.587056 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55402.537878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55402.537878 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 562 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 596 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.277580 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.743289 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -666,12 +666,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16454 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16454 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16812 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16812 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16812 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16812 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16452 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16452 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16810 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16810 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16810 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16810 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -680,14 +680,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61415001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 61415001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 217011500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 217011500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278426501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 278426501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278426501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 278426501 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61946751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 61946751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218347750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 218347750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 280294501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 280294501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 280294501 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 280294501 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -696,14 +696,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64647.369474 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64647.369474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67773.735166 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67773.735166 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65207.106316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65207.106316 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68191.052467 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68191.052467 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 73956e98a..1f99291ed 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077363 # Number of seconds simulated -sim_ticks 77363103500 # Number of ticks simulated -final_tick 77363103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077522 # Number of seconds simulated +sim_ticks 77521581000 # Number of ticks simulated +final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219490 # Simulator instruction rate (inst/s) -host_op_rate 219490 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45211856 # Simulator tick rate (ticks/s) +host_inst_rate 159390 # Simulator instruction rate (inst/s) +host_op_rate 159390 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32899346 # Simulator tick rate (ticks/s) host_mem_usage 233160 # Number of bytes of host memory used -host_seconds 1711.12 # Real time elapsed on the host +host_seconds 2356.33 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 476224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220864 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7441 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2854901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3300798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6155699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2854901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2854901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2854901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3300798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6155699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7441 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory +system.physmem.bytes_read::total 476288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2850716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3293225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6143941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2850716 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2850716 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2850716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3293225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6143941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7442 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7441 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 476224 # Total number of bytes read from memory +system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 476288 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 476224 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 599 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 527 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 600 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 447 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 516 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 517 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 435 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 436 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 405 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 337 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 305 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 453 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 542 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 454 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 379 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 77363015000 # Total gap between requests +system.physmem.totGap 77521491500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7441 # Categorize read packet sizes +system.physmem.readPktSize::6 7442 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2033 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 243 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,138 +149,138 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 761 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 617.293035 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 239.548208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1200.351847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 242 31.80% 31.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 107 14.06% 45.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 65 8.54% 54.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 58 7.62% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 31 4.07% 66.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 22 2.89% 68.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 22 2.89% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 17 2.23% 74.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 1.71% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 18 2.37% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.53% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.58% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 9 1.18% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 10 1.31% 82.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.66% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.66% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 18 2.37% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.39% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 7 0.92% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 4 0.53% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.39% 90.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 5 0.66% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 7 0.92% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.39% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.39% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 3 0.39% 94.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.13% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.13% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 3 0.39% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.13% 96.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.26% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.13% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.13% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.13% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 7 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 761 # Bytes accessed per row activation -system.physmem.totQLat 39473750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 177700000 # Sum of mem lat for all requests -system.physmem.totBusLat 37205000 # Total cycles spent in databus access -system.physmem.totBankLat 101021250 # Total cycles spent in bank access -system.physmem.avgQLat 5304.90 # Average queueing delay per request -system.physmem.avgBankLat 13576.30 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 621.460317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 241.668493 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1200.727367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 238 31.48% 31.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 108 14.29% 45.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 62 8.20% 53.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 57 7.54% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 33 4.37% 65.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 22 2.91% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 21 2.78% 71.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 18 2.38% 73.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 13 1.72% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 16 2.12% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 6 0.79% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 12 1.59% 80.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 9 1.19% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 9 1.19% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.66% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.79% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 17 2.25% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.40% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 7 0.93% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 4 0.53% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.40% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.79% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 7 0.93% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.40% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.40% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.26% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.13% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.13% 94.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.13% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 3 0.40% 95.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.26% 96.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.13% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.26% 97.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.13% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 7 0.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 756 # Bytes accessed per row activation +system.physmem.totQLat 42048500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 179991000 # Sum of mem lat for all requests +system.physmem.totBusLat 37210000 # Total cycles spent in databus access +system.physmem.totBankLat 100732500 # Total cycles spent in bank access +system.physmem.avgQLat 5650.16 # Average queueing delay per request +system.physmem.avgBankLat 13535.68 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23881.20 # Average memory access latency -system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24185.84 # Average memory access latency +system.physmem.avgRdBW 6.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.14 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6680 # Number of row buffer hits during reads +system.physmem.readRowHits 6686 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10396857.28 # Average gap between requests -system.membus.throughput 6155699 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4309 # Transaction distribution -system.membus.trans_dist::ReadResp 4309 # Transaction distribution +system.physmem.avgGap 10416755.11 # Average gap between requests +system.membus.throughput 6143941 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4310 # Transaction distribution +system.membus.trans_dist::ReadResp 4310 # Transaction distribution system.membus.trans_dist::ReadExReq 3132 # Transaction distribution system.membus.trans_dist::ReadExResp 3132 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 14882 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 14882 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 476224 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476224 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 14884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 14884 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 476288 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476288 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9093000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9304000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69496500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69668500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 50225543 # Number of BP lookups -system.cpu.branchPred.condPredicted 29217666 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1195897 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25687498 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23216118 # Number of BTB hits +system.cpu.branchPred.lookups 50329141 # Number of BP lookups +system.cpu.branchPred.condPredicted 29286929 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1209855 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26570475 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23288927 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.379055 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9009525 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1024 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.649645 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9008918 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1078 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101778798 # DTB read hits -system.cpu.dtb.read_misses 78056 # DTB read misses -system.cpu.dtb.read_acv 48605 # DTB read access violations -system.cpu.dtb.read_accesses 101856854 # DTB read accesses -system.cpu.dtb.write_hits 78401927 # DTB write hits -system.cpu.dtb.write_misses 1498 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 78403425 # DTB write accesses -system.cpu.dtb.data_hits 180180725 # DTB hits -system.cpu.dtb.data_misses 79554 # DTB misses -system.cpu.dtb.data_acv 48607 # DTB access violations -system.cpu.dtb.data_accesses 180260279 # DTB accesses -system.cpu.itb.fetch_hits 50199009 # ITB hits -system.cpu.itb.fetch_misses 367 # ITB misses +system.cpu.dtb.read_hits 101805775 # DTB read hits +system.cpu.dtb.read_misses 78244 # DTB read misses +system.cpu.dtb.read_acv 48603 # DTB read access violations +system.cpu.dtb.read_accesses 101884019 # DTB read accesses +system.cpu.dtb.write_hits 78424815 # DTB write hits +system.cpu.dtb.write_misses 1501 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 78426316 # DTB write accesses +system.cpu.dtb.data_hits 180230590 # DTB hits +system.cpu.dtb.data_misses 79745 # DTB misses +system.cpu.dtb.data_acv 48606 # DTB access violations +system.cpu.dtb.data_accesses 180310335 # DTB accesses +system.cpu.itb.fetch_hits 50278510 # ITB hits +system.cpu.itb.fetch_misses 355 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50199376 # ITB accesses +system.cpu.itb.fetch_accesses 50278865 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -294,238 +294,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 154726209 # number of cpu cycles simulated +system.cpu.numCycles 155043164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51083952 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 448497930 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50225543 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32225643 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78739470 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6093368 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19754761 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10148 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50199009 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 408107 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154447023 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.903895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325218 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 51171798 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449189873 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50329141 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32297845 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78873322 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6177793 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19775166 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 10164 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 50278510 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 413807 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154759425 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.902504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324797 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75707553 49.02% 49.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4276532 2.77% 51.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6874422 4.45% 56.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5367897 3.48% 59.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11734775 7.60% 67.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7804305 5.05% 72.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5608156 3.63% 76.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1827762 1.18% 77.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35245621 22.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75886103 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4289159 2.77% 51.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6884479 4.45% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5373987 3.47% 59.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11775541 7.61% 67.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7819980 5.05% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5600753 3.62% 76.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1832171 1.18% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35297252 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154447023 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324609 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.898655 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56435005 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15098519 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74108370 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3950827 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4854302 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9469599 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4266 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 444616188 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12118 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4854302 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59563357 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4893725 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 414604 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75021983 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9699052 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440177556 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 167 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8017745 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287187239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 578692114 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 306192880 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 272499234 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154759425 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324614 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.897192 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56546720 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15105326 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74238970 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3943829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4924580 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9495837 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4282 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 445245835 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12211 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4924580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59688043 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4892244 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 416020 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75141817 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9696721 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440741300 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25268 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8017940 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287478957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 579418122 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 306415899 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 273002223 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27654910 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36841 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27864767 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104645789 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80545124 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8910343 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6399312 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408008914 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401637302 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 964402 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32300806 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15167317 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 71 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154447023 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.600486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995525 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27946628 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36876 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 265 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27780890 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104697675 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80623147 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8951892 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6419862 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408420930 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401925039 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 976126 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32712161 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15467708 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154759425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.597096 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.996071 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28234595 18.28% 18.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25848670 16.74% 35.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25579083 16.56% 51.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24239826 15.69% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21261159 13.77% 81.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15485386 10.03% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8478015 5.49% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3990980 2.58% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1329309 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28451061 18.38% 18.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25861408 16.71% 35.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25614965 16.55% 51.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24252162 15.67% 67.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21259746 13.74% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15502795 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8516760 5.50% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3980528 2.57% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1320000 0.85% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154447023 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154759425 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 34190 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 34116 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 57000 0.48% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5570 0.05% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1934681 16.39% 17.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1747492 14.80% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5061407 42.87% 74.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2960127 25.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 59668 0.50% 0.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5432 0.05% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5299 0.04% 0.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1955339 16.54% 17.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1744150 14.75% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5075259 42.92% 75.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2944520 24.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155697269 38.77% 38.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126268 0.53% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155814394 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126224 0.53% 39.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32795718 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7492895 1.87% 49.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2793275 0.70% 50.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16555197 4.12% 54.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1576539 0.39% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103353833 25.73% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79212727 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32839124 8.17% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7506811 1.87% 49.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2794214 0.70% 50.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556558 4.12% 54.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1581320 0.39% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103393269 25.72% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79279544 19.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401637302 # Type of FU issued -system.cpu.iq.rate 2.595794 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11805850 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029394 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 633814426 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260039391 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234669938 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 336677453 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180319624 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161314335 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241373993 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172035578 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15061229 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401925039 # Type of FU issued +system.cpu.iq.rate 2.592343 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11823783 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029418 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 634356878 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260386455 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234772610 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 337052534 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180795959 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161415506 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241485172 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172230069 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15009534 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9891302 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112335 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 49025 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7024395 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9943188 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112068 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 49084 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7102418 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3733 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260799 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3689 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4854302 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2516728 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 369298 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 432783708 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 121887 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104645789 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80545124 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 286 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 93 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 98 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 49025 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 940065 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 405593 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1345658 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398139116 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101905490 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3498186 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4924580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2516499 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 372884 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 433248692 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 121349 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104697675 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80623147 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 81 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 49084 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 956530 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 406825 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1363355 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398354690 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101932663 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3570349 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24774508 # number of nop insts executed -system.cpu.iew.exec_refs 180308945 # number of memory reference insts executed -system.cpu.iew.exec_branches 46542252 # Number of branches executed -system.cpu.iew.exec_stores 78403455 # Number of stores executed -system.cpu.iew.exec_rate 2.573185 # Inst execution rate -system.cpu.iew.wb_sent 396614980 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 395984273 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193530512 # num instructions producing a value -system.cpu.iew.wb_consumers 271082574 # num instructions consuming a value +system.cpu.iew.exec_nop 24827504 # number of nop insts executed +system.cpu.iew.exec_refs 180359006 # number of memory reference insts executed +system.cpu.iew.exec_branches 46573877 # Number of branches executed +system.cpu.iew.exec_stores 78426343 # Number of stores executed +system.cpu.iew.exec_rate 2.569315 # Inst execution rate +system.cpu.iew.wb_sent 396825960 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396188116 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193569295 # num instructions producing a value +system.cpu.iew.wb_consumers 271188688 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.559258 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713917 # average fanout of values written-back +system.cpu.iew.wb_rate 2.555341 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713781 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34145749 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34614887 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1191710 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149592721 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.665000 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.996623 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1205659 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149834845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.660693 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.995613 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55286060 36.96% 36.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22516991 15.05% 52.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13020116 8.70% 60.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11469174 7.67% 68.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8183204 5.47% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5453733 3.65% 77.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5164454 3.45% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3280279 2.19% 83.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25218710 16.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55453685 37.01% 37.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22592497 15.08% 52.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13053957 8.71% 60.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11447163 7.64% 68.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8190236 5.47% 73.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5440968 3.63% 77.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5148789 3.44% 80.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3296235 2.20% 83.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25211315 16.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149592721 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149834845 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,212 +536,212 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25218710 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25211315 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557181366 # The number of ROB reads -system.cpu.rob.rob_writes 870483842 # The number of ROB writes -system.cpu.timesIdled 3633 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 279186 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557900023 # The number of ROB reads +system.cpu.rob.rob_writes 871491746 # The number of ROB writes +system.cpu.timesIdled 3551 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 283739 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.411972 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.411972 # CPI: Total CPI of All Threads -system.cpu.ipc 2.427351 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.427351 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 397971851 # number of integer regfile reads -system.cpu.int_regfile_writes 170072905 # number of integer regfile writes -system.cpu.fp_regfile_reads 156478965 # number of floating regfile reads -system.cpu.fp_regfile_writes 104018276 # number of floating regfile writes +system.cpu.cpi 0.412816 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.412816 # CPI: Total CPI of All Threads +system.cpu.ipc 2.422389 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.422389 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398140602 # number of integer regfile reads +system.cpu.int_regfile_writes 170166273 # number of integer regfile writes +system.cpu.fp_regfile_reads 156587084 # number of floating regfile reads +system.cpu.fp_regfile_writes 104079306 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7367647 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3191 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3191 # Transaction distribution +system.cpu.toL2Bus.throughput 7370748 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9009 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 17157 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 17190 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 260736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 569984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 569984 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 310656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 571392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 571392 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5108000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5130000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6111000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6844000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6265500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6767250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 2147 # number of replacements -system.cpu.icache.tagsinuse 1831.625379 # Cycle average of tags in use -system.cpu.icache.total_refs 50193388 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4074 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12320.419244 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1831.625379 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894348 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894348 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50193388 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50193388 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50193388 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50193388 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50193388 # number of overall hits -system.cpu.icache.overall_hits::total 50193388 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses -system.cpu.icache.overall_misses::total 5621 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 317313500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 317313500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 317313500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 317313500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 317313500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 317313500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50199009 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50199009 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50199009 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50199009 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50199009 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50199009 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 2147 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.618681 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50272888 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4074 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12339.933235 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.618681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894345 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894345 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50272888 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50272888 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50272888 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50272888 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50272888 # number of overall hits +system.cpu.icache.overall_hits::total 50272888 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5622 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5622 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5622 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5622 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5622 # number of overall misses +system.cpu.icache.overall_misses::total 5622 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 322487500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 322487500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 322487500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 322487500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 322487500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 322487500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50278510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50278510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50278510 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50278510 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50278510 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50278510 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56451.432130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56451.432130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56451.432130 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56451.432130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56451.432130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56451.432130 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 403 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57361.704020 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 57361.704020 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 57361.704020 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 57361.704020 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 57361.704020 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 57361.704020 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 272 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.571429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1547 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1547 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1547 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1547 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1547 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1547 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1548 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1548 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1548 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1548 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1548 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1548 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4074 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4074 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4074 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 4074 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4074 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4074 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 240569000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 240569000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 240569000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 240569000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 240569000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 240569000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242677000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 242677000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242677000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 242677000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242677000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 242677000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59049.828179 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59049.828179 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59049.828179 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59049.828179 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59049.828179 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59049.828179 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59567.255768 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59567.255768 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900750 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.952483 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900750 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54566.246742 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63592.182030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56360.962877 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56067.768199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56067.768199 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54566.246742 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54566.246742 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 776 # number of replacements -system.cpu.dcache.tagsinuse 3295.678448 # Cycle average of tags in use -system.cpu.dcache.total_refs 159952392 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38293.605937 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3295.678448 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804609 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804609 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86451599 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86451599 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500787 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500787 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 159952386 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 159952386 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 159952386 # number of overall hits -system.cpu.dcache.overall_hits::total 159952386 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1809 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1809 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19942 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19942 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21751 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21751 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21751 # number of overall misses -system.cpu.dcache.overall_misses::total 21751 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 111333000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 111333000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1028184585 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1028184585 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1139517585 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1139517585 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1139517585 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1139517585 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86453408 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86453408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 788 # number of replacements +system.cpu.dcache.tags.tagsinuse 3294.798817 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 160031202 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4188 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38211.843840 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3294.798817 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804394 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 86530434 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86530434 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500763 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500763 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 160031197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 160031197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 160031197 # number of overall hits +system.cpu.dcache.overall_hits::total 160031197 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1798 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1798 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19966 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19966 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21764 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21764 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21764 # number of overall misses +system.cpu.dcache.overall_misses::total 21764 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114434250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114434250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1039316587 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1039316587 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1153750837 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1153750837 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1153750837 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1153750837 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86532232 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86532232 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 159974137 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 159974137 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 159974137 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 159974137 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 160052961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 160052961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 160052961 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 160052961 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000272 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000272 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61543.946932 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61543.946932 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51558.749624 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51558.749624 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52389.204404 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52389.204404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52389.204404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52389.204404 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 37387 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63645.300334 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63645.300334 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52054.321697 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52054.321697 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53011.892897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53011.892897 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 38531 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 654 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.166667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.915902 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 655 # number of writebacks -system.cpu.dcache.writebacks::total 655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 823 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 823 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16751 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16751 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17574 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17574 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17574 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17574 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4177 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4177 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4177 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4177 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 66792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 66792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 216966500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 216966500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 283759000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 283759000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 283759000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 283759000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 666 # number of writebacks +system.cpu.dcache.writebacks::total 666 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 810 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16766 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16766 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17576 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17576 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17576 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17576 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3200 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3200 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4188 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4188 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4188 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4188 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67480500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67480500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218199250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 218199250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285679750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 285679750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285679750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 285679750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67740.872211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67740.872211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67993.262300 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67993.262300 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67933.684463 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67933.684463 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67933.684463 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67933.684463 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68300.101215 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68300.101215 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68187.265625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68187.265625 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index ff5b38f2f..2e7f2c614 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1134670186 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1769 # number of replacements -system.cpu.icache.tagsinuse 1795.138964 # Cycle average of tags in use -system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1769 # number of replacements +system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use -system.cpu.l2cache.total_refs 677 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.148270 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.115127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits @@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 3fe39b26c..31843ed63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068340 # Number of seconds simulated -sim_ticks 68340072000 # Number of ticks simulated -final_tick 68340072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068375 # Number of seconds simulated +sim_ticks 68375005500 # Number of ticks simulated +final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97727 # Simulator instruction rate (inst/s) -host_op_rate 124939 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24460648 # Simulator tick rate (ticks/s) -host_mem_usage 254748 # Number of bytes of host memory used -host_seconds 2793.88 # Real time elapsed on the host +host_inst_rate 171790 # Simulator instruction rate (inst/s) +host_op_rate 219625 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43020256 # Simulator tick rate (ticks/s) +host_mem_usage 254724 # Number of bytes of host memory used +host_seconds 1589.37 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 193856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272320 # Number of bytes read from this memory -system.physmem.bytes_read::total 466176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193856 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3029 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4255 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7284 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2836637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3984778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6821415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2836637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2836637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2836637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3984778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6821415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7284 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory +system.physmem.bytes_read::total 466432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194176 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3034 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7288 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2839868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3981806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6821674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2839868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2839868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7288 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7289 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 466176 # Total number of bytes read from memory +system.physmem.cpureqs 7293 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 466432 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 466176 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 607 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 608 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 526 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 354 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 163 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 210 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 208 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 323 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 416 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 612 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 506 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68339875000 # Total gap between requests +system.physmem.totGap 68374814000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7284 # Categorize read packet sizes +system.physmem.readPktSize::6 7288 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,62 +149,62 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 639.642957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 236.501213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1328.325684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 231 32.22% 32.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 96 13.39% 45.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 63 8.79% 54.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 56 7.81% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 30 4.18% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 30 4.18% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 16 2.23% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 21 2.93% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 1.81% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 17 2.37% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 8 1.12% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.67% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.42% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 9 1.26% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.70% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 7 0.98% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 0.70% 86.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 0.70% 87.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.56% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.28% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.56% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3 0.42% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 4 0.56% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.56% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.28% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.14% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.28% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 639.554318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 239.565124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1324.415379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 223 31.06% 31.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 101 14.07% 45.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 63 8.77% 53.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 56 7.80% 61.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 31 4.32% 66.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 32 4.46% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 16 2.23% 72.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 24 3.34% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.25% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 16 2.23% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 9 1.25% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 12 1.67% 82.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.70% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 9 1.25% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 7 0.97% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.84% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 4 0.56% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.42% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.70% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.42% 88.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.42% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.56% 89.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 5 0.70% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.56% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.42% 91.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.42% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.14% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.28% 94.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.14% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.14% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.14% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation @@ -214,15 +214,15 @@ system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 39275000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 171092500 # Sum of mem lat for all requests -system.physmem.totBusLat 36420000 # Total cycles spent in databus access -system.physmem.totBankLat 95397500 # Total cycles spent in bank access -system.physmem.avgQLat 5391.95 # Average queueing delay per request -system.physmem.avgBankLat 13096.86 # Average bank access latency per request +system.physmem.bytesPerActivate::total 718 # Bytes accessed per row activation +system.physmem.totQLat 36604250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 168483000 # Sum of mem lat for all requests +system.physmem.totBusLat 36440000 # Total cycles spent in databus access +system.physmem.totBankLat 95438750 # Total cycles spent in bank access +system.physmem.avgQLat 5022.54 # Average queueing delay per request +system.physmem.avgBankLat 13095.33 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23488.81 # Average memory access latency +system.physmem.avgMemAccLat 23117.86 # Average memory access latency system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s @@ -231,37 +231,37 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6567 # Number of row buffer hits during reads +system.physmem.readRowHits 6570 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9382190.42 # Average gap between requests -system.membus.throughput 6821415 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4461 # Transaction distribution -system.membus.trans_dist::ReadResp 4461 # Transaction distribution +system.physmem.avgGap 9381835.07 # Average gap between requests +system.membus.throughput 6821674 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4467 # Transaction distribution +system.membus.trans_dist::ReadResp 4467 # Transaction distribution system.membus.trans_dist::UpgradeReq 5 # Transaction distribution system.membus.trans_dist::UpgradeResp 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 2823 # Transaction distribution -system.membus.trans_dist::ReadExResp 2823 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 14578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 14578 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 466176 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466176 # Total data (bytes) +system.membus.trans_dist::ReadExReq 2821 # Transaction distribution +system.membus.trans_dist::ReadExResp 2821 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 14586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 14586 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 466432 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466432 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8863500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67994996 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68010245 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 35386289 # Number of BP lookups -system.cpu.branchPred.condPredicted 21204879 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1638532 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19153921 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16759106 # Number of BTB hits +system.cpu.branchPred.lookups 35388733 # Number of BP lookups +system.cpu.branchPred.condPredicted 21200896 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1644934 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19122518 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16795427 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.496999 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6781793 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8488 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.830625 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6785564 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8441 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -305,100 +305,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136680145 # number of cpu cycles simulated +system.cpu.numCycles 136750012 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38911514 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317585001 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35386289 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23540899 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70801219 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6795871 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21500027 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 100 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1484 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37522622 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 503492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136360129 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.984944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 38949353 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317676023 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35388733 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23580991 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70834954 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6803690 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21493719 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1383 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37560816 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 509146 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136426737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.984407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454366 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66188924 48.54% 48.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6771554 4.97% 53.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5692762 4.17% 57.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6083969 4.46% 62.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4907326 3.60% 65.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4077145 2.99% 68.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3184432 2.34% 71.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4135342 3.03% 74.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35318675 25.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66221739 48.54% 48.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6780898 4.97% 53.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5694782 4.17% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6088849 4.46% 62.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4909575 3.60% 65.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4088004 3.00% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3182942 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4139594 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35320354 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136360129 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258899 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.323564 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45414780 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16659439 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66663560 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2545187 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5077163 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7331349 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 68935 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401047467 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 212517 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5077163 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50947779 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1931381 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 327570 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63615860 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14460376 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393522571 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1660698 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10177766 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1066 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432139045 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2330040462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1257112117 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1072928345 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136426737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258784 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.323042 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45449120 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16657240 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66693516 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2548377 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5078484 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7335953 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69077 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401163284 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 211870 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5078484 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50979253 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1928009 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 329001 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63651330 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14460660 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393604020 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1657735 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10191603 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1257645546 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072712885 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47572852 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11802 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11801 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36468583 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103474945 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91276854 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4259608 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5261316 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384098955 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22768 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373971213 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1208914 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34303040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 86231470 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136360129 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.742526 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.023578 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11830 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36438205 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103461367 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91301104 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4273842 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5281559 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384115412 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373986631 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1200950 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34324808 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 86133615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136426737 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.741300 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023490 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24894566 18.26% 18.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19912259 14.60% 32.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20562905 15.08% 47.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18156426 13.32% 61.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24028186 17.62% 78.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15708589 11.52% 90.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8792760 6.45% 96.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3383887 2.48% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 920551 0.68% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24929928 18.27% 18.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19932793 14.61% 32.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20578448 15.08% 47.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18152288 13.31% 61.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24038629 17.62% 78.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15699021 11.51% 90.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8799073 6.45% 96.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3376437 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 920120 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136360129 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136426737 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8941 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8934 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -417,22 +417,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46063 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46301 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7630 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7704 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 463 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190949 1.08% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4204 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241086 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190616 1.07% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 3949 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241166 1.36% 2.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9286535 52.36% 55.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7946359 44.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9286471 52.35% 55.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7950501 44.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126344065 33.78% 33.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175771 0.58% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126356667 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175742 0.58% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued @@ -451,93 +451,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6778681 1.81% 36.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6779199 1.81% 36.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8473226 2.27% 38.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3428816 0.92% 39.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595959 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20861053 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172627 1.92% 47.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127553 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8471128 2.27% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3427474 0.92% 39.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595849 0.43% 39.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20859409 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172834 1.92% 47.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127502 1.91% 49.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101561380 27.16% 76.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88276793 23.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101548323 27.15% 76.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88297215 23.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373971213 # Type of FU issued -system.cpu.iq.rate 2.736105 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17736902 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047429 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653872242 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288125780 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249960786 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249376129 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130313231 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118044740 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263109864 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128598251 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11095244 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373986631 # Type of FU issued +system.cpu.iq.rate 2.734820 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17740799 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047437 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653979183 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 288208067 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249975124 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249362565 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130269118 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118046236 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263130568 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128596862 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11091317 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8826197 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 108953 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14410 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8901271 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8812619 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109039 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14268 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8925521 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 178209 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1806 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 177200 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1779 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5077163 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 281172 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384123288 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 853132 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103474945 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91276854 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11734 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 343 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 352 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14410 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1275078 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 370888 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1645966 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370028321 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100269572 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3942892 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5078484 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 284505 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35417 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384139745 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 871852 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103461367 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91301104 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 311 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 371 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14268 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1284870 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 366093 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1650963 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370046005 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100262370 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3940626 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1565 # number of nop insts executed -system.cpu.iew.exec_refs 187470029 # number of memory reference insts executed -system.cpu.iew.exec_branches 32001457 # Number of branches executed -system.cpu.iew.exec_stores 87200457 # Number of stores executed -system.cpu.iew.exec_rate 2.707257 # Inst execution rate -system.cpu.iew.wb_sent 368660932 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368005526 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182984682 # num instructions producing a value -system.cpu.iew.wb_consumers 363667286 # num instructions consuming a value +system.cpu.iew.exec_nop 1545 # number of nop insts executed +system.cpu.iew.exec_refs 187486507 # number of memory reference insts executed +system.cpu.iew.exec_branches 32007235 # Number of branches executed +system.cpu.iew.exec_stores 87224137 # Number of stores executed +system.cpu.iew.exec_rate 2.706003 # Inst execution rate +system.cpu.iew.wb_sent 368676629 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368021360 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182960102 # num instructions producing a value +system.cpu.iew.wb_consumers 363631500 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.692458 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503165 # average fanout of values written-back +system.cpu.iew.wb_rate 2.691198 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503147 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35058333 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35074746 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1569963 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131282966 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.658875 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659705 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1576251 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131348253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.657554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659541 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34515611 26.29% 26.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28430867 21.66% 47.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13310132 10.14% 58.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11454615 8.73% 66.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13758236 10.48% 77.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7411224 5.65% 82.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3878786 2.95% 85.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3899655 2.97% 88.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14623840 11.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34568937 26.32% 26.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28443468 21.66% 47.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13309150 10.13% 58.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11454276 8.72% 66.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13766870 10.48% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7405227 5.64% 82.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3876233 2.95% 85.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3903284 2.97% 88.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14620808 11.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131282966 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131348253 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -548,220 +548,220 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14623840 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14620808 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 500779997 # The number of ROB reads -system.cpu.rob.rob_writes 773327958 # The number of ROB writes -system.cpu.timesIdled 6728 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320016 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 500864729 # The number of ROB reads +system.cpu.rob.rob_writes 773362160 # The number of ROB writes +system.cpu.timesIdled 6666 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 323275 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.500593 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.500593 # CPI: Total CPI of All Threads -system.cpu.ipc 1.997633 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.997633 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1768864956 # number of integer regfile reads -system.cpu.int_regfile_writes 232856502 # number of integer regfile writes -system.cpu.fp_regfile_reads 188105910 # number of floating regfile reads -system.cpu.fp_regfile_writes 132495512 # number of floating regfile writes -system.cpu.misc_regfile_reads 566780330 # number of misc regfile reads +system.cpu.cpi 0.500848 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500848 # CPI: Total CPI of All Threads +system.cpu.ipc 1.996612 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.996612 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1768925077 # number of integer regfile reads +system.cpu.int_regfile_writes 232843327 # number of integer regfile writes +system.cpu.fp_regfile_reads 188113453 # number of floating regfile reads +system.cpu.fp_regfile_writes 132483580 # number of floating regfile writes +system.cpu.misc_regfile_reads 566770577 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20129917 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17615 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17615 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1040 # Transaction distribution +system.cpu.toL2Bus.throughput 20110273 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1037 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2840 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 41952 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 1375168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1375168 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 512 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11790000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 41937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 1374656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1374656 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 384 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11782000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23771988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24379238 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6938461 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7509966 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 13951 # number of replacements -system.cpu.icache.tagsinuse 1844.969918 # Cycle average of tags in use -system.cpu.icache.total_refs 37505309 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15840 # 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Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902587 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902587 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37543488 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37543488 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37543488 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37543488 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37543488 # number of overall hits +system.cpu.icache.overall_hits::total 37543488 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17326 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17326 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17326 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17326 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17326 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25312.084628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25312.084628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25312.084628 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 919 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25393.194275 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25393.194275 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25393.194275 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25393.194275 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 913 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 350210509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350210509 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 350210509 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1486 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1486 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1486 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1486 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1486 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1486 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15840 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15840 # 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Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5388 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.448033 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 380.401816 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2774.612860 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 780.466052 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011609 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.084674 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.023818 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.120101 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12795 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 300 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67578.034009 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67550.109007 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -779,168 +779,168 @@ system.cpu.l2cache.demand_mshr_hits::total 51 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1432 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4461 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 403541500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168121750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235419750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 403541500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808583 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253365 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2821 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2821 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3034 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4254 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 166700500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 234729250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 401429750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 166700500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 234729250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 401429750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253749 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55504.044239 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56894.203911 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55950.291414 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10300.800000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10300.800000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54533.209352 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54533.209352 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994010 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994010 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356521 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356521 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54944.133158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56670.272156 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55497.873293 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10201 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10201 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54420.684155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54420.684155 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55080.920692 # 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Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3101.863625 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757291 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757291 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88809743 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88809743 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031242 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031242 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11022 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11022 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170843715 # 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number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21423 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21423 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25434 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25434 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25434 # number of overall misses -system.cpu.dcache.overall_misses::total 25434 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 218203000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 218203000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1190820596 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1190820596 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 155000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1409023596 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1409023596 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1409023596 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1409023596 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88816484 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88816484 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25385 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25385 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25385 # number of overall misses +system.cpu.dcache.overall_misses::total 25385 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 221925207 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 221925207 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1196433403 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1196433403 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 157000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1418358610 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1418358610 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1418358610 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1418358610 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88813705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88813705 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11014 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11014 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11024 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170869149 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170869149 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170869149 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170869149 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170866370 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170866370 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170866370 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170866370 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000149 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54619.023780 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54619.023780 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55544.596110 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55544.596110 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55399.213494 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55399.213494 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24937 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1182 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 461 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.093275 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 90.923077 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56013.429329 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56013.429329 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55848.079307 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55848.079307 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55873.886547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55873.886547 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25209 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1225 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 407 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.938575 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 102.083333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks -system.cpu.dcache.writebacks::total 1040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2223 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2223 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18595 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18595 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1037 # number of writebacks +system.cpu.dcache.writebacks::total 1037 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2191 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2191 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18581 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18581 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20818 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20818 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20818 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20818 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1772 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1772 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2844 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2844 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106478039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 106478039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191753000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 191753000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298231039 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298231039 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298231039 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298231039 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20772 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20772 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20772 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20772 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4613 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4613 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4613 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4613 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106433039 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 106433039 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191658495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 191658495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298091534 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298091534 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298091534 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298091534 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -949,14 +949,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60089.186795 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60089.186795 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67423.699015 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67423.699015 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60097.706945 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60097.706945 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67437.894089 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67437.894089 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 03f82082e..e8172a215 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1051668684 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 13796 # number of replacements -system.cpu.icache.tagsinuse 1765.993223 # Cycle average of tags in use -system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13796 # number of replacements +system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3487.723791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.106437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1332 # number of replacements -system.cpu.dcache.tagsinuse 3078.412981 # Cycle average of tags in use -system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1332 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index c480587dc..fb55fbe0e 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.631301 # Number of seconds simulated -sim_ticks 631300530000 # Number of ticks simulated -final_tick 631300530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.631883 # Number of seconds simulated +sim_ticks 631883288500 # Number of ticks simulated +final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153163 # Simulator instruction rate (inst/s) -host_op_rate 153163 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53038574 # Simulator tick rate (ticks/s) -host_mem_usage 237176 # Number of bytes of host memory used -host_seconds 11902.67 # Real time elapsed on the host +host_inst_rate 129491 # Simulator instruction rate (inst/s) +host_op_rate 129491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44882876 # Simulator tick rate (ticks/s) +host_mem_usage 237188 # Number of bytes of host memory used +host_seconds 14078.49 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295296 # Number of bytes read from this memory -system.physmem.bytes_read::total 30472576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295168 # Number of bytes read from this memory +system.physmem.bytes_read::total 30471232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473364 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473362 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476113 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 280817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47988707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48269524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 280817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 280817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6783001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6783001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6783001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 280817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47988707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55052525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476134 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 278634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47944246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48222880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 278634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 278634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6776745 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6776745 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6776745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 278634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47944246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54999625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476114 # Total number of read requests seen system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543042 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30472576 # Total number of bytes read from memory +system.physmem.cpureqs 543022 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30471232 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30472576 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30471232 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 95 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29446 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29790 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29772 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29865 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29863 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29774 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29887 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 29447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29852 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29890 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 29849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29585 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29633 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29915 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29796 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29583 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29509 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29637 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4125 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4164 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4223 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4096 # Tr system.physmem.perBankWrReqs::15 4157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 631300447500 # Total gap between requests +system.physmem.totGap 631883258500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476134 # Categorize read packet sizes +system.physmem.readPktSize::6 476114 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 66908 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 408382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 408378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -156,40 +156,40 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 166615 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 208.530564 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.079554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 536.352711 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 52781 31.68% 31.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 42583 25.56% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39981 24.00% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 25354 15.22% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 274 0.16% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 129 0.08% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 97 0.06% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 83 0.05% 96.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 81 0.05% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 95 0.06% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 108 0.06% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 114 0.07% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 86 0.05% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 166584 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 208.562071 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.103843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 536.299000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 52740 31.66% 31.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 42613 25.58% 57.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 39946 23.98% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 25368 15.23% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 277 0.17% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 122 0.07% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 95 0.06% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 87 0.05% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 83 0.05% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 94 0.06% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 111 0.07% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 115 0.07% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 83 0.05% 97.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-897 90 0.05% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 79 0.05% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 79 0.05% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 75 0.05% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 77 0.05% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 81 0.05% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 76 0.05% 97.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 77 0.05% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 76 0.05% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 74 0.04% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 77 0.05% 97.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 81 0.05% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 82 0.05% 97.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::1472-1473 3443 2.07% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536-1537 36 0.02% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::1600-1601 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.00% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1857 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 3 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240-2241 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.61% # Bytes accessed per row activation @@ -197,11 +197,12 @@ system.physmem.bytesPerActivate::2432-2433 2 0.00% 99.61% # system.physmem.bytesPerActivate::2560-2561 3 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2688-2689 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::3392-3393 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.62% # Bytes accessed per row activation @@ -209,7 +210,7 @@ system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.62% # system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.63% # Bytes accessed per row activation @@ -233,73 +234,73 @@ system.physmem.bytesPerActivate::8000-8001 4 0.00% 99.65% # system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 1 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 586 0.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 166615 # Bytes accessed per row activation -system.physmem.totQLat 1512536000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14445141000 # Sum of mem lat for all requests -system.physmem.totBusLat 2380195000 # Total cycles spent in databus access -system.physmem.totBankLat 10552410000 # Total cycles spent in bank access -system.physmem.avgQLat 3177.34 # Average queueing delay per request -system.physmem.avgBankLat 22167.11 # Average bank access latency per request +system.physmem.bytesPerActivate::total 166584 # Bytes accessed per row activation +system.physmem.totQLat 1351239750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14292404750 # Sum of mem lat for all requests +system.physmem.totBusLat 2380120000 # Total cycles spent in databus access +system.physmem.totBankLat 10561045000 # Total cycles spent in bank access +system.physmem.avgQLat 2838.60 # Average queueing delay per request +system.physmem.avgBankLat 22185.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30344.45 # Average memory access latency -system.physmem.avgRdBW 48.27 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 30024.55 # Average memory access latency +system.physmem.avgRdBW 48.22 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.22 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.78 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.99 # Average write queue length over time +system.physmem.avgWrQLen 11.01 # Average write queue length over time system.physmem.readRowHits 326147 # Number of row buffer hits during reads -system.physmem.writeRowHits 50184 # Number of row buffer hits during writes +system.physmem.writeRowHits 50200 # Number of row buffer hits during writes system.physmem.readRowHitRate 68.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.00 # Row buffer hit rate for writes -system.physmem.avgGap 1162526.01 # Average gap between requests -system.membus.throughput 55052525 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409284 # Transaction distribution -system.membus.trans_dist::ReadResp 409284 # Transaction distribution +system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes +system.physmem.avgGap 1163642.10 # Average gap between requests +system.membus.throughput 54999625 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409258 # Transaction distribution +system.membus.trans_dist::ReadResp 409257 # Transaction distribution system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66850 # Transaction distribution -system.membus.trans_dist::ReadExResp 66850 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1019176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1019176 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34754688 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 34754688 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34754688 # Total data (bytes) +system.membus.trans_dist::ReadExReq 66856 # Transaction distribution +system.membus.trans_dist::ReadExResp 66856 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 1019135 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1019135 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34753344 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 34753344 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34753344 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1238262500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1232718500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4532735250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4527448500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 388673605 # Number of BP lookups -system.cpu.branchPred.condPredicted 255878326 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25733265 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 278525299 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258256723 # Number of BTB hits +system.cpu.branchPred.lookups 388901077 # Number of BP lookups +system.cpu.branchPred.condPredicted 255997466 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25785874 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 315302493 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258353491 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.722896 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57195432 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6738 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.938296 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57247417 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6895 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 521844087 # DTB read hits -system.cpu.dtb.read_misses 593644 # DTB read misses +system.cpu.dtb.read_hits 522159380 # DTB read hits +system.cpu.dtb.read_misses 590851 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 522437731 # DTB read accesses -system.cpu.dtb.write_hits 282954606 # DTB write hits -system.cpu.dtb.write_misses 50165 # DTB write misses +system.cpu.dtb.read_accesses 522750231 # DTB read accesses +system.cpu.dtb.write_hits 283002528 # DTB write hits +system.cpu.dtb.write_misses 50162 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283004771 # DTB write accesses -system.cpu.dtb.data_hits 804798693 # DTB hits -system.cpu.dtb.data_misses 643809 # DTB misses +system.cpu.dtb.write_accesses 283052690 # DTB write accesses +system.cpu.dtb.data_hits 805161908 # DTB hits +system.cpu.dtb.data_misses 641013 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 805442502 # DTB accesses -system.cpu.itb.fetch_hits 394528514 # ITB hits -system.cpu.itb.fetch_misses 534 # ITB misses +system.cpu.dtb.data_accesses 805802921 # DTB accesses +system.cpu.itb.fetch_hits 394748041 # ITB hits +system.cpu.itb.fetch_misses 630 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394529048 # ITB accesses +system.cpu.itb.fetch_accesses 394748671 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -313,238 +314,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1262601061 # number of cpu cycles simulated +system.cpu.numCycles 1263766578 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 409498007 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3272810217 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388673605 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315452155 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 629699645 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157846800 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75851008 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 147 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7336 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394528514 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11392908 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1246680714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.625219 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.138755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 409917284 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3274493634 # Number of instructions fetch has processed +system.cpu.fetch.Branches 388901077 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315600908 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630100236 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157853545 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75868728 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6965 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 394748041 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11243258 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1247472116 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.624903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.139302 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 616981069 49.49% 49.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57198279 4.59% 54.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43039078 3.45% 57.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71977388 5.77% 63.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129322230 10.37% 73.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46258105 3.71% 77.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41218514 3.31% 80.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7777319 0.62% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 232908732 18.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 617371880 49.49% 49.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57447684 4.61% 54.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43286408 3.47% 57.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71838123 5.76% 63.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129156368 10.35% 73.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46178870 3.70% 77.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41219816 3.30% 80.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7663689 0.61% 81.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233309278 18.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1246680714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307836 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.592117 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 437789893 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62140482 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 606005534 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9132317 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131612488 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31510475 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12424 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3192799837 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46361 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131612488 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467284900 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27231873 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27253 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 585294370 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35229830 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3093290625 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 1247472116 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307732 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.591059 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438201536 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62209215 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 606414230 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9080438 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131566697 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31709739 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12402 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3193700667 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46294 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131566697 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467502237 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27351671 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28189 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 585846018 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35177304 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3094945067 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14758 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28928557 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2053350484 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3577730264 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3457415406 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120314858 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 15191 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28875434 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2054257390 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3579193509 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3458491340 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120702169 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 668381414 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4231 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109772702 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 743605283 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351355021 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 69106055 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8779755 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2622263880 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2159577480 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17944946 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 799158217 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 726204094 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1246680714 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.732262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.802997 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 669288320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4234 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109722880 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 743716097 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351305913 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 69009362 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8819654 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2623113984 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 93 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2159995607 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17916537 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 800006156 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 726205656 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 54 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1247472116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.731498 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803359 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 450451444 36.13% 36.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196386892 15.75% 51.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251435205 20.17% 72.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120817476 9.69% 81.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104827933 8.41% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79080340 6.34% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24383702 1.96% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17529670 1.41% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1768052 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 450995748 36.15% 36.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 196797874 15.78% 51.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251286832 20.14% 72.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120757727 9.68% 81.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104717605 8.39% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79196335 6.35% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24309118 1.95% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17642931 1.41% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1767946 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1246680714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1247472116 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146168 3.12% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25530327 69.57% 72.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10022787 27.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146304 3.11% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25641829 69.66% 72.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10023004 27.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1233812197 57.13% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851163 1.29% 58.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254698 0.38% 58.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204652 0.33% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589396274 27.29% 86.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293038648 13.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234267096 57.14% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17095 0.00% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851364 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204649 0.33% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589311123 27.28% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293086828 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2159577480 # Type of FU issued -system.cpu.iq.rate 1.710420 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36699282 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016994 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5469378913 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3334207188 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1989129090 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151100989 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 87288283 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73609749 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2118824418 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449592 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62141857 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2159995607 # Type of FU issued +system.cpu.iq.rate 1.709173 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36811137 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017042 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5471089482 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3335131409 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1989836434 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101522 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88062076 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73609987 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2119354134 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77449858 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62153092 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 232535257 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18630 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 75784 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140560125 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 232646071 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 31940 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75814 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140511017 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4408 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2802 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4421 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2886 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131612488 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13139012 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 539946 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2986122932 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 725503 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 743605283 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351355021 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 196101 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1503 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 75784 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25727396 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 27151 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25754547 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2065136857 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 522437892 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94440623 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131566697 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13318869 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540046 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2986589244 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 731786 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 743716097 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351305913 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 93 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 134266 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1522 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 75814 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25780444 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 27789 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25808233 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2065907774 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 522750367 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94087833 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363858964 # number of nop insts executed -system.cpu.iew.exec_refs 805443124 # number of memory reference insts executed -system.cpu.iew.exec_branches 277347977 # Number of branches executed -system.cpu.iew.exec_stores 283005232 # Number of stores executed -system.cpu.iew.exec_rate 1.635621 # Inst execution rate -system.cpu.iew.wb_sent 2065019944 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2062738839 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1180752690 # num instructions producing a value -system.cpu.iew.wb_consumers 1753366082 # num instructions consuming a value +system.cpu.iew.exec_nop 363475167 # number of nop insts executed +system.cpu.iew.exec_refs 805803501 # number of memory reference insts executed +system.cpu.iew.exec_branches 277598296 # Number of branches executed +system.cpu.iew.exec_stores 283053134 # Number of stores executed +system.cpu.iew.exec_rate 1.634723 # Inst execution rate +system.cpu.iew.wb_sent 2065776472 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2063446421 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1180901001 # num instructions producing a value +system.cpu.iew.wb_consumers 1753223374 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.633722 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673421 # average fanout of values written-back +system.cpu.iew.wb_rate 1.632775 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673560 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 960178624 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 960640976 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25721232 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1115068226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.801672 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.508434 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25773841 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1115905419 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.800321 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.507651 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 496151769 44.50% 44.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228465229 20.49% 64.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119927421 10.76% 75.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58951874 5.29% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50411669 4.52% 85.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24161138 2.17% 87.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19007626 1.70% 89.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16618211 1.49% 90.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101373289 9.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 496848865 44.52% 44.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228666687 20.49% 65.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119877587 10.74% 75.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58838951 5.27% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50501288 4.53% 85.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24162159 2.17% 87.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19119877 1.71% 89.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16606359 1.49% 90.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101283646 9.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1115068226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1115905419 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,212 +556,212 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101373289 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101283646 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3977224755 # The number of ROB reads -system.cpu.rob.rob_writes 6069947076 # The number of ROB writes -system.cpu.timesIdled 341189 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15920347 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3978613943 # The number of ROB reads +system.cpu.rob.rob_writes 6070825883 # The number of ROB writes +system.cpu.timesIdled 341889 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16294462 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.692579 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692579 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443879 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443879 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2627113034 # number of integer regfile reads -system.cpu.int_regfile_writes 1496009216 # number of integer regfile writes -system.cpu.fp_regfile_reads 78810922 # number of floating regfile reads -system.cpu.fp_regfile_writes 52660839 # number of floating regfile writes +system.cpu.cpi 0.693218 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.693218 # CPI: Total CPI of All Threads +system.cpu.ipc 1.442548 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.442548 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2627733458 # number of integer regfile reads +system.cpu.int_regfile_writes 1496469824 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811377 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661114 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 166051525 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71638 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 20109 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3159809 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3179918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 643456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104184960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 104828416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104828416 # Total data (bytes) +system.cpu.toL2Bus.throughput 165896459 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1470295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1470294 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 71645 # 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number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 381722499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 381722499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 381722499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 381722499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394748041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394748041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394748041 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394748041 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394748041 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394748041 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29585.096412 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29585.096412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29585.096412 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29585.096412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29585.096412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29585.096412 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 820 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29513.104917 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29513.104917 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29513.104917 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29513.104917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29513.104917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29513.104917 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 646 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 443356 # number of replacements -system.cpu.l2cache.tagsinuse 32690.931292 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1090076 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 476092 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.289633 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1331.519382 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 35.398256 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31324.013654 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.040635 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001080 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.955933 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997648 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7284 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1053767 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1061051 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 95971 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 95971 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58975.018169 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58975.018169 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527823 # number of replacements -system.cpu.dcache.tagsinuse 4094.615904 # Cycle average of tags in use -system.cpu.dcache.total_refs 667502438 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531919 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 435.729590 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 397277000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.615904 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999662 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 457769415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 457769415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733001 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733001 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 667502416 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 75679638000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 75679638000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 45101799853 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45101799853 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 133500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 133500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 120781437853 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 120781437853 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 120781437853 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 120781437853 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 459695189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 459695189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 1527799 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.613876 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 667806397 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1531895 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 435.934837 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 399882250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.613876 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999662 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 458073360 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458073360 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209733012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209733012 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 25 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 25 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 667806372 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 667806372 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 667806372 # number of overall hits +system.cpu.dcache.overall_hits::total 667806372 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925786 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925786 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061884 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061884 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2987670 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987670 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987670 # number of overall misses +system.cpu.dcache.overall_misses::total 2987670 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76327323000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76327323000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 44999711104 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 44999711104 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121327034104 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121327034104 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121327034104 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121327034104 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 459999146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 459999146 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 670490085 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 670490085 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 670490085 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 670490085 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004189 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 25 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 25 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 670794042 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 670794042 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 670794042 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 670794042 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004186 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004186 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.083333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.083333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004456 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004456 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004456 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004456 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39298.296685 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39298.296685 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42472.937393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42472.937393 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40426.646276 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40426.646276 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40426.646276 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40426.646276 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17832 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 107 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 375 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.004454 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004454 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004454 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004454 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39634.374224 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39634.374224 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42377.238101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42377.238101 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40609.248714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40609.248714 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18768 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.552000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 107 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.086455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks -system.cpu.dcache.writebacks::total 95971 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465494 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465494 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990257 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990257 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455751 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455751 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455751 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455751 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460280 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460280 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71638 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71638 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531918 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531918 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531918 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41822016500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41822016500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5130364000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130364000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46952380500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46952380500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46952380500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46952380500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003177 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003177 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 95986 # number of writebacks +system.cpu.dcache.writebacks::total 95986 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465536 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465536 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990239 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990239 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455775 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455775 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455775 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455775 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460250 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460250 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71645 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71645 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531895 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531895 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531895 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531895 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41766827000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41766827000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5159100250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5159100250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46925927250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46925927250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46925927250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46925927250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003174 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003174 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002285 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002285 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002285 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002285 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28639.724231 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28639.724231 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71615.120467 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71615.120467 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30649.408454 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30649.408454 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30649.408454 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30649.408454 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28602.518062 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28602.518062 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72009.215577 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72009.215577 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 217f3cee7..3b39f56f2 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 5539479066 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.418050 # Cycle average of tags in use -system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 9046 # number of replacements +system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 442570 # number of replacements -system.cpu.l2cache.tagsinuse 32706.854192 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1089464 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 475302 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.292151 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 442570 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use -system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1526048 # number of replacements +system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 54c03f73f..68bfe2c31 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.629145 # Number of seconds simulated -sim_ticks 629144850500 # Number of ticks simulated -final_tick 629144850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.640648 # Number of seconds simulated +sim_ticks 640648369500 # Number of ticks simulated +final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104232 # Simulator instruction rate (inst/s) -host_op_rate 141949 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47369420 # Simulator tick rate (ticks/s) -host_mem_usage 254336 # Number of bytes of host memory used -host_seconds 13281.67 # Real time elapsed on the host +host_inst_rate 99606 # Simulator instruction rate (inst/s) +host_op_rate 135651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46095119 # Simulator tick rate (ticks/s) +host_mem_usage 254320 # Number of bytes of host memory used +host_seconds 13898.40 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 155072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30241984 # Number of bytes read from this memory -system.physmem.bytes_read::total 30397056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155072 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory +system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2423 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472531 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472560 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 246481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48068396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48314877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 246481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6723844 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6723844 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6723844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 246481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48068396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55038721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474954 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 242954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47208174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47451128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474992 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30397056 # Total number of bytes read from memory +system.physmem.cpureqs 545451 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30399488 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30397056 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 163 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4296 # Reqs where no action is needed +system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29740 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29705 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29439 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29490 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29807 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29795 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29538 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29815 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29804 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4096 # Tr system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 629144781500 # Total gap between requests +system.physmem.totGap 640648293500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 474954 # Categorize read packet sizes +system.physmem.readPktSize::6 474992 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,12 +92,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 66098 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407729 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -156,49 +156,47 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 173211 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 199.837655 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.549683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 508.405937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 59600 34.41% 34.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 42691 24.65% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39909 23.04% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 25367 14.65% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 276 0.16% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 104 0.06% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 98 0.06% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 91 0.05% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 88 0.05% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 83 0.05% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 78 0.05% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 81 0.05% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 73 0.04% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 74 0.04% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 79 0.05% 97.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 80 0.05% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 173268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 199.789644 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.514067 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 508.333416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 59669 34.44% 34.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 42666 24.62% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 39942 23.05% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 25325 14.62% 96.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 291 0.17% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 110 0.06% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 103 0.06% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 89 0.05% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 94 0.05% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 79 0.05% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 78 0.05% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 80 0.05% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 70 0.04% 97.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 76 0.04% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 80 0.05% 97.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 77 0.04% 97.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 80 0.05% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 73 0.04% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 73 0.04% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3309 1.91% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 4 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 81 0.05% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 72 0.04% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 72 0.04% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3310 1.91% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 3 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 4 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 3 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation @@ -209,62 +207,62 @@ system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 173211 # Bytes accessed per row activation -system.physmem.totQLat 2060605250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15116660250 # Sum of mem lat for all requests -system.physmem.totBusLat 2373955000 # Total cycles spent in databus access -system.physmem.totBankLat 10682100000 # Total cycles spent in bank access -system.physmem.avgQLat 4340.03 # Average queueing delay per request -system.physmem.avgBankLat 22498.53 # Average bank access latency per request +system.physmem.bytesPerActivate::total 173268 # Bytes accessed per row activation +system.physmem.totQLat 1888421000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14966831000 # Sum of mem lat for all requests +system.physmem.totBusLat 2374200000 # Total cycles spent in databus access +system.physmem.totBankLat 10704210000 # Total cycles spent in bank access +system.physmem.avgQLat 3976.96 # Average queueing delay per request +system.physmem.avgBankLat 22542.77 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31838.56 # Average memory access latency -system.physmem.avgRdBW 48.31 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.31 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.72 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31519.74 # Average memory access latency +system.physmem.avgRdBW 47.45 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.60 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.45 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.60 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.43 # Data bus utilization in percentage +system.physmem.busUtil 0.42 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 17.41 # Average write queue length over time -system.physmem.readRowHits 318020 # Number of row buffer hits during reads -system.physmem.writeRowHits 49639 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.10 # Row buffer hit rate for writes -system.physmem.avgGap 1162817.59 # Average gap between requests -system.membus.throughput 55038619 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408879 # Transaction distribution -system.membus.trans_dist::ReadResp 408878 # Transaction distribution +system.physmem.avgWrQLen 17.45 # Average write queue length over time +system.physmem.readRowHits 318007 # Number of row buffer hits during reads +system.physmem.writeRowHits 49644 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes +system.physmem.avgGap 1183995.81 # Average gap between requests +system.membus.throughput 54054139 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408917 # Transaction distribution +system.membus.trans_dist::ReadResp 408916 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4296 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4296 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution system.membus.trans_dist::ReadExReq 66075 # Transaction distribution system.membus.trans_dist::ReadExResp 66075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1024597 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1024597 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34627264 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 34627264 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34627264 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 1024803 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1024803 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34629696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 34629696 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34629696 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206768500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4481136954 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 441633744 # Number of BP lookups -system.cpu.branchPred.condPredicted 353245820 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30626910 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 253291175 # Number of BTB lookups -system.cpu.branchPred.BTBHits 229518524 # Number of BTB hits +system.cpu.branchPred.lookups 451070712 # Number of BP lookups +system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 31575662 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 266989928 # Number of BTB lookups +system.cpu.branchPred.BTBHits 238695746 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.614497 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52707299 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806413 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.402528 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 53258278 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806364 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -308,238 +306,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1258289702 # number of cpu cycles simulated +system.cpu.numCycles 1281296740 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 355059035 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2281679265 # Number of instructions fetch has processed -system.cpu.fetch.Branches 441633744 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 282225823 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 601500993 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 156584245 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133257591 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11034 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 167 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 335655020 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11657170 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1215734936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.578441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176596 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 365834433 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2312845521 # Number of instructions fetch has processed +system.cpu.fetch.Branches 451070712 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 291954024 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 613483563 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 162414515 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 128244265 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11411 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 346004157 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12181247 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1238361342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.567207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.166964 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614278728 50.53% 50.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43031217 3.54% 54.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 96058050 7.90% 61.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55653458 4.58% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 73683625 6.06% 72.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 43835223 3.61% 76.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31015132 2.55% 78.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 32844314 2.70% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 225335189 18.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 624922537 50.46% 50.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43984122 3.55% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 100783073 8.14% 62.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 58015364 4.68% 66.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 73986941 5.97% 72.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44117238 3.56% 76.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31886448 2.57% 78.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33644071 2.72% 81.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 227021548 18.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1215734936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.350979 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.813318 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 405408112 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105525155 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 562197495 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16710779 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 125893395 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 45735070 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12243 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3027450313 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 24999 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 125893395 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 441381944 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37599884 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 466637 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540742593 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 69650483 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2947282074 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 91 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4813438 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54199144 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2931640163 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14025190740 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13455020985 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 570169755 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1238361342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.352042 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.805082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 416001710 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101876756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 574960463 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 14748325 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 130774088 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46845433 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13115 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3066767432 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27354 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 130774088 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 450873553 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37362667 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 459915 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 552824643 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 66066476 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2984722482 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 106 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4345913 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 52259250 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13600947598 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 607723883 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 938500073 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 22029 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19516 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 179002715 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 971623898 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 487434291 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36825257 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 41359268 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2792194659 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28248 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2432796766 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13281338 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 894337134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2316040320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6864 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1215734936 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.001091 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18729 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 172024073 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 975055963 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 496398991 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36275443 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40590257 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2826416078 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28152 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2457324643 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 15915709 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 928556403 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2380098621 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6768 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1238361342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.984336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.868331 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 379743334 31.24% 31.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183587297 15.10% 46.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204204940 16.80% 63.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169567149 13.95% 77.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132821991 10.93% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92473374 7.61% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37933065 3.12% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12385370 1.02% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3018416 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 394006079 31.82% 31.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183256590 14.80% 46.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 205523874 16.60% 63.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 174394872 14.08% 77.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 137878376 11.13% 88.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 90899666 7.34% 95.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 36275985 2.93% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12839255 1.04% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3286645 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1215734936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1238361342 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 717080 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24380 0.03% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55165781 62.93% 63.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31749638 36.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 691696 0.78% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24382 0.03% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55024342 62.24% 63.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 32666949 36.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1103940359 45.38% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11224025 0.46% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502268 0.23% 46.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23395329 0.96% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838660213 34.47% 81.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 441822804 18.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1118619814 45.52% 45.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223087 0.46% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 46.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5501669 0.22% 46.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23389012 0.95% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 843037947 34.31% 81.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 447301347 18.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2432796766 # Type of FU issued -system.cpu.iq.rate 1.933415 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87656879 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036031 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6059775624 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3603986878 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2248220965 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122491061 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82640163 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56428970 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2457145320 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63308325 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84445856 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2457324643 # Type of FU issued +system.cpu.iq.rate 1.917842 # Inst issue rate +system.cpu.iq.fu_busy_cnt 88407369 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035977 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6133604202 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3666175191 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2269813505 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 123729504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88892403 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56421926 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2481804628 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63927384 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 85672552 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 340236717 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429873 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 210438994 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 343668782 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 27729 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1429255 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 219403694 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 345 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 304 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 125893395 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15644195 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1562618 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2792235356 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1396921 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 971623898 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 487434291 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18262 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1558827 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2523 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429873 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32450935 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1518228 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33969163 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2357455643 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792848546 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 75341123 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 130774088 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 15649984 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1558990 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2826456693 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 641968 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 975055963 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 496398991 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18166 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1553675 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1429255 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 33789507 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2118647 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 35908154 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2378923796 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 796860173 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 78400847 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12449 # number of nop insts executed -system.cpu.iew.exec_refs 1216025241 # number of memory reference insts executed -system.cpu.iew.exec_branches 319732380 # Number of branches executed -system.cpu.iew.exec_stores 423176695 # Number of stores executed -system.cpu.iew.exec_rate 1.873540 # Inst execution rate -system.cpu.iew.wb_sent 2330413186 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2304649935 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347862197 # num instructions producing a value -system.cpu.iew.wb_consumers 2523443205 # num instructions consuming a value +system.cpu.iew.exec_nop 12463 # number of nop insts executed +system.cpu.iew.exec_refs 1223764024 # number of memory reference insts executed +system.cpu.iew.exec_branches 324680497 # Number of branches executed +system.cpu.iew.exec_stores 426903851 # Number of stores executed +system.cpu.iew.exec_rate 1.856653 # Inst execution rate +system.cpu.iew.wb_sent 2351973532 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2326235431 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1354756756 # num instructions producing a value +system.cpu.iew.wb_consumers 2530303455 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.831573 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534136 # average fanout of values written-back +system.cpu.iew.wb_rate 1.815532 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535413 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 906899118 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 941120455 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30614902 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1089841541 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.729918 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.397219 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 31562826 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1107587254 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.702201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.378361 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 449517068 41.25% 41.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288638854 26.48% 67.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95107207 8.73% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70204085 6.44% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46459856 4.26% 87.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22200640 2.04% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15848625 1.45% 90.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10985187 1.01% 91.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90880019 8.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 463154673 41.82% 41.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 291887882 26.35% 68.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 96478924 8.71% 76.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70059146 6.33% 83.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46846853 4.23% 87.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22330225 2.02% 89.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15798039 1.43% 90.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11765677 1.06% 91.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89265835 8.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1089841541 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1107587254 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -550,222 +549,222 @@ system.cpu.commit.branches 298259106 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90880019 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89265835 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3791178653 # The number of ROB reads -system.cpu.rob.rob_writes 5710375191 # The number of ROB writes -system.cpu.timesIdled 353026 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42554766 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3844759887 # The number of ROB reads +system.cpu.rob.rob_writes 5783698867 # The number of ROB writes +system.cpu.timesIdled 353367 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42935398 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.908925 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.908925 # CPI: Total CPI of All Threads -system.cpu.ipc 1.100200 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.100200 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11755248902 # number of integer regfile reads -system.cpu.int_regfile_writes 2218571084 # number of integer regfile writes -system.cpu.fp_regfile_reads 68795959 # number of floating regfile reads -system.cpu.fp_regfile_writes 49541079 # number of floating regfile writes -system.cpu.misc_regfile_reads 1363718123 # number of misc regfile reads +system.cpu.cpi 0.925545 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.925545 # CPI: Total CPI of All Threads +system.cpu.ipc 1.080445 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.080445 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11851555490 # number of integer regfile reads +system.cpu.int_regfile_writes 2239006966 # number of integer regfile writes +system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads +system.cpu.fp_regfile_writes 49533000 # number of floating regfile writes +system.cpu.misc_regfile_reads 1371543913 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 169026080 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1492742 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1492741 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72516 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72516 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52382 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178768 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3231150 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1538688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104528128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 106066816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106066816 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 275072 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 929281000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52387 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3231222 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1536768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104525120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 106061888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 42510998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2307535978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.replacements 22361 # number of replacements -system.cpu.icache.tagsinuse 1639.588858 # Cycle average of tags in use -system.cpu.icache.total_refs 335620121 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24041 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13960.322824 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1639.588858 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.800580 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.800580 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 335624135 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 335624135 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 335624135 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 335624135 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 335624135 # number of overall hits -system.cpu.icache.overall_hits::total 335624135 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30883 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30883 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30883 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30883 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30883 # number of overall misses -system.cpu.icache.overall_misses::total 30883 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 525457997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 525457997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 525457997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 525457997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 525457997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 525457997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 335655018 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 335655018 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 335655018 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 335655018 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 335655018 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 335655018 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17014.473885 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17014.473885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17014.473885 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17014.473885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17014.473885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17014.473885 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2055 # number of cycles access was blocked +system.cpu.icache.tags.replacements 22329 # number of replacements +system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits +system.cpu.icache.overall_hits::total 345973619 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 30537 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 30537 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 30537 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 30537 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 30537 # number of overall misses +system.cpu.icache.overall_misses::total 30537 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 527751245 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 527751245 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 527751245 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 527751245 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 527751245 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 527751245 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 346004156 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 346004156 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 346004156 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 346004156 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 346004156 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 346004156 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17282.354030 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17282.354030 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17282.354030 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17282.354030 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1734 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 35 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58.714286 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 54.187500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2543 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2543 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2543 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2543 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2543 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2543 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28340 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28340 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28340 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28340 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28340 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28340 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 421731499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 421731499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 421731499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 421731499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 421731499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 421731499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14881.139697 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14881.139697 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14881.139697 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14881.139697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14881.139697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14881.139697 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2162 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2162 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2162 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2162 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2162 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2162 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28375 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28375 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28375 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28375 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28375 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28375 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 422292499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 422292499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 422292499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 422292499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 422292499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 422292499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14882.555031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14882.555031 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 442172 # number of replacements -system.cpu.l2cache.tagsinuse 32679.418470 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1109399 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 474919 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.335975 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1315.444690 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 50.407521 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31313.566259 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.040144 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001538 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.955614 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997297 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21617 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1057925 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1079542 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96335 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96335 # number of Writeback hits +system.cpu.l2cache.tags.replacements 442208 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304304 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307476 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304304 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58784.539474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62915.650639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62891.081197 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56999.065456 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56999.065456 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58906.211308 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62395.325386 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62377.525508 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58906.211308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62395.325386 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62377.525508 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56913.178207 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56913.178207 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532821 # number of replacements -system.cpu.dcache.tagsinuse 4094.414072 # Cycle average of tags in use -system.cpu.dcache.total_refs 970116115 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536917 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 631.209177 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 390600000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.414072 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999613 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999613 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 693989998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693989998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276093265 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276093265 # number of WriteReq hits +system.cpu.dcache.tags.replacements 1532805 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 696790485 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 696790485 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276093216 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276093216 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 970083263 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 970083263 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 970083263 # number of overall hits -system.cpu.dcache.overall_hits::total 970083263 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1953007 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1953007 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 842413 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 842413 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 972883701 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 972883701 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 972883701 # number of overall hits +system.cpu.dcache.overall_hits::total 972883701 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953888 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953888 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 842462 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 842462 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2795420 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2795420 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2795420 # number of overall misses -system.cpu.dcache.overall_misses::total 2795420 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79048557500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79048557500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 56325650469 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 56325650469 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 203500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 203500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 135374207969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 135374207969 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 135374207969 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 135374207969 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695943005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695943005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2796350 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2796350 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2796350 # number of overall misses +system.cpu.dcache.overall_misses::total 2796350 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79173694807 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79173694807 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 56852278531 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56852278531 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 204750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 136025973338 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 136025973338 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 136025973338 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 136025973338 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 698744373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 698744373 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972878683 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972878683 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972878683 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972878683 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002806 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002806 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 975680051 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 975680051 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 975680051 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 975680051 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002796 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002796 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002873 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002873 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002873 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002873 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40475.306796 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40475.306796 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66862.275949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66862.275949 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48427.144389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48427.144389 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2558 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 879 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 58 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40521.101930 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40521.101930 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67483.493061 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67483.493061 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 68250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 68250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48644.115843 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48644.115843 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2745 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 62 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.103448 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.876404 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.274194 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9.584270 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96335 # number of writebacks -system.cpu.dcache.writebacks::total 96335 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488604 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 488604 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765599 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765599 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96304 # number of writebacks +system.cpu.dcache.writebacks::total 96304 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489504 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489504 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765580 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765580 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1254203 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1254203 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1254203 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1254203 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464403 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464403 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541217 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541217 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541217 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541217 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42813858522 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42813858522 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4818359000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4818359000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47632217522 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47632217522 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47632217522 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47632217522 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002104 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29236.390886 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29236.390886 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62727.614758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62727.614758 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1255084 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1255084 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1255084 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1255084 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464384 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464384 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76882 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76882 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541266 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541266 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541266 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541266 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42754567776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42754567776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4832230139 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4832230139 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47586797915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47586797915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47586797915 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47586797915 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002096 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002096 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001580 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001580 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29196.281697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29196.281697 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62852.555071 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62852.555071 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 6e9e09ef8..b119e8929 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 4652237184 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.tagsinuse 1392.317060 # Cycle average of tags in use -system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 18364 # number of replacements +system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 441378 # number of replacements -system.cpu.l2cache.tagsinuse 32692.891822 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1102614 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 474121 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.325596 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 441378 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use -system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1529557 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 9b354cbb8..fc992598c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043732 # Number of seconds simulated -sim_ticks 43731802500 # Number of ticks simulated -final_tick 43731802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043769 # Number of seconds simulated +sim_ticks 43769191000 # Number of ticks simulated +final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69429 # Simulator instruction rate (inst/s) -host_op_rate 69429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34369620 # Simulator tick rate (ticks/s) -host_mem_usage 233240 # Number of bytes of host memory used -host_seconds 1272.40 # Real time elapsed on the host +host_inst_rate 112888 # Simulator instruction rate (inst/s) +host_op_rate 112888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55931443 # Simulator tick rate (ticks/s) +host_mem_usage 233228 # Number of bytes of host memory used +host_seconds 782.55 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 158412 # Nu system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10394998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 231830554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242225552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10394998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10394998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166830718 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166830718 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166830718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10394998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 231830554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 409056270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10386118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 231632520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 242018638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10386118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10386118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166688208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166688208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166688208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165515 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen system.physmem.cpureqs 279512 # Reqs generatd by CPU via cache - shady @@ -43,22 +43,22 @@ system.physmem.bytesConsumedRd 10592960 # by system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10439 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10013 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10351 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10256 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10015 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10350 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10362 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 9796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10273 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10510 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 10590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10480 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10237 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 10581 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 10468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10593 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 7259 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 7283 # Tr system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43731782000 # Total gap between requests +system.physmem.totGap 43769170000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -92,10 +92,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 113997 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 72899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 72862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4910 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,12 +124,12 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4951 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see @@ -147,209 +147,209 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 366.074289 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.394514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 748.149039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 19835 40.59% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7665 15.69% 56.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4199 8.59% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2953 6.04% 70.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2157 4.41% 75.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1715 3.51% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1297 2.65% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1110 2.27% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 804 1.65% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 685 1.40% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 483 0.99% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 536 1.10% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 409 0.84% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 338 0.69% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 255 0.52% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 348 0.71% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 228 0.47% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 211 0.43% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 159 0.33% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 209 0.43% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 394 0.81% 94.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 305 0.62% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 602 1.23% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 201 0.41% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 151 0.31% 97.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 39 0.08% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 155 0.32% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 66 0.14% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 55 0.11% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 29 0.06% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 79 0.16% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 48826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 366.351698 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.645495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 749.158032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 19754 40.46% 40.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7696 15.76% 56.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4247 8.70% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2897 5.93% 70.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2142 4.39% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1740 3.56% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1303 2.67% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1111 2.28% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 826 1.69% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 678 1.39% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 468 0.96% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 525 1.08% 88.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 411 0.84% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 341 0.70% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 262 0.54% 90.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 362 0.74% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 210 0.43% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 226 0.46% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 155 0.32% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 229 0.47% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 390 0.80% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 303 0.62% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 582 1.19% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 207 0.42% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 152 0.31% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 46 0.09% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 145 0.30% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 73 0.15% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 52 0.11% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 28 0.06% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 72 0.15% 98.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::2112-2113 42 0.09% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 46 0.09% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 24 0.05% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 45 0.09% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 30 0.06% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 23 0.05% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 17 0.03% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 14 0.03% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 23 0.05% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 11 0.02% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 12 0.02% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 11 0.02% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 10 0.02% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 6 0.01% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 12 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 5 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 7 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 6 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 6 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 42 0.09% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 23 0.05% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.10% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 25 0.05% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 11 0.02% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 23 0.05% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 7 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 13 0.03% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 21 0.04% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 13 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 14 0.03% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 8 0.02% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 9 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 5 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 8 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 5 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 3 0.01% 99.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::4096-4097 7 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 9 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 6 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 6 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 5 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 6 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 6 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 12 0.02% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 3 0.01% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 6 0.01% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 164 0.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48863 # Bytes accessed per row activation -system.physmem.totQLat 6289978250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8777494500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::total 48826 # Bytes accessed per row activation +system.physmem.totQLat 6287289000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8773086500 # Sum of mem lat for all requests system.physmem.totBusLat 827575000 # Total cycles spent in databus access -system.physmem.totBankLat 1659941250 # Total cycles spent in bank access -system.physmem.avgQLat 38002.47 # Average queueing delay per request -system.physmem.avgBankLat 10028.95 # Average bank access latency per request +system.physmem.totBankLat 1658222500 # Total cycles spent in bank access +system.physmem.avgQLat 37986.22 # Average queueing delay per request +system.physmem.avgBankLat 10018.56 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53031.41 # Average memory access latency -system.physmem.avgRdBW 242.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 166.83 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 242.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 166.83 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53004.78 # Average memory access latency +system.physmem.avgRdBW 242.02 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 166.69 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 242.02 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 166.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.20 # Data bus utilization in percentage +system.physmem.busUtil 3.19 # Data bus utilization in percentage system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 10.42 # Average write queue length over time -system.physmem.readRowHits 153768 # Number of row buffer hits during reads -system.physmem.writeRowHits 76872 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.90 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.43 # Row buffer hit rate for writes -system.physmem.avgGap 156457.62 # Average gap between requests -system.membus.throughput 409056270 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 34624 # Transaction distribution -system.membus.trans_dist::ReadResp 34624 # Transaction distribution +system.physmem.avgWrQLen 10.49 # Average write queue length over time +system.physmem.readRowHits 153779 # Number of row buffer hits during reads +system.physmem.writeRowHits 76898 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.46 # Row buffer hit rate for writes +system.physmem.avgGap 156591.38 # Average gap between requests +system.membus.throughput 408706846 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 34625 # Transaction distribution +system.membus.trans_dist::ReadResp 34625 # Transaction distribution system.membus.trans_dist::Writeback 113997 # Transaction distribution -system.membus.trans_dist::ReadExReq 130891 # Transaction distribution -system.membus.trans_dist::ReadExResp 130891 # Transaction distribution +system.membus.trans_dist::ReadExReq 130890 # Transaction distribution +system.membus.trans_dist::ReadExResp 130890 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side 445027 # Packet count per connected master and slave (bytes) system.membus.pkt_count 445027 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1215256500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1522914250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1522799000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) -system.cpu.branchPred.lookups 18742056 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318265 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4775163 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15487144 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4660091 # Number of BTB hits +system.cpu.branchPred.lookups 18742730 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318368 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 15507340 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4664027 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.090061 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1660966 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 30.076254 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277593 # DTB read hits +system.cpu.dtb.read_hits 20277790 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367741 # DTB read accesses -system.cpu.dtb.write_hits 14728959 # DTB write hits +system.cpu.dtb.read_accesses 20367938 # DTB read accesses +system.cpu.dtb.write_hits 14728966 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736211 # DTB write accesses -system.cpu.dtb.data_hits 35006552 # DTB hits +system.cpu.dtb.write_accesses 14736218 # DTB write accesses +system.cpu.dtb.data_hits 35006756 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103952 # DTB accesses -system.cpu.itb.fetch_hits 12367361 # ITB hits -system.cpu.itb.fetch_misses 10891 # ITB misses +system.cpu.dtb.data_accesses 35104156 # DTB accesses +system.cpu.itb.fetch_hits 12367759 # ITB hits +system.cpu.itb.fetch_misses 11021 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378252 # ITB accesses +system.cpu.itb.fetch_accesses 12378780 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -363,34 +363,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87463606 # number of cpu cycles simulated +system.cpu.numCycles 87538383 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8070350 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10671706 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74169774 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8074238 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10668492 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74161920 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126489024 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 66036 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126481170 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293666 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14166320 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35060384 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4447706 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 216957 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4664663 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9107934 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.869161 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44778070 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14174454 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060070 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77195811 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77194023 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 233969 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17892398 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69571208 # Number of cycles cpu stages are processed. -system.cpu.activity 79.543036 # Percentage of cycles cpu is active +system.cpu.timesIdled 231301 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17962893 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69575490 # Number of cycles cpu stages are processed. +system.cpu.activity 79.479981 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -402,214 +402,214 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.990072 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.990918 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.990072 # CPI: Total CPI of All Threads -system.cpu.ipc 1.010028 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.990918 # CPI: Total CPI of All Threads +system.cpu.ipc 1.009165 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.010028 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34814257 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52649349 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.195722 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45010578 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42453028 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.537935 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44433795 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43029811 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.197390 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65350614 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22112992 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.282507 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41414421 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46049185 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.649539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 84399 # number of replacements -system.cpu.icache.tagsinuse 1906.561640 # Cycle average of tags in use -system.cpu.icache.total_refs 12250118 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 86445 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.709966 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1906.561640 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.930938 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.930938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12250118 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250118 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250118 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250118 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250118 # number of overall hits -system.cpu.icache.overall_hits::total 12250118 # number of overall hits +system.cpu.ipc_total 1.009165 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34882792 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52655591 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.151432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45083196 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42455187 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.498939 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44507774 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43030609 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.156276 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65417325 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22121058 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.270124 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41496378 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46042005 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.596362 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 84371 # number of replacements +system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12250515 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250515 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250515 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250515 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250515 # number of overall hits +system.cpu.icache.overall_hits::total 12250515 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 117235 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 117235 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 117235 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 117235 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 117235 # number of overall misses system.cpu.icache.overall_misses::total 117235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2039550500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2039550500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2039550500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2039550500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2039550500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2039550500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367353 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367353 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367353 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367353 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2053420481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2053420481 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2053420481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2053420481 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2053420481 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2053420481 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12367750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367750 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367750 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367750 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367750 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009479 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.009479 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.009479 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.009479 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009479 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009479 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17397.112637 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17397.112637 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17397.112637 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17397.112637 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17397.112637 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17397.112637 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 661 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 188 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17515.421854 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17515.421854 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17515.421854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17515.421854 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 36.722222 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.812500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30790 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30790 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30790 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30790 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30790 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30790 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86445 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 86445 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 86445 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 86445 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 86445 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 86445 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1457986019 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1457986019 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1457986019 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1457986019 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1457986019 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1457986019 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006990 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006990 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006990 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006990 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006990 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006990 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16866.053780 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16866.053780 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16866.053780 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16866.053780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16866.053780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16866.053780 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30818 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30818 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30818 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30818 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30818 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30818 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1462353516 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1462353516 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1462353516 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1462353516 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1462353516 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1462353516 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16922.058345 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16922.058345 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 671941569 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 147022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 147022 # Transaction distribution +system.cpu.toL2Bus.throughput 671326642 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143770 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 172890 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 172834 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577046 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 749936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5532480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 749880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5530688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23852736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29385216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29385216 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size 29383424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 397924000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 129676981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 131178984 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 306529482 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 326782984 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.l2cache.replacements 131592 # number of replacements -system.cpu.l2cache.tagsinuse 30902.534146 # Cycle average of tags in use -system.cpu.l2cache.total_refs 151462 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 163650 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.925524 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27127.756920 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2008.955025 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1765.822201 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.827873 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.053889 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.943071 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 79342 # number of ReadReq hits +system.cpu.l2cache.tags.replacements 131591 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27124.475533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.827773 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061262 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.054026 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943061 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 112398 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 168352 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 168352 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 79342 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 79314 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 45935 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 125277 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 79342 # number of overall hits +system.cpu.l2cache.demand_hits::total 125249 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 79314 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 45935 # number of overall hits -system.cpu.l2cache.overall_hits::total 125277 # number of overall hits +system.cpu.l2cache.overall_hits::total 125249 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 7103 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27521 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 34624 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130891 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130891 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27522 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 34625 # 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number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2014348750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2594490500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13747919500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13747919500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 580141750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15762268250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16342410000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 580141750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15762268250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16342410000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146995 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 168352 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 168352 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 86445 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 86417 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290792 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 86445 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290764 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 86417 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290792 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082168 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454314 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.235502 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 290764 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082194 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082168 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569187 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082168 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569187 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81013.796987 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73115.075760 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74735.472505 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104943.796747 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104943.796747 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81013.796987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99414.176325 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98624.532520 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81013.796987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99414.176325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98624.532520 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81675.594819 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73190.493060 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74931.133574 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105034.146994 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105034.146994 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98736.730810 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98736.730810 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -621,83 +621,83 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks system.cpu.l2cache.writebacks::total 113997 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7103 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34624 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27522 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34625 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130890 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130890 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 7103 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 165515 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 487204750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1670232750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2157437500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12146942750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12146942750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 487204750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13817175500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14304380250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 487204750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13817175500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14304380250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082168 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454314 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235502 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 490395250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1665695250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156090500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12145170500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12145170500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 490395250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13810865750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14301261000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 490395250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13810865750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14301261000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082168 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569187 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082168 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.569187 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68591.405040 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60689.391737 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62310.463840 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92801.970724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92801.970724 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68591.405040 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87223.035502 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86423.467662 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68591.405040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87223.035502 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86423.467662 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69040.581444 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60522.318509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62269.761733 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92789.139736 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92789.139736 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4076.684340 # Cycle average of tags in use -system.cpu.dcache.total_refs 33754860 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.184025 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 292193000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.684340 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995284 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995284 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180280 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180280 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574580 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574580 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754860 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754860 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754860 # number of overall hits -system.cpu.dcache.overall_hits::total 33754860 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96358 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96358 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038797 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038797 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135155 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135155 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135155 # number of overall misses -system.cpu.dcache.overall_misses::total 1135155 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4970252500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4970252500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 87207912000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 87207912000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92178164500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92178164500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92178164500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92178164500 # number of overall miss cycles +system.cpu.dcache.tags.replacements 200251 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574569 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574569 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754840 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754840 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754840 # number of overall hits +system.cpu.dcache.overall_hits::total 33754840 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038808 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038808 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135175 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135175 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135175 # number of overall misses +system.cpu.dcache.overall_misses::total 1135175 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010614984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5010614984 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 87491278500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 87491278500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92501893484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92501893484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92501893484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92501893484 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -706,40 +706,40 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51581.108989 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51581.108989 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83950.870093 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 83950.870093 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81203.152433 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81203.152433 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5824366 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116607 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071086 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51995.133023 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51995.133023 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84222.761569 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84222.761569 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81486.901565 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81486.901565 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5878259 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 106 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116796 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.948682 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.329284 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 106 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks system.cpu.dcache.writebacks::total 168352 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35591 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35591 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895217 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895217 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930808 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930808 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930808 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930808 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35600 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35600 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895228 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895228 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930828 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930828 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930828 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930828 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -748,14 +748,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2407208517 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2407208517 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14006251501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14006251501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16413460018 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16413460018 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16413460018 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16413460018 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2409027516 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2409027516 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14018315000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14018315000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16427342516 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16427342516 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16427342516 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16427342516 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -764,14 +764,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39613.746227 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39613.746227 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97550.156714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97550.156714 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39643.680221 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39643.680221 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97634.176069 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97634.176069 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 42c254d5a..a1c1e25d4 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024943 # Number of seconds simulated -sim_ticks 24942850000 # Number of ticks simulated -final_tick 24942850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024977 # Number of seconds simulated +sim_ticks 24977022500 # Number of ticks simulated +final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187895 # Simulator instruction rate (inst/s) -host_op_rate 187895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58883311 # Simulator tick rate (ticks/s) +host_inst_rate 130696 # Simulator instruction rate (inst/s) +host_op_rate 130696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41014411 # Simulator tick rate (ticks/s) host_mem_usage 236320 # Number of bytes of host memory used -host_seconds 423.60 # Real time elapsed on the host +host_seconds 608.98 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 490496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153472 # Number of bytes read from this memory -system.physmem.bytes_read::total 10643968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296640 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296640 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7664 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158648 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166312 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114010 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114010 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19664794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 407069441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 426734234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19664794 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19664794 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 292534333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 292534333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 292534333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19664794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 407069441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 719268568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166312 # Total number of read requests seen -system.physmem.writeReqs 114010 # Total number of write requests seen -system.physmem.cpureqs 280322 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10643968 # Total number of bytes read from memory -system.physmem.bytesWritten 7296640 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10643968 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296640 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153536 # Number of bytes read from this memory +system.physmem.bytes_read::total 10643520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158649 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166305 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19617390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 406515068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 426132458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19617390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19617390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 292149475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 292149475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 292149475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166305 # Total number of read requests seen +system.physmem.writeReqs 114016 # Total number of write requests seen +system.physmem.cpureqs 280321 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10643520 # Total number of bytes read from memory +system.physmem.bytesWritten 7297024 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10055 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9845 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10639 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10621 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10312 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10060 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10618 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10548 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10226 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10618 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10625 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7257 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7260 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7176 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7177 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6943 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6990 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6967 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24942817000 # Total gap between requests +system.physmem.totGap 24976988500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166312 # Categorize read packet sizes +system.physmem.readPktSize::6 166305 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114010 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 73936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 25960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114016 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 72274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,9 +124,9 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4953 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see @@ -146,208 +146,208 @@ system.physmem.wrQLenPdf::18 4957 # Wh system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 360.286489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 169.159256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 741.433360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 20689 41.55% 41.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7785 15.64% 57.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4196 8.43% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3037 6.10% 71.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2069 4.16% 75.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1703 3.42% 79.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1326 2.66% 81.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1152 2.31% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 751 1.51% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 622 1.25% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 468 0.94% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 538 1.08% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 428 0.86% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 311 0.62% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 271 0.54% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 335 0.67% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 282 0.57% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 173 0.35% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 131 0.26% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 297 0.60% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 411 0.83% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 172 0.35% 94.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 311 0.62% 95.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 639 1.28% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 258 0.52% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 81 0.16% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 48 0.10% 97.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 163 0.33% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 101 0.20% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 35 0.07% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 33 0.07% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 83 0.17% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 54 0.11% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 28 0.06% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 37 0.07% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 43 0.09% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 20 0.04% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 23 0.05% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 20 0.04% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 10 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 11 0.02% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 8 0.02% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 16 0.03% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 8 0.02% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 7 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 49952 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.130045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.640646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 741.801736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 20814 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7820 15.66% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4185 8.38% 65.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3013 6.03% 71.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2148 4.30% 76.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1700 3.40% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1301 2.60% 82.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1098 2.20% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 776 1.55% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 657 1.32% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 496 0.99% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 568 1.14% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 406 0.81% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 302 0.60% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 268 0.54% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 357 0.71% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 241 0.48% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 170 0.34% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 145 0.29% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 323 0.65% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 351 0.70% 94.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 146 0.29% 94.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 301 0.60% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 689 1.38% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 236 0.47% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 76 0.15% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 36 0.07% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 184 0.37% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 89 0.18% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 34 0.07% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 40 0.08% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 93 0.19% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 64 0.13% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 19 0.04% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 44 0.09% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 19 0.04% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 19 0.04% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 36 0.07% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 21 0.04% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 12 0.02% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 20 0.04% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 10 0.02% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 10 0.02% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 17 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 15 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 9 0.02% 99.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 17 0.03% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 7 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 10 0.02% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 8 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 7 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 8 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 8 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 9 0.02% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 10 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 5 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 6 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 5 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 6 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 8 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 13 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 5 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 9 0.02% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 5 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 10 0.02% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 165 0.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49789 # Bytes accessed per row activation -system.physmem.totQLat 6526905250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8951626500 # Sum of mem lat for all requests -system.physmem.totBusLat 831550000 # Total cycles spent in databus access -system.physmem.totBankLat 1593171250 # Total cycles spent in bank access -system.physmem.avgQLat 39245.42 # Average queueing delay per request -system.physmem.avgBankLat 9579.53 # Average bank access latency per request +system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 11 0.02% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 7 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 169 0.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49952 # Bytes accessed per row activation +system.physmem.totQLat 6557959000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8953517750 # Sum of mem lat for all requests +system.physmem.totBusLat 831510000 # Total cycles spent in databus access +system.physmem.totBankLat 1564048750 # Total cycles spent in bank access +system.physmem.avgQLat 39434.04 # Average queueing delay per request +system.physmem.avgBankLat 9404.87 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53824.94 # Average memory access latency -system.physmem.avgRdBW 426.73 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 292.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 426.73 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 292.53 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53838.91 # Average memory access latency +system.physmem.avgRdBW 426.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 292.15 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 426.13 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 292.15 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.62 # Data bus utilization in percentage +system.physmem.busUtil 5.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.36 # Average read queue length over time -system.physmem.avgWrQLen 10.09 # Average write queue length over time -system.physmem.readRowHits 154174 # Number of row buffer hits during reads -system.physmem.writeRowHits 76335 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.95 # Row buffer hit rate for writes -system.physmem.avgGap 88979.16 # Average gap between requests -system.membus.throughput 719268568 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35517 # Transaction distribution -system.membus.trans_dist::ReadResp 35517 # Transaction distribution -system.membus.trans_dist::Writeback 114010 # Transaction distribution -system.membus.trans_dist::ReadExReq 130795 # Transaction distribution -system.membus.trans_dist::ReadExResp 130795 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 446634 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 446634 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 17940608 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17940608 # Total data (bytes) +system.physmem.avgWrQLen 9.86 # Average write queue length over time +system.physmem.readRowHits 154145 # Number of row buffer hits during reads +system.physmem.writeRowHits 76216 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.85 # Row buffer hit rate for writes +system.physmem.avgGap 89101.38 # Average gap between requests +system.membus.throughput 718281933 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35508 # Transaction distribution +system.membus.trans_dist::ReadResp 35508 # Transaction distribution +system.membus.trans_dist::Writeback 114016 # Transaction distribution +system.membus.trans_dist::ReadExReq 130797 # Transaction distribution +system.membus.trans_dist::ReadExResp 130797 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 446626 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 446626 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1221780000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 4.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 1527507000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.1 # Layer utilization (%) -system.cpu.branchPred.lookups 16555988 # Number of BP lookups -system.cpu.branchPred.condPredicted 10692092 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 419935 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11595461 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7351910 # Number of BTB hits +system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 1541382250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.2 # Layer utilization (%) +system.cpu.branchPred.lookups 16531947 # Number of BP lookups +system.cpu.branchPred.condPredicted 10672978 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 414050 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11481292 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7335496 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.403344 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1990234 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41425 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.890858 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1991572 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 40927 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22410816 # DTB read hits -system.cpu.dtb.read_misses 219473 # DTB read misses -system.cpu.dtb.read_acv 42 # DTB read access violations -system.cpu.dtb.read_accesses 22630289 # DTB read accesses -system.cpu.dtb.write_hits 15705108 # DTB write hits -system.cpu.dtb.write_misses 41065 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 15746173 # DTB write accesses -system.cpu.dtb.data_hits 38115924 # DTB hits -system.cpu.dtb.data_misses 260538 # DTB misses -system.cpu.dtb.data_acv 44 # DTB access violations -system.cpu.dtb.data_accesses 38376462 # DTB accesses -system.cpu.itb.fetch_hits 13936543 # ITB hits -system.cpu.itb.fetch_misses 35109 # ITB misses +system.cpu.dtb.read_hits 22403443 # DTB read hits +system.cpu.dtb.read_misses 219972 # DTB read misses +system.cpu.dtb.read_acv 45 # DTB read access violations +system.cpu.dtb.read_accesses 22623415 # DTB read accesses +system.cpu.dtb.write_hits 15699616 # DTB write hits +system.cpu.dtb.write_misses 41064 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 15740680 # DTB write accesses +system.cpu.dtb.data_hits 38103059 # DTB hits +system.cpu.dtb.data_misses 261036 # DTB misses +system.cpu.dtb.data_acv 46 # DTB access violations +system.cpu.dtb.data_accesses 38364095 # DTB accesses +system.cpu.itb.fetch_hits 13905618 # ITB hits +system.cpu.itb.fetch_misses 35229 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13971652 # ITB accesses +system.cpu.itb.fetch_accesses 13940847 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -361,139 +361,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49885704 # number of cpu cycles simulated +system.cpu.numCycles 49954048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15828757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105472202 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16555988 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9342144 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19569330 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2015634 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7564714 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 312127 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13936543 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 209148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44745227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.357172 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15782352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105305571 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16531947 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9327068 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19535430 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1996105 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7525610 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314470 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13905618 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 207845 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44615196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.360307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120920 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25175897 56.26% 56.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1533640 3.43% 59.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1372500 3.07% 62.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1510966 3.38% 66.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4145174 9.26% 75.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1852523 4.14% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 674526 1.51% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069811 2.39% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7410190 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25079766 56.21% 56.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1526701 3.42% 59.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1368492 3.07% 62.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1511592 3.39% 66.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4137930 9.27% 75.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1849422 4.15% 79.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 676249 1.52% 81.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069566 2.40% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7395478 16.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44745227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.331878 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.114277 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16915257 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7099488 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18565359 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 807394 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1357729 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3748109 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107416 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103728039 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304294 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1357729 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17378057 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4787405 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84706 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18857243 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2280087 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102449322 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 562 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2762 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2150788 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61699088 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123470125 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123020099 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 450026 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44615196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.330943 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.108049 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16870832 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7056928 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18547803 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 794977 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1344656 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3743758 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107019 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103586885 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 307942 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1344656 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17339272 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4755583 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85639 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18836599 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2253447 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102335224 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 557 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2492 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122850608 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 451670 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9152207 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5534 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4701242 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23248702 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16281518 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1196604 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 458974 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90797694 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5272 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88473068 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 98121 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10747304 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4709427 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 689 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44745227 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.977263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.106527 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5530 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4823408 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23239875 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16264209 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1185310 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 465013 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90722071 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5344 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88415019 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 95015 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10694229 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4666218 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 761 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44615196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981724 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109954 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16442789 36.75% 36.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6947095 15.53% 52.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5617294 12.55% 64.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4751397 10.62% 75.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4688341 10.48% 85.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649423 5.92% 91.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1924303 4.30% 96.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1305783 2.92% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 418802 0.94% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16409410 36.78% 36.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6866152 15.39% 52.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5567351 12.48% 64.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4772569 10.70% 75.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4725060 10.59% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2625070 5.88% 91.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1917083 4.30% 96.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1291638 2.90% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 440863 0.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44745227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44615196 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126164 6.77% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 785807 42.18% 48.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 951202 51.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126842 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 784071 42.12% 48.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 950643 51.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49382358 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43890 0.05% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121219 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121003 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38951 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49344695 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43834 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121349 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121152 0.14% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38963 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -515,84 +515,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22865563 25.84% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15899938 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22855764 25.85% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15889119 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88473068 # Type of FU issued -system.cpu.iq.rate 1.773515 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1863173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021059 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223048793 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101154216 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86567905 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603864 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414189 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294216 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90034241 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 302000 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1467603 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88415019 # Type of FU issued +system.cpu.iq.rate 1.769927 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1861556 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021055 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222796879 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101023469 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86533748 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 604926 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 415943 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294379 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89974024 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 302551 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1471412 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2972064 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5071 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18375 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1668141 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2963237 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4955 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18224 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1650832 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2922 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 100269 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2867 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 96301 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1357729 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3744152 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 78814 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100285943 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219681 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23248702 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16281518 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5272 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60147 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 593 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18375 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 199378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 160408 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 359786 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87617560 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22633363 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 855508 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1344656 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3651094 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 72855 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100203758 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 216158 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23239875 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16264209 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5344 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49772 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6561 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18224 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 192723 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161669 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 354392 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87578159 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22626447 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 836860 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9482977 # number of nop insts executed -system.cpu.iew.exec_refs 38379854 # number of memory reference insts executed -system.cpu.iew.exec_branches 15087965 # Number of branches executed -system.cpu.iew.exec_stores 15746491 # Number of stores executed -system.cpu.iew.exec_rate 1.756366 # Inst execution rate -system.cpu.iew.wb_sent 87252732 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86862121 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33357056 # num instructions producing a value -system.cpu.iew.wb_consumers 43763173 # num instructions consuming a value +system.cpu.iew.exec_nop 9476343 # number of nop insts executed +system.cpu.iew.exec_refs 38367436 # number of memory reference insts executed +system.cpu.iew.exec_branches 15087087 # Number of branches executed +system.cpu.iew.exec_stores 15740989 # Number of stores executed +system.cpu.iew.exec_rate 1.753174 # Inst execution rate +system.cpu.iew.wb_sent 87216851 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86828127 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33345535 # num instructions producing a value +system.cpu.iew.wb_consumers 43468305 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.741223 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762217 # average fanout of values written-back +system.cpu.iew.wb_rate 1.738160 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767123 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8947131 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8869178 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 315269 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43387498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.036086 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.786442 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 309326 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43270540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.041589 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791914 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20491808 47.23% 47.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7040185 16.23% 63.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3430647 7.91% 71.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2065344 4.76% 76.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2060078 4.75% 80.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1160326 2.67% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1096269 2.53% 86.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719123 1.66% 87.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5323718 12.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20425554 47.20% 47.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7044262 16.28% 63.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3374707 7.80% 71.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2054728 4.75% 76.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2036437 4.71% 80.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1166697 2.70% 83.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1108378 2.56% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 724905 1.68% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5334872 12.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43387498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43270540 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,212 +603,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5323718 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5334872 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 134034241 # The number of ROB reads -system.cpu.rob.rob_writes 195936054 # The number of ROB writes -system.cpu.timesIdled 84426 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5140477 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133828176 # The number of ROB reads +system.cpu.rob.rob_writes 195767077 # The number of ROB writes +system.cpu.timesIdled 83938 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5338852 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.626770 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.626770 # CPI: Total CPI of All Threads -system.cpu.ipc 1.595482 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.595482 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115957750 # number of integer regfile reads -system.cpu.int_regfile_writes 57532597 # number of integer regfile writes -system.cpu.fp_regfile_reads 249573 # number of floating regfile reads -system.cpu.fp_regfile_writes 239887 # number of floating regfile writes -system.cpu.misc_regfile_reads 38017 # number of misc regfile reads +system.cpu.cpi 0.627628 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.627628 # CPI: Total CPI of All Threads +system.cpu.ipc 1.593299 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.593299 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115893073 # number of integer regfile reads +system.cpu.int_regfile_writes 57500612 # number of integer regfile writes +system.cpu.fp_regfile_reads 249654 # number of floating regfile reads +system.cpu.fp_regfile_writes 240130 # number of floating regfile writes +system.cpu.misc_regfile_reads 38049 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1201112463 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155760 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155759 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143412 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 187195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580089 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 767284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5990208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23968960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29959168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29959168 # Total data (bytes) +system.cpu.toL2Bus.throughput 1198592827 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155432 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 186551 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580061 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 766612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5969600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23967680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 29937280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402997500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 140404482 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141571734 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308361998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.icache.replacements 91549 # number of replacements -system.cpu.icache.tagsinuse 1926.731072 # Cycle average of tags in use -system.cpu.icache.total_refs 13830286 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93597 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.764202 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20183588000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1926.731072 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.940787 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.940787 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13830286 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13830286 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13830286 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13830286 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13830286 # number of overall hits -system.cpu.icache.overall_hits::total 13830286 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106255 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106255 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106255 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106255 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106255 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19525.283170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19525.283170 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44.428571 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35.812500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93598 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93598 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1582060018 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1582060018 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1582060018 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1582060018 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1582060018 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1582060018 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006716 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006716 # 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Cycle average of tags in use -system.cpu.l2cache.total_refs 159968 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 164470 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.972627 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26413.266317 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2101.990357 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 2207.047959 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.806069 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.064148 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.067354 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.937570 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 85933 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75738.842812 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77309.027289 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107568.438114 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107568.438114 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.504114 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101980.518314 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 101107.568278 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.504114 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101980.518314 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 101107.568278 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -817,164 +817,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114010 # number of writebacks -system.cpu.l2cache.writebacks::total 114010 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7665 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27853 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35518 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130795 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130795 # 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number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7657 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27852 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35509 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130797 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130797 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7657 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158649 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166306 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7657 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158649 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166306 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 538279000 # 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Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20615905 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20615905 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574108 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574108 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34190013 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34190013 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34190013 # number of overall hits +system.cpu.dcache.overall_hits::total 34190013 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267467 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267467 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039269 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039269 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306736 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306736 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306736 # number of overall misses +system.cpu.dcache.overall_misses::total 1306736 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15939734750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15939734750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 90566913172 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 90566913172 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106506647922 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106506647922 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106506647922 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106506647922 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20883372 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20883372 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35510616 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35510616 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35510616 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35510616 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012772 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012772 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071119 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071119 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036783 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036783 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036783 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036783 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58582.685441 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58582.685441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86560.535625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 86560.535625 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80843.833387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80843.833387 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5220473 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 159 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112927 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35496749 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35496749 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35496749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35496749 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012808 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012808 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071118 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036813 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036813 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036813 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036813 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59595.145382 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59595.145382 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87144.823113 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 87144.823113 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81505.864935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81505.864935 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5253118 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 160 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112229 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.228741 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 159 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.807135 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 160 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168941 # number of writebacks -system.cpu.dcache.writebacks::total 168941 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204728 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 204728 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895877 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895877 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100605 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100605 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100605 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100605 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62163 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62163 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143411 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143411 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205574 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205574 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205574 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205574 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2517427002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2517427002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14256184493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14256184493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16773611495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16773611495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16773611495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16773611495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40497.192896 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40497.192896 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99407.887073 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99407.887073 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks +system.cpu.dcache.writebacks::total 168929 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205307 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205307 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895863 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895863 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101170 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101170 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101170 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101170 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62160 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62160 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205566 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205566 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205566 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205566 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2516687000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2516687000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14340164994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14340164994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16856851994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16856851994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16856851994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16856851994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002977 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002977 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.242600 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.242600 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99996.966612 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99996.966612 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 9b4737e22..060f66d07 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 267269454 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.686406 # Cycle average of tags in use -system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 74391 # number of replacements +system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 131235 # number of replacements -system.cpu.l2cache.tagsinuse 30728.810101 # Cycle average of tags in use -system.cpu.l2cache.total_refs 142024 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 163291 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.869760 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.937769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 131235 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use -system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 200248 # number of replacements +system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 419a13ff5..8607c685b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026649 # Number of seconds simulated -sim_ticks 26649062500 # Number of ticks simulated -final_tick 26649062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026765 # Number of seconds simulated +sim_ticks 26765004500 # Number of ticks simulated +final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95593 # Simulator instruction rate (inst/s) -host_op_rate 135659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35926621 # Simulator tick rate (ticks/s) -host_mem_usage 255136 # Number of bytes of host memory used -host_seconds 741.76 # Real time elapsed on the host +host_inst_rate 88779 # Simulator instruction rate (inst/s) +host_op_rate 125988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33510752 # Simulator tick rate (ticks/s) +host_mem_usage 255124 # Number of bytes of host memory used +host_seconds 798.70 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory -system.physmem.bytes_read::total 8240768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128762 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11193790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 298039152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 309232942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11193790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11193790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 201613096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 201613096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 201613096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11193790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 298039152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 510846038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128763 # Total number of read requests seen -system.physmem.writeReqs 83950 # Total number of write requests seen -system.physmem.cpureqs 213025 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8240768 # Total number of bytes read from memory -system.physmem.bytesWritten 5372800 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8240768 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372800 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8141 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8450 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8090 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7962 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8062 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7880 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8005 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5268 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7944704 # Number of bytes read from this memory +system.physmem.bytes_read::total 8242496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372160 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372160 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4653 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124136 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128789 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83940 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83940 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11126170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296831783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307957953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11126170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11126170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200715827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200715827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200715827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128790 # Total number of read requests seen +system.physmem.writeReqs 83940 # Total number of write requests seen +system.physmem.cpureqs 213051 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8242496 # Total number of bytes read from memory +system.physmem.bytesWritten 5372160 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8159 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8089 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7815 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 7883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7888 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7978 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8014 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5378 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5264 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 5519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5206 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5031 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5089 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5091 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 5253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5145 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5343 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5342 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 5363 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 5451 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 5227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26649044000 # Total gap between requests +system.physmem.totGap 26764988000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128763 # Categorize read packet sizes +system.physmem.readPktSize::6 128790 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83950 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 75538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83940 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 76190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,11 +124,11 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -137,201 +137,201 @@ system.physmem.wrQLenPdf::9 3650 # Wh system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 390.104497 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.978164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 858.430673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 13421 38.47% 38.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5383 15.43% 53.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3065 8.78% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2226 6.38% 69.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1625 4.66% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1388 3.98% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1071 3.07% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 870 2.49% 83.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 590 1.69% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 488 1.40% 86.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 448 1.28% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 588 1.69% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 296 0.85% 90.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 306 0.88% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 186 0.53% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 205 0.59% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 126 0.36% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 210 0.60% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 103 0.30% 93.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 233 0.67% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 114 0.33% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 336 0.96% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 140 0.40% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 305 0.87% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 63 0.18% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 139 0.40% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 46 0.13% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 83 0.24% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 24 0.07% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 56 0.16% 97.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 58 0.17% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 11 0.03% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 27 0.08% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 19 0.05% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 23 0.07% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 10 0.03% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 17 0.05% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 8 0.02% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 14 0.04% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 16 0.05% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 16 0.05% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.03% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 15 0.04% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 7 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 7 0.02% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 12 0.03% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 11 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 7 0.02% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 3 0.01% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 9 0.03% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 3 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 7 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 34959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 389.285277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.799947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 855.459025 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 13425 38.40% 38.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5427 15.52% 53.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3113 8.90% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2218 6.34% 69.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1684 4.82% 73.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1324 3.79% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1016 2.91% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 832 2.38% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 675 1.93% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 524 1.50% 86.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 431 1.23% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 550 1.57% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 311 0.89% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 325 0.93% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 173 0.49% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 178 0.51% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 117 0.33% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 209 0.60% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 130 0.37% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 238 0.68% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 111 0.32% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 314 0.90% 95.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 120 0.34% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 318 0.91% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 69 0.20% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 140 0.40% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 41 0.12% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 97 0.28% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 65 0.19% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 25 0.07% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 42 0.12% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 12 0.03% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 31 0.09% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.05% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 26 0.07% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 33 0.09% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 11 0.03% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 15 0.04% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 11 0.03% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 8 0.02% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 11 0.03% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 15 0.04% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 9 0.03% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 11 0.03% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 6 0.02% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 5 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 3 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 7 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 3 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 4 0.01% 98.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3649 3 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.01% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 7 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 2 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 4 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 3 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 4 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 4 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 6 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 3 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 9 0.03% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 3 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 3 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 4 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 4 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 4 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 5 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 2 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 2 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 2 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 2 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.01% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 3 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 3 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 3 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 6 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 2 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6977 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::7488-7489 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 4 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 238 0.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34891 # Bytes accessed per row activation -system.physmem.totQLat 2799338750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4801886250 # Sum of mem lat for all requests -system.physmem.totBusLat 643800000 # Total cycles spent in databus access -system.physmem.totBankLat 1358747500 # Total cycles spent in bank access -system.physmem.avgQLat 21740.58 # Average queueing delay per request -system.physmem.avgBankLat 10552.48 # Average bank access latency per request -system.physmem.avgBusLat 4999.96 # Average bus latency per request -system.physmem.avgMemAccLat 37293.02 # Average memory access latency -system.physmem.avgRdBW 309.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 201.61 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 309.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 201.61 # Average consumed write bandwidth in MB/s +system.physmem.bytesPerActivate::8128-8129 2 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 239 0.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 34959 # Bytes accessed per row activation +system.physmem.totQLat 2852295000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4861110000 # Sum of mem lat for all requests +system.physmem.totBusLat 643935000 # Total cycles spent in databus access +system.physmem.totBankLat 1364880000 # Total cycles spent in bank access +system.physmem.avgQLat 22147.38 # Average queueing delay per request +system.physmem.avgBankLat 10597.96 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 37745.35 # Average memory access latency +system.physmem.avgRdBW 307.96 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 200.72 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 307.96 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 200.72 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.99 # Data bus utilization in percentage +system.physmem.busUtil 3.97 # Data bus utilization in percentage system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 10.01 # Average write queue length over time -system.physmem.readRowHits 120254 # Number of row buffer hits during reads -system.physmem.writeRowHits 57565 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.57 # Row buffer hit rate for writes -system.physmem.avgGap 125281.69 # Average gap between requests -system.membus.throughput 510846038 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26509 # Transaction distribution -system.membus.trans_dist::ReadResp 26508 # Transaction distribution -system.membus.trans_dist::Writeback 83950 # Transaction distribution -system.membus.trans_dist::UpgradeReq 312 # Transaction distribution -system.membus.trans_dist::UpgradeResp 312 # Transaction distribution -system.membus.trans_dist::ReadExReq 102254 # Transaction distribution -system.membus.trans_dist::ReadExResp 102254 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 342099 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 342099 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13613568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 13613568 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13613568 # Total data (bytes) +system.physmem.avgWrQLen 10.24 # Average write queue length over time +system.physmem.readRowHits 120249 # Number of row buffer hits during reads +system.physmem.writeRowHits 57506 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.51 # Row buffer hit rate for writes +system.physmem.avgGap 125816.71 # Average gap between requests +system.membus.throughput 508673780 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26538 # Transaction distribution +system.membus.trans_dist::ReadResp 26537 # Transaction distribution +system.membus.trans_dist::Writeback 83940 # Transaction distribution +system.membus.trans_dist::UpgradeReq 321 # Transaction distribution +system.membus.trans_dist::UpgradeResp 321 # Transaction distribution +system.membus.trans_dist::ReadExReq 102252 # Transaction distribution +system.membus.trans_dist::ReadExResp 102252 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 342161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 342161 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13614656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 13614656 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13614656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 926784500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1200135938 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1207011429 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) -system.cpu.branchPred.lookups 16620839 # Number of BP lookups -system.cpu.branchPred.condPredicted 12757336 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 602395 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10635009 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7765773 # Number of BTB hits +system.cpu.branchPred.lookups 16635237 # Number of BP lookups +system.cpu.branchPred.condPredicted 12768503 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 604840 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10652885 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7773045 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.020841 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1824331 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113161 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.966572 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1823659 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113448 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -375,99 +375,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53298126 # number of cpu cycles simulated +system.cpu.numCycles 53530010 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12535190 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85154971 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16620839 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9590104 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21184086 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2355794 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10829442 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 551 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11674707 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 181091 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46276167 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.576733 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.331391 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12549473 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85279503 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16635237 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9596704 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21206249 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2379470 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10773225 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 477 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11686664 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 178212 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46277294 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.580240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332526 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25111993 54.27% 54.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2139332 4.62% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1963886 4.24% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2043329 4.42% 67.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1467358 3.17% 70.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1375070 2.97% 73.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 956833 2.07% 75.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1188482 2.57% 78.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10029884 21.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25091643 54.22% 54.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2136768 4.62% 58.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1963962 4.24% 63.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2042989 4.41% 67.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466847 3.17% 70.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1383026 2.99% 73.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 957932 2.07% 75.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1190240 2.57% 78.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10043887 21.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46276167 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.311847 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.597710 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14619512 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9177970 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19466340 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1388431 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1623914 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3328977 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104776 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116789336 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 361687 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1623914 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16330804 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2680643 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1000847 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19093672 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5546287 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114905556 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 219 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17136 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4693151 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1312 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115218637 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529387920 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529379803 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8117 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46277294 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310765 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.593116 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14640784 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9115289 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19504792 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1371825 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1644604 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3334519 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105037 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116943845 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 363315 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1644604 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16350397 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2675070 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1001661 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19117578 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5487984 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115077475 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 183 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4627273 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 285 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115384718 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 530174580 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 530166885 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7695 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16085965 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20302 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20297 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13065620 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29609265 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22417131 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3885027 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4397806 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111472584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35916 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107208843 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 271699 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10738438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25737967 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2130 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46276167 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.316718 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.989507 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16252046 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20256 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20253 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13031784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29643166 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22451729 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3891559 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4392801 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111618845 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35897 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107291250 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 275974 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10887740 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26073816 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2111 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46277294 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.318443 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.990403 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11020528 23.81% 23.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8094858 17.49% 41.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7429249 16.05% 57.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7154901 15.46% 72.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5386733 11.64% 84.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3906460 8.44% 92.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1842144 3.98% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 871664 1.88% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 569630 1.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11003161 23.78% 23.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8115395 17.54% 41.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7436608 16.07% 57.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7096880 15.34% 72.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5407297 11.68% 84.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3935038 8.50% 92.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1843993 3.98% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 867713 1.88% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 571209 1.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46276167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46277294 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112593 4.57% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113414 4.57% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available @@ -496,118 +496,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1348878 54.73% 59.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1003122 40.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1362149 54.91% 59.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1005332 40.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56608598 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91438 0.09% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28894537 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21614012 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56660345 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91595 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 269 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28911335 26.95% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21627699 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107208843 # Type of FU issued -system.cpu.iq.rate 2.011494 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464595 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022989 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263429476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122274650 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105524045 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 671 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1168 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 196 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109673111 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2189921 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107291250 # Type of FU issued +system.cpu.iq.rate 2.004320 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2480897 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023123 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263615967 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122570490 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105600159 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 698 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1174 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 216 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109771796 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 351 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2179165 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2302157 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6684 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29801 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1861393 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2336058 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6530 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30281 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1895991 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 27 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 724 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 805 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1623914 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1145014 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 48197 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111518283 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 295309 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29609265 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22417131 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19996 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6449 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5406 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29801 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 392238 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181031 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 573269 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106181942 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28595303 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1026901 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1644604 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1147402 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 47438 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111664541 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 286964 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29643166 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22451729 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19977 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6774 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4975 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30281 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393124 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181749 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 574873 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106260947 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28610039 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030303 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9783 # number of nop insts executed -system.cpu.iew.exec_refs 49924361 # number of memory reference insts executed -system.cpu.iew.exec_branches 14597950 # Number of branches executed -system.cpu.iew.exec_stores 21329058 # Number of stores executed -system.cpu.iew.exec_rate 1.992227 # Inst execution rate -system.cpu.iew.wb_sent 105744224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105524241 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53247487 # num instructions producing a value -system.cpu.iew.wb_consumers 103444790 # num instructions consuming a value +system.cpu.iew.exec_nop 9799 # number of nop insts executed +system.cpu.iew.exec_refs 49952901 # number of memory reference insts executed +system.cpu.iew.exec_branches 14605114 # Number of branches executed +system.cpu.iew.exec_stores 21342862 # Number of stores executed +system.cpu.iew.exec_rate 1.985072 # Inst execution rate +system.cpu.iew.wb_sent 105821179 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105600375 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53334269 # num instructions producing a value +system.cpu.iew.wb_consumers 103952809 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.979887 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514743 # average fanout of values written-back +system.cpu.iew.wb_rate 1.972732 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.513062 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10886753 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11033009 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 499558 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44652253 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.253692 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.763005 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 501673 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44632690 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.254680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.761954 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15559873 34.85% 34.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11688259 26.18% 61.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3454288 7.74% 68.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2872185 6.43% 75.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1868727 4.19% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1932277 4.33% 83.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 683931 1.53% 85.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 562545 1.26% 86.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6030168 13.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15532654 34.80% 34.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11684135 26.18% 60.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462025 7.76% 68.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2877014 6.45% 75.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1854993 4.16% 79.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1951437 4.37% 83.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 690877 1.55% 85.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 565658 1.27% 86.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6013897 13.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44652253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44632690 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -618,226 +618,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6030168 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6013897 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150115967 # The number of ROB reads -system.cpu.rob.rob_writes 224671489 # The number of ROB writes -system.cpu.timesIdled 79206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7021959 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150258931 # The number of ROB reads +system.cpu.rob.rob_writes 224984633 # The number of ROB writes +system.cpu.timesIdled 80350 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7252716 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.751656 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.751656 # CPI: Total CPI of All Threads -system.cpu.ipc 1.330396 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.330396 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511415343 # number of integer regfile reads -system.cpu.int_regfile_writes 103300902 # number of integer regfile writes -system.cpu.fp_regfile_reads 1012 # number of floating regfile reads -system.cpu.fp_regfile_writes 876 # number of floating regfile writes -system.cpu.misc_regfile_reads 49160884 # number of misc regfile reads +system.cpu.cpi 0.754926 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.754926 # CPI: Total CPI of All Threads +system.cpu.ipc 1.324633 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.324633 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511766096 # number of integer regfile reads +system.cpu.int_regfile_writes 103375635 # number of integer regfile writes +system.cpu.fp_regfile_reads 1160 # number of floating regfile reads +system.cpu.fp_regfile_writes 1012 # number of floating regfile writes +system.cpu.misc_regfile_reads 49188390 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 776266857 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 87116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 87115 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129077 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 62962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454559 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 517521 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1998208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18655488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 20653696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20653696 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 33088 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 290859995 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 771895107 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 86668 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 86666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 61963 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454719 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 516682 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1966784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18660992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 20627776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47617981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 47827231 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 243817935 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.replacements 29381 # number of replacements -system.cpu.icache.tagsinuse 1810.408207 # Cycle average of tags in use -system.cpu.icache.total_refs 11639182 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31418 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 370.462219 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1810.408207 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.883988 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.883988 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11639193 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11639193 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11639193 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11639193 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11639193 # number of overall hits -system.cpu.icache.overall_hits::total 11639193 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35513 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35513 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35513 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35513 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35513 # number of overall misses -system.cpu.icache.overall_misses::total 35513 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 845054999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 845054999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 845054999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 845054999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 845054999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 845054999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11674706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11674706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11674706 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11674706 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11674706 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11674706 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003042 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003042 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003042 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003042 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003042 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23795.652268 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23795.652268 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23795.652268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23795.652268 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1082 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 28871 # number of replacements +system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11651673 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11651673 # number of overall hits +system.cpu.icache.overall_hits::total 11651673 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34991 # number of overall misses +system.cpu.icache.overall_misses::total 34991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 840169228 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 840169228 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 840169228 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 840169228 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8687985251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9019745751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 331760500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8687985251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9019745751 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307980 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.952381 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.952381 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72420.538473 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68911.961879 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68911.961879 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70575.235950 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69456.160708 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69496.678005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70575.235950 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69456.160708 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69496.678005 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69414.584423 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69414.584423 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # 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number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 951500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 951500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 128281947979 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 128281947979 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 128281947979 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 128281947979 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26173960 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26173960 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44341813 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44341813 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44341813 # number of overall hits +system.cpu.dcache.overall_hits::total 44341813 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125377 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125377 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583101 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583101 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708478 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708478 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708478 # number of overall misses +system.cpu.dcache.overall_misses::total 1708478 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5199394222 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5199394222 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 124981048011 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 124981048011 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 861250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 861250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 130180442233 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 130180442233 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 130180442233 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 130180442233 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26200390 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26200390 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16024 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16029 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46023861 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46023861 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46023861 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46023861 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004791 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004791 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002746 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002746 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037125 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037125 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40943.651471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40943.651471 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77783.170981 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77783.170981 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21625 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21625 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75079.273319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75079.273319 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5184 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1288 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46050291 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46050291 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46050291 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46050291 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004785 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004785 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079754 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079754 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002620 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002620 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037100 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037100 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037100 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037100 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41470.080015 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41470.080015 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78946.983175 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78946.983175 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20505.952381 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20505.952381 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76196.733135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76196.733135 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9105 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1249 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 129 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.751724 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 80.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.581395 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 78.062500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129077 # number of writebacks -system.cpu.dcache.writebacks::total 129077 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69998 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69998 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475881 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475881 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545879 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545879 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545879 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545879 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55409 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55409 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162741 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162741 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162741 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162741 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243387065 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243387065 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8465944990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8465944990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10709332055 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10709332055 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10709332055 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10709332055 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129110 # number of writebacks +system.cpu.dcache.writebacks::total 129110 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69907 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69907 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475766 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475766 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545673 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545673 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545673 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545673 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55470 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55470 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107335 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162805 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162805 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162805 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162805 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2262652309 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2262652309 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8543267922 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8543267922 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10805920231 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10805920231 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10805920231 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10805920231 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.773918 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.773918 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78876.243711 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78876.243711 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40790.559023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40790.559023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79594.427931 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79594.427931 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 9c1dc992d..170d172b3 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 265378090 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.497265 # Cycle average of tags in use -system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 16890 # number of replacements +system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 94693 # number of replacements -system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use -system.cpu.l2cache.total_refs 74295 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 125788 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.590637 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.926764 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 94693 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use -system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 155902 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 4b553d931..df352064c 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -73,15 +73,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 404484520 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.815325 # Cycle average of tags in use -system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 184976 # number of replacements +system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits @@ -151,19 +151,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 98540 # number of replacements -system.cpu.l2cache.tagsinuse 30850.759699 # Cycle average of tags in use -system.cpu.l2cache.total_refs 226933 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129534 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.751918 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941490 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 98540 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits @@ -289,15 +289,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use -system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 146582 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 24ed3058e..fe02977f3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.015958 # Number of seconds simulated -sim_ticks 1015958135500 # Number of ticks simulated -final_tick 1015958135500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.017017 # Number of seconds simulated +sim_ticks 1017016979500 # Number of ticks simulated +final_tick 1017016979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102863 # Simulator instruction rate (inst/s) -host_op_rate 102863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57427110 # Simulator tick rate (ticks/s) -host_mem_usage 225152 # Number of bytes of host memory used -host_seconds 17691.26 # Real time elapsed on the host +host_inst_rate 113008 # Simulator instruction rate (inst/s) +host_op_rate 113008 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63156510 # Simulator tick rate (ticks/s) +host_mem_usage 225148 # Number of bytes of host memory used +host_seconds 16103.12 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125365184 # Number of bytes read from this memory -system.physmem.bytes_read::total 125420160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365248 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420224 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958831 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1958832 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959691 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 123396014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 123450126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54112 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54112 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 64132280 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 64132280 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 64132280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 123396014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 187582407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959690 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 54056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 123267606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 123321662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 64065511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 64065511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 64065511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 123267606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 187387172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959691 # Total number of read requests seen system.physmem.writeReqs 1018058 # Total number of write requests seen -system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125420160 # Total number of bytes read from memory +system.physmem.cpureqs 2977749 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125420224 # Total number of bytes read from memory system.physmem.bytesWritten 65155712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125420160 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 125420224 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 578 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 576 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 116204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 117698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 117699 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 117773 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 117508 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 119859 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 124486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 126960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 126961 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 130063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 128617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 128618 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 130264 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 125937 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 125207 # Track reads on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 64552 # Tr system.physmem.perBankWrReqs::15 64187 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1015958077500 # Total gap between requests +system.physmem.totGap 1017016906500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959690 # Categorize read packet sizes +system.physmem.readPktSize::6 1959691 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,10 +92,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 1018058 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1654417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 206034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 74348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1654293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 74498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24401 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,10 +124,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 44264 # What write queue length does an incoming req see @@ -147,45 +147,45 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1724238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 110.484683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.063313 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.326643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1380958 80.09% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 190861 11.07% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 56628 3.28% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 27570 1.60% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15749 0.91% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1724249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 110.484089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.062986 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.322838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1380983 80.09% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 190835 11.07% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 56645 3.29% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 27563 1.60% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15745 0.91% 96.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-385 10044 0.58% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6620 0.38% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6559 0.38% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3696 0.21% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 2923 0.17% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2676 0.16% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2682 0.16% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1400 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1070 0.06% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1040 0.06% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 917 0.05% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6630 0.38% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6555 0.38% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3694 0.21% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 2928 0.17% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2668 0.15% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2688 0.16% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1402 0.08% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1069 0.06% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1034 0.06% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 922 0.05% 99.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 816 0.05% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 821 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 760 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 818 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 762 0.04% 99.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280-1281 561 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 626 0.04% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 627 0.04% 99.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1408-1409 841 0.05% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3634 0.21% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 546 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 235 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 177 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3636 0.21% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 543 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 234 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 178 0.01% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::1728-1729 137 0.01% 99.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::1792-1793 143 0.01% 99.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation @@ -197,10 +197,10 @@ system.physmem.bytesPerActivate::2176-2177 67 0.00% 99.82% # system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 60 0.00% 99.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 57 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 45 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 58 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 44 0.00% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::2560-2561 52 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::2752-2753 29 0.00% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.85% # Bytes accessed per row activation @@ -208,7 +208,7 @@ system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.85% # system.physmem.bytesPerActivate::2944-2945 31 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3009 19 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 27 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 23 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 22 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3200-3201 16 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3264-3265 31 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3328-3329 31 0.00% 99.87% # Bytes accessed per row activation @@ -228,8 +228,8 @@ system.physmem.bytesPerActivate::4160-4161 8 0.00% 99.88% # system.physmem.bytesPerActivate::4224-4225 8 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352-4353 24 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 11 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 9 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544-4545 18 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.88% # Bytes accessed per row activation @@ -266,8 +266,8 @@ system.physmem.bytesPerActivate::6592-6593 4 0.00% 99.90% # system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6720-6721 6 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 8 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7040-7041 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.90% # Bytes accessed per row activation @@ -288,73 +288,73 @@ system.physmem.bytesPerActivate::8000-8001 19 0.00% 99.92% # system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 14 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1430 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1724238 # Bytes accessed per row activation -system.physmem.totQLat 33987005500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 98689973000 # Sum of mem lat for all requests -system.physmem.totBusLat 9795560000 # Total cycles spent in databus access -system.physmem.totBankLat 54907407500 # Total cycles spent in bank access -system.physmem.avgQLat 17348.17 # Average queueing delay per request -system.physmem.avgBankLat 28026.68 # Average bank access latency per request +system.physmem.bytesPerActivate::total 1724249 # Bytes accessed per row activation +system.physmem.totQLat 33963917000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 98664809500 # Sum of mem lat for all requests +system.physmem.totBusLat 9795575000 # Total cycles spent in databus access +system.physmem.totBankLat 54905317500 # Total cycles spent in bank access +system.physmem.avgQLat 17336.36 # Average queueing delay per request +system.physmem.avgBankLat 28025.57 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50374.85 # Average memory access latency -system.physmem.avgRdBW 123.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 64.13 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 123.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 64.13 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 50361.93 # Average memory access latency +system.physmem.avgRdBW 123.32 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 64.07 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 123.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 64.07 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.47 # Data bus utilization in percentage +system.physmem.busUtil 1.46 # Data bus utilization in percentage system.physmem.avgRdQLen 0.10 # Average read queue length over time system.physmem.avgWrQLen 10.57 # Average write queue length over time -system.physmem.readRowHits 900967 # Number of row buffer hits during reads -system.physmem.writeRowHits 351956 # Number of row buffer hits during writes +system.physmem.readRowHits 900981 # Number of row buffer hits during reads +system.physmem.writeRowHits 351934 # Number of row buffer hits during writes system.physmem.readRowHitRate 45.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate 34.57 # Row buffer hit rate for writes -system.physmem.avgGap 341183.36 # Average gap between requests -system.membus.throughput 187582407 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1178392 # Transaction distribution -system.membus.trans_dist::ReadResp 1178392 # Transaction distribution +system.physmem.avgGap 341538.83 # Average gap between requests +system.membus.throughput 187387172 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178393 # Transaction distribution +system.membus.trans_dist::ReadResp 1178393 # Transaction distribution system.membus.trans_dist::Writeback 1018058 # Transaction distribution system.membus.trans_dist::ReadExReq 781298 # Transaction distribution system.membus.trans_dist::ReadExResp 781298 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 4937438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 4937438 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575872 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 190575872 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190575872 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 4937440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4937440 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 190575936 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190575936 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11748266000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11803876500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18466425750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18471159750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.branchPred.lookups 326521750 # Number of BP lookups -system.cpu.branchPred.condPredicted 252556520 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138229412 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220084071 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135399986 # Number of BTB hits +system.cpu.branchPred.lookups 326564713 # Number of BP lookups +system.cpu.branchPred.condPredicted 252601424 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138218301 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 218593713 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135545625 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.521938 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 62.008016 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444838557 # DTB read hits +system.cpu.dtb.read_hits 444840309 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449735635 # DTB read accesses -system.cpu.dtb.write_hits 160846849 # DTB write hits +system.cpu.dtb.read_accesses 449737387 # DTB read accesses +system.cpu.dtb.write_hits 160847153 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162548153 # DTB write accesses -system.cpu.dtb.data_hits 605685406 # DTB hits +system.cpu.dtb.write_accesses 162548457 # DTB write accesses +system.cpu.dtb.data_hits 605687462 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612283788 # DTB accesses -system.cpu.itb.fetch_hits 231915406 # ITB hits +system.cpu.dtb.data_accesses 612285844 # DTB accesses +system.cpu.itb.fetch_hits 231947501 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231915428 # ITB accesses +system.cpu.itb.fetch_accesses 231947523 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -368,34 +368,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2031916272 # number of cpu cycles simulated +system.cpu.numCycles 2034033960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172213740 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154308010 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667655233 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172359749 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154204964 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667587623 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043857850 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043790240 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651713796 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884761 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120483996 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11146958 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131630954 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83569020 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.166808 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139383608 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651716905 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884714 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120522396 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11097447 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131619843 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83580106 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.161652 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139337588 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742160374 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742086287 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533550 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 460194055 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571722217 # Number of cycles cpu stages are processed. -system.cpu.activity 77.351722 # Percentage of cycles cpu is active +system.cpu.timesIdled 7521644 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 462344107 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571689853 # Number of cycles cpu stages are processed. +system.cpu.activity 77.269597 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -407,211 +407,211 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.116572 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.117736 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.116572 # CPI: Total CPI of All Threads -system.cpu.ipc 0.895598 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.117736 # CPI: Total CPI of All Threads +system.cpu.ipc 0.894666 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.895598 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 845299879 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186616393 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.398882 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1098097789 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933818483 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.957528 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1059529924 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972386348 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 47.855631 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1622292075 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409624197 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.159502 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 1010582157 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021334115 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.264577 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 668.704565 # Cycle average of tags in use -system.cpu.icache.total_refs 231914267 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269981.684517 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 668.704565 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.326516 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.326516 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231914267 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231914267 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231914267 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231914267 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231914267 # number of overall hits -system.cpu.icache.overall_hits::total 231914267 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses -system.cpu.icache.overall_misses::total 1139 # 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number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231915406 # number of overall (read+write) accesses +system.cpu.ipc_total 0.894666 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 847369948 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186664012 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.340423 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1100283558 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933750402 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.906333 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1061657822 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972376138 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 47.805305 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1624406509 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409627451 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.138673 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 1012697898 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021336062 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.212341 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 668.751330 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 231946364 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 270019.050058 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 668.751330 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.326539 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.326539 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231946364 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231946364 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231946364 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231946364 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231946364 # number of overall hits +system.cpu.icache.overall_hits::total 231946364 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1137 # 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number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231947501 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231947501 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72548.726953 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72548.726953 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72548.726953 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72548.726953 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72548.726953 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72548.726953 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72550.791557 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72550.791557 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72550.791557 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72550.791557 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 162 # 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number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 278 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 278 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 278 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 278 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 278 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 64913500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 64913500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 64913500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 64913500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 64913500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 64913500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65194000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 65194000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65194000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 65194000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65194000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 65194000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75568.684517 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75568.684517 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75568.684517 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75568.684517 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75568.684517 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75568.684517 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75895.227008 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75895.227008 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75895.227008 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75895.227008 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75895.227008 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75895.227008 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 806684389 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 805844654 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7222689 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7222689 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3693280 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3693279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889621 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916176 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 21917894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916181 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21917899 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819502592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 819557568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819557568 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819502720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 819557696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819557696 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 10096073500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1288500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1466500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13667172000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.l2cache.replacements 1926959 # number of replacements -system.cpu.l2cache.tagsinuse 30929.406479 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8958686 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1956752 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.578345 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 67679483750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14929.609549 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.376091 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15965.420838 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.455616 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001049 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.487226 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.943891 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6044297 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044297 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693280 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693280 # 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Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 67691760750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14923.938165 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.347502 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455442 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.487444 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943935 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6044296 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044296 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693279 # 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number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111448 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112307 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111451 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112310 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111448 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112307 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111451 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112310 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413469 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413469 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163152 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413468 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413468 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.214986 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.215060 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.027939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88164.973296 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 88155.058758 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101135.001626 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101135.001626 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74564.027939 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93338.189971 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93329.960606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74564.027939 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93338.189971 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93329.960606 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74890.570431 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88394.302840 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88384.459174 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101327.212856 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101327.212856 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74890.570431 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93552.711897 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93544.531638 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74890.570431 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93552.711897 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93544.531638 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,83 +623,83 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 1018058 # number of writebacks system.cpu.l2cache.writebacks::total 1018058 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177533 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1178392 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781298 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 781298 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69332641250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69332641250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53393500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158498901250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158552294750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53393500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158498901250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158552294750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958832 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959691 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53514000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 89157154500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89210668500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69321257750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69321257750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158478412250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158531926250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53514000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158478412250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158531926250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413469 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413469 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413468 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413468 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62157.741560 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75722.939400 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75713.050920 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88740.328594 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88740.328594 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62157.741560 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80915.046398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80906.824421 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62157.741560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80915.046398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80906.824421 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62298.020955 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75715.142408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75705.361878 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88725.758609 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88725.758609 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107352 # number of replacements -system.cpu.dcache.tagsinuse 4082.468819 # Cycle average of tags in use -system.cpu.dcache.total_refs 593298146 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.115682 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12678178000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.468819 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996696 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996696 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437268759 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268759 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156029387 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156029387 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593298146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593298146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593298146 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 260860363500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 449106891000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 449106891000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 449106891000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 449106891000 # number of overall miss cycles +system.cpu.dcache.tags.replacements 9107355 # number of replacements +system.cpu.dcache.tags.tagsinuse 4082.476561 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 593297569 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111451 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.115597 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 12681367250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4082.476561 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996698 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156028804 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156028804 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593297569 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593297569 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593297569 # number of overall hits +system.cpu.dcache.overall_hits::total 593297569 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326898 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326898 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4699698 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4699698 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12026596 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12026596 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12026596 # number of overall misses +system.cpu.dcache.overall_misses::total 12026596 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 189082879500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 189082879500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 263051310000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 263051310000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 452134189500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 452134189500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 452134189500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 452134189500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -710,54 +710,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029236 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029236 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25692.506344 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25692.506344 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55512.657915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55512.657915 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37344.601817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37344.601817 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15563445 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7313446 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 432083 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 73150 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.019573 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 99.978756 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029240 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029240 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019868 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019868 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019868 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019868 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25806.675554 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25806.675554 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55971.960326 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55971.960326 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37594.527121 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37594.527121 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15699726 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7389800 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 434712 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 73152 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.115235 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 101.019794 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693280 # number of writebacks -system.cpu.dcache.writebacks::total 3693280 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2809939 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2809939 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2914571 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2914571 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2914571 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2914571 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 3693279 # number of writebacks +system.cpu.dcache.writebacks::total 3693279 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104626 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104626 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2810519 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2810519 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2915145 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2915145 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2915145 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2915145 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222272 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222272 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889176 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889176 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171613180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171613180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92147472000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92147472000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263760652000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 263760652000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263760652000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 263760652000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889179 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889179 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111451 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111451 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111451 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111451 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171880361750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171880361750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92301345750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92301345750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264181707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 264181707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264181707500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 264181707500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -766,14 +766,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23761.661150 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23761.661150 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48776.541730 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48776.541730 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23798.655292 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23798.655292 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48857.914337 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48857.914337 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 88a7eaf62..b939ad0cc 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.693021 # Number of seconds simulated -sim_ticks 693021015500 # Number of ticks simulated -final_tick 693021015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.694171 # Number of seconds simulated +sim_ticks 694171131000 # Number of ticks simulated +final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172458 # Simulator instruction rate (inst/s) -host_op_rate 172458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68844519 # Simulator tick rate (ticks/s) -host_mem_usage 228224 # Number of bytes of host memory used -host_seconds 10066.47 # Real time elapsed on the host +host_inst_rate 169313 # Simulator instruction rate (inst/s) +host_op_rate 169313 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67701038 # Simulator tick rate (ticks/s) +host_mem_usage 228220 # Number of bytes of host memory used +host_seconds 10253.48 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125798976 # Number of bytes read from this memory -system.physmem.bytes_read::total 125860352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65263616 # Number of bytes written to this memory -system.physmem.bytes_written::total 65263616 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965609 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966568 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019744 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019744 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 88563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 181522599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 181611162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 88563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 88563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 94172636 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 94172636 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 94172636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 88563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 181522599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 275783798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966568 # Total number of read requests seen -system.physmem.writeReqs 1019744 # Total number of write requests seen -system.physmem.cpureqs 2986322 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125860352 # Total number of bytes read from memory -system.physmem.bytesWritten 65263616 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125860352 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65263616 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 585 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125790400 # Number of bytes read from this memory +system.physmem.bytes_read::total 125852032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65261440 # Number of bytes written to this memory +system.physmem.bytes_written::total 65261440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965475 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966438 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019710 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019710 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 88785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 181209495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 181298280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 88785 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 88785 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94013475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94013475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94013475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 88785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 181209495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 275311755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966438 # Total number of read requests seen +system.physmem.writeReqs 1019710 # Total number of write requests seen +system.physmem.cpureqs 2986156 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125852032 # Total number of bytes read from memory +system.physmem.bytesWritten 65261440 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125852032 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65261440 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 561 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 119008 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 114438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 116555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 118046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 118149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 117808 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120225 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 124916 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 127564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 130488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 129072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 130765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 126644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 125671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 122973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123661 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61280 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 119011 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 114417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 116554 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 118021 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 118126 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 117795 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 124937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 127536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 130495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 129073 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 130794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 126583 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 125666 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 122963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123677 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 61282 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 61566 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 60655 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 61327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 61759 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 64220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 65486 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 65716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64323 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64319 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 64636 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64301 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 60662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 61309 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 61746 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 64226 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 65702 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 65470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 65888 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65399 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 65733 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64314 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 64641 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64291 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 693020927000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 694171008500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966568 # Categorize read packet sizes +system.physmem.readPktSize::6 1966438 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1019744 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1645883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 229621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20600 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019710 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1645970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 229492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20630 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -124,237 +124,237 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44296 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1725071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 110.744307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.207489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.283228 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1378927 79.93% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 191993 11.13% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 57386 3.33% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 28102 1.63% 96.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15937 0.92% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 9770 0.57% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6740 0.39% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6906 0.40% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3659 0.21% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3018 0.17% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2639 0.15% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2655 0.15% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1401 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1109 0.06% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1069 0.06% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 819 0.05% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 853 0.05% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 845 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 758 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 637 0.04% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 729 0.04% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 683 0.04% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3600 0.21% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 572 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 238 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 183 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 143 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 137 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 83 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 102 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 118 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 69 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 71 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 61 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 55 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 46 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 41 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 53 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 34 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 52 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 44 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 22 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 36 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 29 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 20 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 30 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 16 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 19 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1724767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 110.763752 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.212194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.511378 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1378543 79.93% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 191920 11.13% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 57620 3.34% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 28373 1.65% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15698 0.91% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 9692 0.56% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6693 0.39% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6792 0.39% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3776 0.22% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 2960 0.17% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2630 0.15% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2677 0.16% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1390 0.08% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1126 0.07% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1092 0.06% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 878 0.05% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 859 0.05% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 813 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 757 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 627 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 709 0.04% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 705 0.04% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3570 0.21% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 579 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 253 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 194 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 146 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 142 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 94 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 85 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 102 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 71 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 61 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 59 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 49 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 59 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 39 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 46 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 39 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 28 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 48 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 43 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 24 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 22 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 32 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 25 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 21 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 25 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 26 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 19 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 25 0.00% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::3712-3713 10 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 20 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 25 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 16 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 13 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 23 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 19 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 7 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 9 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 11 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 5 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 17 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 4 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 26 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 21 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 6 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 16 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 14 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 28 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 7 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 9 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 14 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 10 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 12 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 10 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 21 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 7 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 7 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 19 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6336-6337 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7168-7169 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 15 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 118 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 15 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 12 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 16 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1427 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1725071 # Bytes accessed per row activation -system.physmem.totQLat 33871310750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 97989140750 # Sum of mem lat for all requests -system.physmem.totBusLat 9829915000 # Total cycles spent in databus access -system.physmem.totBankLat 54287915000 # Total cycles spent in bank access -system.physmem.avgQLat 17228.69 # Average queueing delay per request -system.physmem.avgBankLat 27613.62 # Average bank access latency per request +system.physmem.bytesPerActivate::7232-7233 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 17 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 123 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 12 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 18 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1429 0.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1724767 # Bytes accessed per row activation +system.physmem.totQLat 33917679750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 98022206000 # Sum of mem lat for all requests +system.physmem.totBusLat 9829385000 # Total cycles spent in databus access +system.physmem.totBankLat 54275141250 # Total cycles spent in bank access +system.physmem.avgQLat 17253.21 # Average queueing delay per request +system.physmem.avgBankLat 27608.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 49842.31 # Average memory access latency -system.physmem.avgRdBW 181.61 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 94.17 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 181.61 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 94.17 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 49861.82 # Average memory access latency +system.physmem.avgRdBW 181.30 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 94.01 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 181.30 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 94.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 11.24 # Average write queue length over time -system.physmem.readRowHits 907929 # Number of row buffer hits during reads -system.physmem.writeRowHits 352711 # Number of row buffer hits during writes -system.physmem.readRowHitRate 46.18 # Row buffer hit rate for reads +system.physmem.avgWrQLen 10.67 # Average write queue length over time +system.physmem.readRowHits 908058 # Number of row buffer hits during reads +system.physmem.writeRowHits 352757 # Number of row buffer hits during writes +system.physmem.readRowHitRate 46.19 # Row buffer hit rate for reads system.physmem.writeRowHitRate 34.59 # Row buffer hit rate for writes -system.physmem.avgGap 232065.81 # Average gap between requests -system.membus.throughput 275783798 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191455 # Transaction distribution -system.membus.trans_dist::ReadResp 1191455 # Transaction distribution -system.membus.trans_dist::Writeback 1019744 # Transaction distribution -system.membus.trans_dist::ReadExReq 775113 # Transaction distribution -system.membus.trans_dist::ReadExResp 775113 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 4952880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 4952880 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191123968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 191123968 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191123968 # Total data (bytes) +system.physmem.avgGap 232463.70 # Average gap between requests +system.membus.throughput 275311755 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191259 # Transaction distribution +system.membus.trans_dist::ReadResp 1191259 # Transaction distribution +system.membus.trans_dist::Writeback 1019710 # Transaction distribution +system.membus.trans_dist::ReadExReq 775179 # Transaction distribution +system.membus.trans_dist::ReadExResp 775179 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4952586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4952586 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191113472 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 191113472 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191113472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11815530000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11881655250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18578292500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18594236500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.branchPred.lookups 381829258 # Number of BP lookups -system.cpu.branchPred.condPredicted 296791594 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16090940 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262534664 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259935463 # Number of BTB hits +system.cpu.branchPred.lookups 381853679 # Number of BP lookups +system.cpu.branchPred.condPredicted 296812462 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16082560 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 263010897 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259938392 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.009959 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24706233 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3077 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.831796 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24703686 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3043 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613998993 # DTB read hits -system.cpu.dtb.read_misses 11257757 # DTB read misses +system.cpu.dtb.read_hits 613967200 # DTB read hits +system.cpu.dtb.read_misses 11252585 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625256750 # DTB read accesses -system.cpu.dtb.write_hits 212346659 # DTB write hits -system.cpu.dtb.write_misses 7132839 # DTB write misses +system.cpu.dtb.read_accesses 625219785 # DTB read accesses +system.cpu.dtb.write_hits 212300531 # DTB write hits +system.cpu.dtb.write_misses 7117395 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219479498 # DTB write accesses -system.cpu.dtb.data_hits 826345652 # DTB hits -system.cpu.dtb.data_misses 18390596 # DTB misses +system.cpu.dtb.write_accesses 219417926 # DTB write accesses +system.cpu.dtb.data_hits 826267731 # DTB hits +system.cpu.dtb.data_misses 18369980 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844736248 # DTB accesses -system.cpu.itb.fetch_hits 391092043 # ITB hits -system.cpu.itb.fetch_misses 41 # ITB misses +system.cpu.dtb.data_accesses 844637711 # DTB accesses +system.cpu.itb.fetch_hits 391085180 # ITB hits +system.cpu.itb.fetch_misses 51 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391092084 # ITB accesses +system.cpu.itb.fetch_accesses 391085231 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -368,238 +368,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1386042032 # number of cpu cycles simulated +system.cpu.numCycles 1388342263 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402569601 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3162430835 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381829258 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284641696 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574759222 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140771117 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 196436536 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1508 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 391092043 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8064861 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1290645563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.450271 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141948 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402551684 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3162454030 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381853679 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284642078 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574754052 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140783496 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 197047269 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1488 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 391085180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8065065 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1291251504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.449139 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141692 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 715886341 55.47% 55.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42669337 3.31% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21804756 1.69% 60.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39713212 3.08% 63.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129418344 10.03% 73.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61537126 4.77% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38572706 2.99% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28132820 2.18% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212910921 16.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 716497452 55.49% 55.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42682670 3.31% 58.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21784053 1.69% 60.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39696423 3.07% 63.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129425846 10.02% 73.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61545626 4.77% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38574460 2.99% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28124081 2.18% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212920893 16.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1290645563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275482 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.281627 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434522823 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 177728995 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542687123 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18828896 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116877726 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58348631 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 887 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3089538872 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2030 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116877726 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457522679 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 122552150 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7258 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535724767 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 57960983 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3007258855 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 610716 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1836419 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51661727 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2248310547 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3900270173 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3899027162 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1243011 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1291251504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275043 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.277863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434540420 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 178303124 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542717448 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18794331 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116896181 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58354479 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 840 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3089587827 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116896181 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457532531 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 123212849 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5836 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535730171 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 57873936 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3007379456 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 610253 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1826446 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51579864 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2248363732 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3900421320 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3899178783 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1242537 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 872107584 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 171 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 169 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123506231 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679721710 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255512825 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67679975 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36990562 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2725376863 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 131 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509736857 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3186715 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 980131211 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 416747410 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 102 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1290645563 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.944559 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.970905 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 872160769 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 168 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 168 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123444205 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679751883 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255539846 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68026727 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37555626 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2725485841 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509620077 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3191439 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 980254556 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 417071077 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 94 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1291251504 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.943556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971187 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 448740391 34.77% 34.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203240605 15.75% 50.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185935244 14.41% 64.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153422938 11.89% 76.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133053941 10.31% 87.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80846786 6.26% 93.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65044265 5.04% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15249478 1.18% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5111915 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 449456095 34.81% 34.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203314241 15.75% 50.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185688017 14.38% 64.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153487226 11.89% 76.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133078124 10.31% 87.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80722513 6.25% 93.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65115490 5.04% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15268261 1.18% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5121537 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1290645563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1291251504 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2163556 11.71% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11907011 64.43% 76.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4409853 23.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2192750 11.84% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11923038 64.36% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4410634 23.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643982989 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 270 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 158 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641664411 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224088858 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643953882 65.51% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 266 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 35 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641631628 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224033966 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509736857 # Type of FU issued -system.cpu.iq.rate 1.810722 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18480420 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007363 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6329888754 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3704398033 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413211688 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1897658 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1216996 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850977 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527279284 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 937993 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62596809 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509620077 # Type of FU issued +system.cpu.iq.rate 1.807638 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18526422 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6330307505 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3704630064 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413135648 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1902014 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217951 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 852306 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527206104 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 940395 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62612888 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235126047 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263685 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 108576 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94784323 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235156220 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263801 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 109236 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94811344 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 179 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1583083 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 161 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1579414 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116877726 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 58990263 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1298967 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2867530467 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8941640 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679721710 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255512825 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 325521 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17838 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 108576 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10366897 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8557633 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18924530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462313409 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625257301 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47423448 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116896181 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 59627165 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1293281 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2867673451 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8945086 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679751883 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255539846 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 123 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 277586 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17880 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 109236 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10358298 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8554506 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18912804 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462213177 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625220360 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47406900 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142153473 # number of nop insts executed -system.cpu.iew.exec_refs 844736823 # number of memory reference insts executed -system.cpu.iew.exec_branches 300880868 # Number of branches executed -system.cpu.iew.exec_stores 219479522 # Number of stores executed -system.cpu.iew.exec_rate 1.776507 # Inst execution rate -system.cpu.iew.wb_sent 2442002538 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2414062665 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388567182 # num instructions producing a value -system.cpu.iew.wb_consumers 1764588303 # num instructions consuming a value +system.cpu.iew.exec_nop 142187487 # number of nop insts executed +system.cpu.iew.exec_refs 844638305 # number of memory reference insts executed +system.cpu.iew.exec_branches 300894564 # Number of branches executed +system.cpu.iew.exec_stores 219417945 # Number of stores executed +system.cpu.iew.exec_rate 1.773491 # Inst execution rate +system.cpu.iew.wb_sent 2441919357 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413987954 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388436926 # num instructions producing a value +system.cpu.iew.wb_consumers 1764428707 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.741695 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back +system.cpu.iew.wb_rate 1.738756 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786905 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 827045847 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 827192555 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16090137 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1173767837 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.550375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.495661 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16081773 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1174355323 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.549599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.495377 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 659878599 56.22% 56.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174801477 14.89% 71.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86143733 7.34% 78.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53556827 4.56% 83.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34704625 2.96% 85.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26036675 2.22% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21629651 1.84% 90.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22889079 1.95% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94127171 8.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 660542597 56.25% 56.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174710504 14.88% 71.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86129545 7.33% 78.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53592661 4.56% 83.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34688707 2.95% 85.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26049111 2.22% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21601989 1.84% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22901440 1.95% 91.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94138769 8.02% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1173767837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1174355323 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -610,209 +610,209 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94127171 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94138769 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3640687439 # The number of ROB reads -system.cpu.rob.rob_writes 5410628429 # The number of ROB writes -system.cpu.timesIdled 939185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 95396469 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3641410035 # The number of ROB reads +system.cpu.rob.rob_writes 5410940495 # The number of ROB writes +system.cpu.timesIdled 938493 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 97090759 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.798391 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.798391 # CPI: Total CPI of All Threads -system.cpu.ipc 1.252519 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.252519 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318270268 # number of integer regfile reads -system.cpu.int_regfile_writes 1932125497 # number of integer regfile writes -system.cpu.fp_regfile_reads 30353 # number of floating regfile reads +system.cpu.cpi 0.799716 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.799716 # CPI: Total CPI of All Threads +system.cpu.ipc 1.250444 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.250444 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318091757 # number of integer regfile reads +system.cpu.int_regfile_writes 1932096202 # number of integer regfile writes +system.cpu.fp_regfile_reads 30725 # number of floating regfile reads system.cpu.fp_regfile_writes 534 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1191881478 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3724968 # Transaction distribution +system.cpu.toL2Bus.throughput 1189905456 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3725037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085580 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 22087498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825937536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 825998912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 825998912 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1926 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085475 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 22087401 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825936384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 825998016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 825998016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178169165 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10178230165 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1438500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1633750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13770459000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14189007000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 768.731270 # Cycle average of tags in use -system.cpu.icache.total_refs 391090558 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 959 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 407810.800834 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 768.731270 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375357 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375357 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 391090558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391090558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391090558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391090558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391090558 # number of overall hits -system.cpu.icache.overall_hits::total 391090558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1484 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1484 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1484 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1484 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1484 # number of overall misses -system.cpu.icache.overall_misses::total 1484 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 114408499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 114408499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 114408499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 114408499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 114408499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 114408499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391092042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391092042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391092042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391092042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391092042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391092042 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 770.551884 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391083687 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 406109.747664 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 770.551884 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376246 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376246 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 391083687 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391083687 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391083687 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391083687 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391083687 # number of overall hits +system.cpu.icache.overall_hits::total 391083687 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1493 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1493 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1493 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1493 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1493 # number of overall misses +system.cpu.icache.overall_misses::total 1493 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108163750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108163750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108163750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108163750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108163750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108163750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391085180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391085180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391085180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391085180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391085180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391085180 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77094.675876 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77094.675876 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77094.675876 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77094.675876 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77094.675876 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77094.675876 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1730 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72447.253851 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72447.253851 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72447.253851 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72447.253851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72447.253851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72447.253851 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 340 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 346 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 525 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 525 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 525 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 525 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 525 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 525 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 959 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965475 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966438 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 61969250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96454947000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96516916250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62065331750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62065331750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61969250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158520278750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158582248000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61969250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158520278750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158582248000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163156 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163266 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411499 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411499 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163130 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163241 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411534 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411534 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214194 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214099 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214181 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214194 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70526.329510 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81054.887627 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81046.413209 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79976.634697 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79976.634697 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70526.329510 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80629.692248 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80624.765327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70526.329510 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80629.692248 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80624.765327 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214099 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214181 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64350.207684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81034.420850 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81020.933525 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80065.806414 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80065.806414 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64350.207684 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80652.401455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80644.417978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64350.207684 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80652.401455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80644.417978 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176210 # number of replacements -system.cpu.dcache.tagsinuse 4087.713956 # Cycle average of tags in use -system.cpu.dcache.total_refs 694263707 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180306 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.625334 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5139692000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.713956 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997977 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997977 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538720806 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538720806 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155542899 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155542899 # number of WriteReq hits +system.cpu.dcache.tags.replacements 9176123 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.719090 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694209653 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180219 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.620163 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5145271250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.719090 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997978 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997978 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538667558 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538667558 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155542093 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155542093 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694263705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694263705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694263705 # number of overall hits -system.cpu.dcache.overall_hits::total 694263705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11385401 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11385401 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5185603 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5185603 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 694209651 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694209651 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694209651 # number of overall hits +system.cpu.dcache.overall_hits::total 694209651 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11383512 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11383512 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5186409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5186409 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16571004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16571004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16571004 # number of overall misses -system.cpu.dcache.overall_misses::total 16571004 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 352412462500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 352412462500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 293618457575 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 293618457575 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 646030920075 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 646030920075 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 646030920075 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 646030920075 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550106207 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550106207 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16569921 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16569921 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16569921 # number of overall misses +system.cpu.dcache.overall_misses::total 16569921 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 354593331250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 354593331250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 296662127899 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 296662127899 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 461500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 461500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 651255459149 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 651255459149 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 651255459149 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 651255459149 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550051070 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550051070 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710834709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710834709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710834709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710834709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020697 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020697 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032263 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032263 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 710779572 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710779572 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710779572 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710779572 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020695 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020695 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032268 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.023312 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.023312 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.023312 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.023312 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30953.012766 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30953.012766 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56621.854310 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56621.854310 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38985.623326 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38985.623326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38985.623326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38985.623326 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13659344 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8231616 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 745438 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.323917 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 126.379710 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31149.730527 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31149.730527 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57199.909976 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57199.909976 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 461500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 461500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39303.473997 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39303.473997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39303.473997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39303.473997 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13761211 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8306103 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 744858 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.474946 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 127.521348 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3724968 # number of writebacks -system.cpu.dcache.writebacks::total 3724968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4088719 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4088719 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3301980 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3301980 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7390699 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7390699 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7390699 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7390699 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296682 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296682 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883623 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883623 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725037 # number of writebacks +system.cpu.dcache.writebacks::total 3725037 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4086921 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4086921 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302782 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3302782 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7389703 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7389703 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7389703 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7389703 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883627 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883627 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180305 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180305 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180305 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180305 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180470424000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 180470424000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85065304522 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85065304522 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265535728522 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 265535728522 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265535728522 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 265535728522 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180218 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180218 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180218 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180218 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180738700500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 180738700500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85282559486 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85282559486 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 459500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 459500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 266021259986 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 266021259986 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 266021259986 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 266021259986 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013265 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013265 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24733.217646 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24733.217646 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45160.472410 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45160.472410 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012916 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012916 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012916 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012916 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24770.293484 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24770.293484 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45275.715142 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45275.715142 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 459500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 459500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28977.662620 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28977.662620 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28977.662620 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28977.662620 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 4fe8387b5..72597a7eb 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 5246772452 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.458646 # Cycle average of tags in use -system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926937 # number of replacements -system.cpu.l2cache.tagsinuse 30535.257456 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8959453 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1956729 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.578791 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926937 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits @@ -318,15 +318,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use -system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9107638 # number of replacements +system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 48447911f..3d9ea108c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.540696 # Number of seconds simulated -sim_ticks 540696400000 # Number of ticks simulated -final_tick 540696400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541686 # Number of seconds simulated +sim_ticks 541686426500 # Number of ticks simulated +final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169038 # Simulator instruction rate (inst/s) -host_op_rate 188575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59174301 # Simulator tick rate (ticks/s) -host_mem_usage 246336 # Number of bytes of host memory used -host_seconds 9137.35 # Real time elapsed on the host +host_inst_rate 161069 # Simulator instruction rate (inst/s) +host_op_rate 179684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56487595 # Simulator tick rate (ticks/s) +host_mem_usage 246340 # Number of bytes of host memory used +host_seconds 9589.48 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143740608 # Number of bytes read from this memory -system.physmem.bytes_read::total 143788736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143725568 # Number of bytes read from this memory +system.physmem.bytes_read::total 143773696 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70441600 # Number of bytes written to this memory -system.physmem.bytes_written::total 70441600 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 70430528 # Number of bytes written to this memory +system.physmem.bytes_written::total 70430528 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245947 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246699 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100650 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100650 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 265843471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 265932483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89011 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89011 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 130279395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 130279395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 130279395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 265843471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 396211878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246699 # Total number of read requests seen -system.physmem.writeReqs 1100650 # Total number of write requests seen -system.physmem.cpureqs 3347359 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143788736 # Total number of bytes read from memory -system.physmem.bytesWritten 70441600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143788736 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70441600 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 675 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 2245712 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246464 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100477 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100477 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 88848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 265329831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 265418679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 88848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 88848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 130020847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 130020847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 130020847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 88848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 265329831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 395439526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246464 # Total number of read requests seen +system.physmem.writeReqs 1100477 # Total number of write requests seen +system.physmem.cpureqs 3346951 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143773696 # Total number of bytes read from memory +system.physmem.bytesWritten 70430528 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143773696 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 599 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 139594 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 136159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 133894 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 136244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 134956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 135313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 136207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 136262 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 143860 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 146526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 144286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 146187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 145855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 146147 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 142095 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 142439 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 67412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 65719 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 66245 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 66183 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 66419 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 67973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68813 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 70394 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 70993 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 70492 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 70984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 70346 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70810 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69131 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 139699 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 136238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 133756 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 136368 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 134718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 135333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 136160 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 136095 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 143598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 146293 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 144461 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 146176 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 145883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 146345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 142220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 142522 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 67428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 65656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 66333 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 66095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 66425 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 67930 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68755 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 70311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 70943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 70521 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 70921 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 70374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70896 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69672 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69074 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 540696152000 # Total gap between requests +system.physmem.totGap 541686363500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246699 # Categorize read packet sizes +system.physmem.readPktSize::6 2246464 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1100650 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1614963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 444775 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 139732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100477 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1615292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 444627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 139018 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,217 +124,217 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1997676 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.204860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.811800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 283.656472 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1593756 79.78% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 230264 11.53% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 68043 3.41% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32667 1.64% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 17678 0.88% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10939 0.55% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7434 0.37% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7476 0.37% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4079 0.20% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3182 0.16% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2817 0.14% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2754 0.14% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1425 0.07% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1138 0.06% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 999 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 880 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 791 0.04% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 732 0.04% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 642 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 540 0.03% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 574 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 838 0.04% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3581 0.18% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 454 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 187 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 173 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 114 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 112 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 90 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 76 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 95 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 66 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 55 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 44 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 45 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 44 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 34 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 42 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 31 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 29 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 30 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 32 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 28 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 35 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 28 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 31 0.00% 99.88% # Bytes accessed per row activation +system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1997603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.193624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.812437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 283.653287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1593724 79.78% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 230021 11.51% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 68328 3.42% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 32466 1.63% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 17759 0.89% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 11013 0.55% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7534 0.38% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 7551 0.38% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3933 0.20% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3162 0.16% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2715 0.14% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2783 0.14% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1408 0.07% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1190 0.06% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1060 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 829 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 802 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 757 0.04% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 590 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 531 0.03% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 601 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 798 0.04% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3587 0.18% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 465 0.02% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 167 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 158 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 120 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 86 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 82 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 107 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 81 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 77 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 52 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 39 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 40 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 36 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 29 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 41 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 32 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 31 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 29 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 30 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 18 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136-3137 33 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 18 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 21 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 16 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 19 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 18 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 11 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 17 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 17 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 21 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 17 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 17 0.00% 99.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::3904-3905 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 29 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 20 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 29 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 17 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 31 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 28 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 33 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 14 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 16 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 17 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 15 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 12 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 21 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 17 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 9 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::6208-6209 17 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272-6273 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 15 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 16 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 10 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 9 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 9 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 15 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 14 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 8 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 9 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 9 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 124 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 13 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 13 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 8 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 7 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 7 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 122 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 8 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 6 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 8 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 12 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 22 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1443 0.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1997676 # Bytes accessed per row activation -system.physmem.totQLat 50306526000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 124453758500 # Sum of mem lat for all requests -system.physmem.totBusLat 11230120000 # Total cycles spent in databus access -system.physmem.totBankLat 62917112500 # Total cycles spent in bank access -system.physmem.avgQLat 22398.04 # Average queueing delay per request -system.physmem.avgBankLat 28012.66 # Average bank access latency per request +system.physmem.bytesPerActivate::8064-8065 8 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 20 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1459 0.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1997603 # Bytes accessed per row activation +system.physmem.totQLat 50283923250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 124431529500 # Sum of mem lat for all requests +system.physmem.totBusLat 11229325000 # Total cycles spent in databus access +system.physmem.totBankLat 62918281250 # Total cycles spent in bank access +system.physmem.avgQLat 22389.56 # Average queueing delay per request +system.physmem.avgBankLat 28015.17 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55410.70 # Average memory access latency -system.physmem.avgRdBW 265.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 130.28 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 265.93 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 130.28 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 55404.72 # Average memory access latency +system.physmem.avgRdBW 265.42 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 130.02 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 265.42 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 130.02 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.10 # Data bus utilization in percentage +system.physmem.busUtil 3.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.23 # Average read queue length over time -system.physmem.avgWrQLen 10.44 # Average write queue length over time -system.physmem.readRowHits 1005962 # Number of row buffer hits during reads -system.physmem.writeRowHits 343028 # Number of row buffer hits during writes -system.physmem.readRowHitRate 44.79 # Row buffer hit rate for reads +system.physmem.avgWrQLen 10.65 # Average write queue length over time +system.physmem.readRowHits 1005654 # Number of row buffer hits during reads +system.physmem.writeRowHits 343066 # Number of row buffer hits during writes +system.physmem.readRowHitRate 44.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes -system.physmem.avgGap 161529.66 # Average gap between requests -system.membus.throughput 396211878 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420214 # Transaction distribution -system.membus.trans_dist::ReadResp 1420214 # Transaction distribution -system.membus.trans_dist::Writeback 1100650 # Transaction distribution -system.membus.trans_dist::ReadExReq 826485 # Transaction distribution -system.membus.trans_dist::ReadExResp 826485 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 5594048 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 5594048 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214230336 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 214230336 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214230336 # Total data (bytes) +system.physmem.avgGap 161845.21 # Average gap between requests +system.membus.throughput 395439408 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420071 # Transaction distribution +system.membus.trans_dist::ReadResp 1420070 # Transaction distribution +system.membus.trans_dist::Writeback 1100477 # Transaction distribution +system.membus.trans_dist::ReadExReq 826393 # Transaction distribution +system.membus.trans_dist::ReadExResp 826393 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 5593404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 5593404 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214204160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 214204160 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214204160 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12859707750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12928469250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21134071500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 21152142500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.9 # Layer utilization (%) -system.cpu.branchPred.lookups 304230401 # Number of BP lookups -system.cpu.branchPred.condPredicted 250450611 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15192997 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 172575058 # Number of BTB lookups -system.cpu.branchPred.BTBHits 162497547 # Number of BTB hits +system.cpu.branchPred.lookups 304298989 # Number of BP lookups +system.cpu.branchPred.condPredicted 250519406 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15198708 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 177303182 # Number of BTB lookups +system.cpu.branchPred.BTBHits 162516904 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.160506 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17547944 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 207 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.660455 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17540360 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 213 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -378,132 +378,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1081392801 # number of cpu cycles simulated +system.cpu.numCycles 1083372854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 300338229 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2194868023 # Number of instructions fetch has processed -system.cpu.fetch.Branches 304230401 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 180045491 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 436913465 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88946702 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 165329116 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 33 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 290586210 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6069176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 973112936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494450 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.204820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 300343787 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2195221955 # Number of instructions fetch has processed +system.cpu.fetch.Branches 304298989 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180057264 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436998042 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88977352 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 165479201 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 101 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 290623561 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6109702 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 973376815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.204787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536199557 55.10% 55.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25797166 2.65% 57.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39079992 4.02% 61.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48369850 4.97% 66.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43937617 4.52% 71.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46464611 4.77% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38405061 3.95% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19061800 1.96% 81.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175797282 18.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536378856 55.10% 55.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25841118 2.65% 57.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39079231 4.01% 61.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48353852 4.97% 66.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43959831 4.52% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46474608 4.77% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38397974 3.94% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19032697 1.96% 81.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175858648 18.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 973112936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281332 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.029668 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 332624022 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 143219561 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 406441589 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20296480 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70531284 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46039188 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 865 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2374316328 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2545 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70531284 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 356409274 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 71650111 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21139 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 401304268 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73196860 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2310523412 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 156231 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5060521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60179356 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 18 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2286636992 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10669420338 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10669417166 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3172 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 973376815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.280881 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.026285 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 332723748 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 143314435 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 406466996 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20316722 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70554914 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46046806 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 803 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2374638821 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2490 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70554914 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 356505375 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 71902909 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22171 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 401350772 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73040674 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2310606044 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 153145 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5003938 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60088597 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2286724696 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10669719595 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10669716841 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2754 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 580317062 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 904 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 901 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 161063694 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 625481573 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 221078320 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85817344 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70539912 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2205002740 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 913 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2019903116 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4041921 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 477338341 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1137890497 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 973112936 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.075713 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906230 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 580404766 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 862 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 859 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 161072397 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 625574992 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 221105439 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85703818 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70396970 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2205173654 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 876 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2020003765 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4023223 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 477517821 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1138229874 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 973376815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.075254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906645 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 289817184 29.78% 29.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153400597 15.76% 45.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161373326 16.58% 62.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120291643 12.36% 74.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123812966 12.72% 87.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73732869 7.58% 94.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38377982 3.94% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9754115 1.00% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2552254 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 290079957 29.80% 29.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153607537 15.78% 45.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161004232 16.54% 62.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120476061 12.38% 74.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123716545 12.71% 87.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73794754 7.58% 94.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38284776 3.93% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9892649 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2520304 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 973112936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 973376815 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 873823 3.65% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5574 0.02% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18262233 76.32% 80.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4786578 20.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 894925 3.74% 3.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5467 0.02% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18249723 76.22% 79.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4791929 20.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1237523467 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925246 0.05% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1237561423 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 924895 0.05% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued @@ -525,90 +525,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 44 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588384414 29.13% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193069911 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 588422338 29.13% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193095054 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2019903116 # Type of FU issued -system.cpu.iq.rate 1.867872 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23928208 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011846 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5040888987 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2682531512 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957653574 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 310 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 612 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 122 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2043831169 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 155 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64629118 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2020003765 # Type of FU issued +system.cpu.iq.rate 1.864551 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23942044 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011852 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5041349349 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2682881596 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957831333 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 100 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2043945677 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64652125 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 139554804 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 275861 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192692 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46231275 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 139648223 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271348 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192348 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46258394 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5362990 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 5367173 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70531284 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 34407025 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1609544 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2205003765 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7646058 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 625481573 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 221078320 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 851 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 482587 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 96102 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192692 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8138129 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9602458 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17740587 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988966025 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574553789 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30937091 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70554914 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34630118 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1599053 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2205174629 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7647376 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 625574992 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 221105439 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 814 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 476287 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97145 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192348 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8141918 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9600574 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17742492 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1989129664 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574576777 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30874101 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 112 # number of nop insts executed -system.cpu.iew.exec_refs 764737764 # number of memory reference insts executed -system.cpu.iew.exec_branches 238303653 # Number of branches executed -system.cpu.iew.exec_stores 190183975 # Number of stores executed -system.cpu.iew.exec_rate 1.839263 # Inst execution rate -system.cpu.iew.wb_sent 1966073864 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957653696 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295701173 # num instructions producing a value -system.cpu.iew.wb_consumers 2059307469 # num instructions consuming a value +system.cpu.iew.exec_nop 99 # number of nop insts executed +system.cpu.iew.exec_refs 764789002 # number of memory reference insts executed +system.cpu.iew.exec_branches 238317780 # Number of branches executed +system.cpu.iew.exec_stores 190212225 # Number of stores executed +system.cpu.iew.exec_rate 1.836053 # Inst execution rate +system.cpu.iew.wb_sent 1966244201 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957831433 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295814578 # num instructions producing a value +system.cpu.iew.wb_consumers 2059506895 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.810308 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629193 # average fanout of values written-back +system.cpu.iew.wb_rate 1.807163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629187 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 482029293 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 482200307 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15192188 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 902581652 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.909050 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.715598 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15197938 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 902821901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.908542 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.715709 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 414112551 45.88% 45.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193170118 21.40% 67.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72777120 8.06% 75.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35259342 3.91% 79.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18942446 2.10% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30787152 3.41% 84.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19991978 2.21% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11413503 1.26% 88.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106127442 11.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 414368116 45.90% 45.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193212165 21.40% 67.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72772864 8.06% 75.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35254508 3.90% 79.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18855841 2.09% 81.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30818249 3.41% 84.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19938130 2.21% 86.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11407177 1.26% 88.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106194851 11.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 902581652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 902821901 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -619,212 +619,212 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106127442 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106194851 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3001556757 # The number of ROB reads -system.cpu.rob.rob_writes 4480884032 # The number of ROB writes -system.cpu.timesIdled 1155619 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 108279865 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3001900611 # The number of ROB reads +system.cpu.rob.rob_writes 4481254115 # The number of ROB writes +system.cpu.timesIdled 1150610 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 109996039 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.700129 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.700129 # CPI: Total CPI of All Threads -system.cpu.ipc 1.428309 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.428309 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9959942925 # number of integer regfile reads -system.cpu.int_regfile_writes 1937523681 # number of integer regfile writes -system.cpu.fp_regfile_reads 126 # number of floating regfile reads -system.cpu.fp_regfile_writes 125 # number of floating regfile writes -system.cpu.misc_regfile_reads 737562736 # number of misc regfile reads +system.cpu.cpi 0.701411 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.701411 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425698 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.425698 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9960721721 # number of integer regfile reads +system.cpu.int_regfile_writes 1937694107 # number of integer regfile writes +system.cpu.fp_regfile_reads 91 # number of floating regfile reads +system.cpu.fp_regfile_writes 89 # number of floating regfile writes +system.cpu.misc_regfile_reads 737621013 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1584099202 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7708436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7708436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3781153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893485 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1562 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22983433 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 22984995 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 49984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856466752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 856516736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes) +system.cpu.toL2Bus.throughput 1581534685 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709687 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3782769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893417 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22987414 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 22988978 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856645824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 856695872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856695872 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10472863577 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10475876330 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1171999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1321749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14401713992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14846430743 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 627.830229 # Cycle average of tags in use -system.cpu.icache.total_refs 290585017 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 781 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 372067.883483 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 627.830229 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306558 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306558 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 290585017 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 290585017 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 290585017 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 290585017 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 290585017 # number of overall hits -system.cpu.icache.overall_hits::total 290585017 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1193 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1193 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1193 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1193 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1193 # number of overall misses -system.cpu.icache.overall_misses::total 1193 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 86035500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 86035500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 86035500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 86035500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 86035500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 86035500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 290586210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 290586210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 290586210 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 290586210 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 290586210 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 290586210 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 22 # number of replacements +system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 290622345 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 290622345 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 290622345 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 290622345 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 290622345 # number of overall hits +system.cpu.icache.overall_hits::total 290622345 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1216 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1216 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1216 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1216 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1216 # number of overall misses +system.cpu.icache.overall_misses::total 1216 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 85849749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 85849749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 85849749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 85849749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 85849749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 85849749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 290623561 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 290623561 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 290623561 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 290623561 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 290623561 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 290623561 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72116.932104 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72116.932104 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72116.932104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72116.932104 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70600.122533 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70600.122533 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70600.122533 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70600.122533 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 50.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 412 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59384001 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59384001 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 782 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 194424710000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48914000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 194375796000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 194424710000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184163 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184242 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436489 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436489 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233984 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233984 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65045.212766 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84955.110633 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 84944.568389 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89275.963569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89275.963569 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65045.212766 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86545.139311 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86537.943000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65045.212766 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86545.139311 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86537.943000 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 2245712 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2246464 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48787000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 120499016750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120547803750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73852563750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73852563750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48787000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 194351580500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 194400367500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48787000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 194351580500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 194400367500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184114 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184193 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436456 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436456 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233931 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233931 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64876.329787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84899.178233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 84888.575113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89367.363651 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89367.363651 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9597044 # number of replacements -system.cpu.dcache.tagsinuse 4088.193523 # Cycle average of tags in use -system.cpu.dcache.total_refs 655932792 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9601140 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.318220 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3513476000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.193523 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998094 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998094 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 488973029 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 488973029 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166959638 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166959638 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 9598226 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 488969047 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 488969047 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166960447 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166960447 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 655932667 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 655932667 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 655932667 # number of overall hits -system.cpu.dcache.overall_hits::total 655932667 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11505709 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11505709 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5626409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5626409 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 655929494 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 655929494 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 655929494 # number of overall hits +system.cpu.dcache.overall_hits::total 655929494 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11507818 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11507818 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5625600 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5625600 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17132118 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17132118 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17132118 # number of overall misses -system.cpu.dcache.overall_misses::total 17132118 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 379498751500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 379498751500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307395824029 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307395824029 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 651000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 651000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 686894575529 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 686894575529 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 686894575529 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 686894575529 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500478738 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500478738 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17133418 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17133418 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17133418 # number of overall misses +system.cpu.dcache.overall_misses::total 17133418 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 381897864985 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 381897864985 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 310946372440 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 310946372440 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 692844237425 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 692844237425 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 692844237425 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 692844237425 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500476865 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500476865 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673064785 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673064785 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673064785 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673064785 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032601 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032601 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025454 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025454 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025454 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025454 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32983.517270 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32983.517270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54634.461169 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54634.461169 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 217000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 217000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40093.967105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40093.967105 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29400681 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3494014 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1217576 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673062912 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673062912 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673062912 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673062912 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022994 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022994 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032596 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032596 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025456 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025456 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025456 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025456 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33185.949325 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33185.949325 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55273.459265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55273.459265 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40438.179786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40438.179786 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29551948 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3560628 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1217583 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.146896 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 53.645121 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.270993 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 54.667874 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781153 # number of writebacks -system.cpu.dcache.writebacks::total 3781153 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798054 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3798054 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732924 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3732924 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3782769 # number of writebacks +system.cpu.dcache.writebacks::total 3782769 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798912 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3798912 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732183 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3732183 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7530978 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7530978 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7530978 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7530978 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707655 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7707655 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893485 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893485 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601140 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210632290508 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 210632290508 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97135590826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 97135590826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 307767881334 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 307767881334 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 307767881334 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 307767881334 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7531095 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7531095 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7531095 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7531095 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708906 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708906 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602323 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602323 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602323 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602323 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210908812007 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 210908812007 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97317389015 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 97317389015 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308226201022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 308226201022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308226201022 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 308226201022 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27327.674955 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27327.674955 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51299.899828 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51299.899828 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014267 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014267 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27359.110619 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27359.110619 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51397.758135 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51397.758135 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 7f261f2f5..991abe176 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 4782410230 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 514.976015 # Cycle average of tags in use -system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 7 # number of replacements +system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926075 # number of replacements -system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1955843 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.945651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926075 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use -system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9111140 # number of replacements +system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 136c3d430..cc029b4bd 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 11765161052 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use -system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 10 # number of replacements +system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits @@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926197 # number of replacements -system.cpu.l2cache.tagsinuse 31136.249379 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.950203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926197 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits @@ -290,15 +290,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.587030 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600407 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9108581 # number of replacements +system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 4f9464f49..9ab9303b1 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041671 # Number of seconds simulated -sim_ticks 41671058000 # Number of ticks simulated -final_tick 41671058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041672 # Number of seconds simulated +sim_ticks 41671895000 # Number of ticks simulated +final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79080 # Simulator instruction rate (inst/s) -host_op_rate 79080 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35856814 # Simulator tick rate (ticks/s) -host_mem_usage 228800 # Number of bytes of host memory used -host_seconds 1162.15 # Real time elapsed on the host +host_inst_rate 84546 # Simulator instruction rate (inst/s) +host_op_rate 84546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38336000 # Simulator tick rate (ticks/s) +host_mem_usage 228812 # Number of bytes of host memory used +host_seconds 1087.02 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4291132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3292837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7583969 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4291132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4291132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4291132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3292837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7583969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4291046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3292771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7583816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4291046 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4291046 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41670985500 # Total gap between requests +system.physmem.totGap 41671821000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1155 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -213,14 +213,14 @@ system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation -system.physmem.totQLat 21938250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 110827000 # Sum of mem lat for all requests +system.physmem.totQLat 20561250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 109587500 # Sum of mem lat for all requests system.physmem.totBusLat 24690000 # Total cycles spent in databus access -system.physmem.totBankLat 64198750 # Total cycles spent in bank access -system.physmem.avgQLat 4442.74 # Average queueing delay per request -system.physmem.avgBankLat 13000.96 # Average bank access latency per request +system.physmem.totBankLat 64336250 # Total cycles spent in bank access +system.physmem.avgQLat 4163.88 # Average queueing delay per request +system.physmem.avgBankLat 13028.81 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22443.70 # Average memory access latency +system.physmem.avgMemAccLat 22192.69 # Average memory access latency system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s @@ -233,8 +233,8 @@ system.physmem.readRowHits 4578 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8438838.70 # Average gap between requests -system.membus.throughput 7583969 # Throughput (bytes/s) +system.physmem.avgGap 8439007.90 # Average gap between requests +system.membus.throughput 7583816 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -245,39 +245,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032 system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5804000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46092250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 46068500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 13412467 # Number of BP lookups -system.cpu.branchPred.condPredicted 9649930 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4269365 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 7424694 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3768519 # Number of BTB hits +system.cpu.branchPred.lookups 13412627 # Number of BP lookups +system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 7424479 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.756556 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 50.757730 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996249 # DTB read hits +system.cpu.dtb.read_hits 19996270 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996259 # DTB read accesses -system.cpu.dtb.write_hits 6501862 # DTB write hits +system.cpu.dtb.read_accesses 19996280 # DTB read accesses +system.cpu.dtb.write_hits 6501863 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501885 # DTB write accesses -system.cpu.dtb.data_hits 26498111 # DTB hits +system.cpu.dtb.write_accesses 6501886 # DTB write accesses +system.cpu.dtb.data_hits 26498133 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498144 # DTB accesses -system.cpu.itb.fetch_hits 9957259 # ITB hits +system.cpu.dtb.data_accesses 26498166 # DTB accesses +system.cpu.itb.fetch_hits 9956949 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9957308 # ITB accesses +system.cpu.itb.fetch_accesses 9956998 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -291,34 +291,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83342117 # number of cpu cycles simulated +system.cpu.numCycles 83343791 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 5905707 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7506760 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570716 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73570550 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146188 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206130 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136146022 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206131 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058018 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521724 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26722400 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3469281 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 799226 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4268507 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5972195 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 41.681781 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57404114 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 8058019 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26722393 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57404028 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82971475 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970405 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10802 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7733735 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75608382 # Number of cycles cpu stages are processed. -system.cpu.activity 90.720496 # Percentage of cycles cpu is active +system.cpu.timesIdled 10389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7736037 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607754 # Number of cycles cpu stages are processed. +system.cpu.activity 90.717920 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -330,72 +330,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.906848 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.906866 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.906848 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102720 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.906866 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102698 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102720 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27661043 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55681074 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.810247 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34090230 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251887 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.096035 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33490685 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851432 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.815414 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65315589 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026528 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.629554 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29482268 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859849 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.625007 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7633 # number of replacements -system.cpu.icache.tagsinuse 1492.272065 # Cycle average of tags in use -system.cpu.icache.total_refs 9945862 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9518 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1044.952931 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.272065 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728648 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728648 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9945862 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9945862 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9945862 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9945862 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9945862 # number of overall hits -system.cpu.icache.overall_hits::total 9945862 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11397 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11397 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11397 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11397 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11397 # number of overall misses -system.cpu.icache.overall_misses::total 11397 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 317452000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 317452000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 317452000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 317452000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 317452000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 317452000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9957259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9957259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9957259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9957259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9957259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9957259 # number of overall (read+write) accesses +system.cpu.ipc_total 1.102698 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27663446 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680345 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.808030 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34092107 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.094605 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33492443 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.814111 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65317278 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026513 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.629101 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 7635 # number of replacements +system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits +system.cpu.icache.overall_hits::total 9945551 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11398 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11398 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11398 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11398 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11398 # number of overall misses +system.cpu.icache.overall_misses::total 11398 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 318279500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 318279500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 318279500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 318279500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 318279500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 318279500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956949 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956949 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956949 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956949 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27853.996666 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27853.996666 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27853.996666 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27853.996666 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27924.153360 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27924.153360 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27924.153360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27924.153360 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -404,83 +404,83 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9518 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9518 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9518 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27326.223997 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27253.098739 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27253.098739 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27253.098739 # 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Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.069165 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.843612 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.867359 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.006398 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6724 # number of ReadReq hits +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2189.714615 # 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number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 6726 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 6803 # number of overall hits +system.cpu.l2cache.overall_hits::total 6805 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -492,52 +492,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183057000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30189500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 213246500 # 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miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293549 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.420577 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293549 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.420577 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65517.895490 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71539.099526 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66307.991294 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66602.206736 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66602.206736 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66410.591333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66410.591333 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65279.885469 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70949.052133 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66023.787313 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66901.858304 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66901.858304 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66329.991900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66329.991900 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -557,73 +557,73 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 148372000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24939500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 173311500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93717750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93717750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 148372000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118657250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 267029250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 148372000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118657250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 267029250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 147140500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24615500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171756000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 147140500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118660500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 265801000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 147140500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118660500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 265801000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321825 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.420577 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.420577 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53103.793844 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59098.341232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53890.391791 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54423.780488 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54423.780488 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52663.027917 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58330.568720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53406.716418 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.821138 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.821138 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.455577 # Cycle average of tags in use -system.cpu.dcache.total_refs 26488507 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11915.657670 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.455577 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492885 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492885 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488507 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488507 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488507 # number of overall hits -system.cpu.dcache.overall_hits::total 26488507 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492886 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488508 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488508 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488508 # number of overall hits +system.cpu.dcache.overall_hits::total 26488508 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8218 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8218 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8794 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8794 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8794 # number of overall misses -system.cpu.dcache.overall_misses::total 8794 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38984000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38984000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 463524000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 463524000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 502508000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 502508000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 502508000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 502508000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 8217 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8217 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8793 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8793 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8793 # number of overall misses +system.cpu.dcache.overall_misses::total 8793 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 38176750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 38176750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 468176250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 468176250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 506353000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 506353000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 506353000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 506353000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -640,19 +640,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000332 system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67680.555556 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67680.555556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56403.504502 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56403.504502 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57142.142370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57142.142370 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21765 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66279.079861 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66279.079861 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56976.542534 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56976.542534 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57585.920619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57585.920619 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22475 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 825 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 847 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.381818 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.534829 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -660,12 +660,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6571 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6571 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6571 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6571 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6570 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6570 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6570 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6570 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -674,14 +674,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116706500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116706500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147919500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 147919500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147919500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 147919500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117222500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 117222500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 148186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 148186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 148186500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 148186500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -690,14 +690,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65711.578947 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65711.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66765.732265 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66765.732265 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65187.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65187.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67060.926773 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67060.926773 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 183d79059..b5b638e61 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023497 # Number of seconds simulated -sim_ticks 23497413000 # Number of ticks simulated -final_tick 23497413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023492 # Number of seconds simulated +sim_ticks 23492267500 # Number of ticks simulated +final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127551 # Simulator instruction rate (inst/s) -host_op_rate 127551 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35603882 # Simulator tick rate (ticks/s) -host_mem_usage 231880 # Number of bytes of host memory used -host_seconds 659.97 # Real time elapsed on the host +host_inst_rate 122951 # Simulator instruction rate (inst/s) +host_op_rate 122951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34312389 # Simulator tick rate (ticks/s) +host_mem_usage 231868 # Number of bytes of host memory used +host_seconds 684.66 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 195392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory -system.physmem.bytes_read::total 334016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195392 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3053 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5219 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8315469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5899543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14215012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8315469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8315469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8315469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5899543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14215012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5219 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 334464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8339084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5898111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14237195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8339084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8339084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5226 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5219 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 334016 # Total number of bytes read from memory +system.physmem.cpureqs 5226 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 334464 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 334016 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 289 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 252 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 398 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23497287000 # Total gap between requests +system.physmem.totGap 23492140500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5219 # Categorize read packet sizes +system.physmem.readPktSize::6 5226 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,139 +149,135 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 779.330144 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 283.808293 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1370.086091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 124 29.67% 29.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 51 12.20% 41.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 42 10.05% 51.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 20 4.78% 56.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15 3.59% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 19 4.55% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7 1.67% 66.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 9 2.15% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 7 1.67% 70.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3 0.72% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 8 1.91% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 7 1.67% 74.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 1.44% 76.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 5 1.20% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.96% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1 0.24% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 1.44% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 5 1.20% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.72% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.72% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.72% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.72% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.48% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.48% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.24% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 2 0.48% 91.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.24% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.24% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.24% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.24% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.24% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.24% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.48% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.24% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.24% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.24% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.24% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 780.923077 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 283.989164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1375.157964 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 120 28.85% 28.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 59 14.18% 43.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 37 8.89% 51.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 19 4.57% 56.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16 3.85% 60.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 20 4.81% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 8 1.92% 67.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 8 1.92% 68.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 1.20% 70.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 5 1.20% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 6 1.44% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 8 1.92% 74.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 1.44% 76.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 4 0.96% 77.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 4 0.96% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 2 0.48% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 1.20% 79.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.96% 83.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.72% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.72% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.96% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 4 0.96% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.48% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.24% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.48% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.24% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.48% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.24% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.24% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 5 1.20% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.24% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.24% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.24% 98.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 2 0.48% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 4 0.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 418 # Bytes accessed per row activation -system.physmem.totQLat 22102000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 116465750 # Sum of mem lat for all requests -system.physmem.totBusLat 26095000 # Total cycles spent in databus access -system.physmem.totBankLat 68268750 # Total cycles spent in bank access -system.physmem.avgQLat 4234.91 # Average queueing delay per request -system.physmem.avgBankLat 13080.81 # Average bank access latency per request +system.physmem.bytesPerActivate::total 416 # Bytes accessed per row activation +system.physmem.totQLat 21308250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 115583250 # Sum of mem lat for all requests +system.physmem.totBusLat 26130000 # Total cycles spent in databus access +system.physmem.totBankLat 68145000 # Total cycles spent in bank access +system.physmem.avgQLat 4077.35 # Average queueing delay per request +system.physmem.avgBankLat 13039.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22315.72 # Average memory access latency -system.physmem.avgRdBW 14.22 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22116.96 # Average memory access latency +system.physmem.avgRdBW 14.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.22 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4801 # Number of row buffer hits during reads +system.physmem.readRowHits 4810 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 92.04 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4502258.48 # Average gap between requests -system.membus.throughput 14215012 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3511 # Transaction distribution -system.membus.trans_dist::ReadResp 3511 # Transaction distribution -system.membus.trans_dist::ReadExReq 1708 # Transaction distribution -system.membus.trans_dist::ReadExResp 1708 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 10438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 10438 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334016 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 334016 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334016 # Total data (bytes) +system.physmem.avgGap 4495243.11 # Average gap between requests +system.membus.throughput 14237195 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3520 # Transaction distribution +system.membus.trans_dist::ReadResp 3520 # Transaction distribution +system.membus.trans_dist::ReadExReq 1706 # Transaction distribution +system.membus.trans_dist::ReadExResp 1706 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 10452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 10452 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334464 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6341000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48807250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49069500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.branchPred.lookups 14862551 # Number of BP lookups -system.cpu.branchPred.condPredicted 10783549 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 926034 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8413875 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6968843 # Number of BTB hits +system.cpu.branchPred.lookups 14868892 # Number of BP lookups +system.cpu.branchPred.condPredicted 10787177 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 926932 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8430316 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6969924 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.825607 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1469354 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3121 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.676901 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1469870 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23132924 # DTB read hits -system.cpu.dtb.read_misses 192093 # DTB read misses +system.cpu.dtb.read_hits 23134581 # DTB read hits +system.cpu.dtb.read_misses 192685 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23325017 # DTB read accesses -system.cpu.dtb.write_hits 7072345 # DTB write hits -system.cpu.dtb.write_misses 1094 # DTB write misses +system.cpu.dtb.read_accesses 23327266 # DTB read accesses +system.cpu.dtb.write_hits 7072669 # DTB write hits +system.cpu.dtb.write_misses 1128 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 7073439 # DTB write accesses -system.cpu.dtb.data_hits 30205269 # DTB hits -system.cpu.dtb.data_misses 193187 # DTB misses +system.cpu.dtb.write_accesses 7073797 # DTB write accesses +system.cpu.dtb.data_hits 30207250 # DTB hits +system.cpu.dtb.data_misses 193813 # DTB misses system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 30398456 # DTB accesses -system.cpu.itb.fetch_hits 14755058 # ITB hits +system.cpu.dtb.data_accesses 30401063 # DTB accesses +system.cpu.itb.fetch_hits 14756036 # ITB hits system.cpu.itb.fetch_misses 101 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14755159 # ITB accesses +system.cpu.itb.fetch_accesses 14756137 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -295,238 +291,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46994827 # number of cpu cycles simulated +system.cpu.numCycles 46984536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15489149 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127098752 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14862551 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8438197 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22157137 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4490975 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5583322 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2356 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14755058 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 326188 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46762472 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.717965 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.375306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15488073 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127117981 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14868892 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8439794 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22159630 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4494895 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5563054 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2312 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14756036 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 325999 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46746670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.719295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.375691 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24605335 52.62% 52.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2364392 5.06% 57.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1192796 2.55% 60.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1746753 3.74% 63.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2761574 5.91% 69.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1153115 2.47% 72.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1218931 2.61% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 773556 1.65% 76.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10946020 23.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24587040 52.60% 52.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2365337 5.06% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191741 2.55% 60.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1747442 3.74% 63.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2760154 5.90% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1154764 2.47% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1218466 2.61% 74.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 772204 1.65% 76.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10949522 23.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46762472 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316259 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.704526 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17321703 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4276623 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20543509 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1101986 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3518651 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2516350 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12158 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 124100512 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31524 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3518651 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18468008 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 966877 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7668 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20476490 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3324778 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121264521 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 82 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 403236 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2443262 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89058236 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157582364 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 147884300 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9698064 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46746670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.705528 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17316199 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4260248 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20549941 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1098483 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3521799 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2517933 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12169 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 124122749 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32253 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3521799 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18461305 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 962240 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7648 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20480612 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3313066 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121283530 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 398899 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2436739 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89066471 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157595093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 147895466 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9699627 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20630875 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 727 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 718 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8817740 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25385211 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8251770 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2611914 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 924495 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105530247 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1715 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96635335 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178536 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20879466 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15657073 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1326 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46762472 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.066515 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875135 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20639110 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 733 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 729 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8785388 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25392018 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8252125 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2596537 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 925406 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105547434 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2098 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96644788 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177437 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20878127 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15672265 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1709 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46746670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.067415 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876261 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12166038 26.02% 26.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9374565 20.05% 46.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8425963 18.02% 64.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6292522 13.46% 77.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4920709 10.52% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2854864 6.11% 94.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1726414 3.69% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 795538 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205859 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12170136 26.03% 26.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9358863 20.02% 46.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8416132 18.00% 64.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6289434 13.45% 77.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4916374 10.52% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2864607 6.13% 94.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1727461 3.70% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 797242 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 206421 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46762472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46746670 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 190796 12.16% 12.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 179 0.01% 12.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7128 0.45% 12.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5650 0.36% 12.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843178 53.72% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 444699 28.33% 95.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77939 4.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 188535 12.02% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 207 0.01% 12.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7191 0.46% 12.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5653 0.36% 12.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842893 53.74% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 446132 28.45% 95.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77750 4.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58779410 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479944 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58781922 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479844 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2800605 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115340 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387840 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311019 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760059 0.79% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23845244 24.68% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7155548 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2799901 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115380 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387749 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311051 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760106 0.79% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23852037 24.68% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7156472 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96635335 # Type of FU issued -system.cpu.iq.rate 2.056297 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1569569 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016242 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226659120 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117679968 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87126809 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15122127 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8766253 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7066480 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90213613 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7991284 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1520773 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96644788 # Type of FU issued +system.cpu.iq.rate 2.056949 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568361 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016228 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226659796 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117693658 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87130802 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15122248 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8768674 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7065649 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90221948 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7991194 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1517986 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5389013 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18483 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34901 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1750667 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5395820 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18680 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34810 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1751022 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10533 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1986 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10535 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1932 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3518651 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 134178 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18459 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115772618 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 373350 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25385211 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8251770 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1715 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3175 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34901 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 538953 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495548 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034501 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95401130 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23325510 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1234205 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3521799 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133427 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18321 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115791419 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 375079 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25392018 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8252125 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2098 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2892 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34810 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 537595 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 497018 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034613 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95405393 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23327731 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1239395 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10240656 # number of nop insts executed -system.cpu.iew.exec_refs 30399148 # number of memory reference insts executed -system.cpu.iew.exec_branches 12029434 # Number of branches executed -system.cpu.iew.exec_stores 7073638 # Number of stores executed -system.cpu.iew.exec_rate 2.030035 # Inst execution rate -system.cpu.iew.wb_sent 94712572 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94193289 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64506867 # num instructions producing a value -system.cpu.iew.wb_consumers 89893282 # num instructions consuming a value +system.cpu.iew.exec_nop 10241887 # number of nop insts executed +system.cpu.iew.exec_refs 30401730 # number of memory reference insts executed +system.cpu.iew.exec_branches 12031007 # Number of branches executed +system.cpu.iew.exec_stores 7073999 # Number of stores executed +system.cpu.iew.exec_rate 2.030570 # Inst execution rate +system.cpu.iew.wb_sent 94717591 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94196451 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64508240 # num instructions producing a value +system.cpu.iew.wb_consumers 89892394 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.004333 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717594 # average fanout of values written-back +system.cpu.iew.wb_rate 2.004839 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717616 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23870674 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23889448 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914298 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43243821 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.125230 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.743207 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 915179 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43224871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.126161 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.744271 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16770420 38.78% 38.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9933071 22.97% 61.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4488153 10.38% 72.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2264318 5.24% 77.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1614513 3.73% 81.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1126501 2.60% 83.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722210 1.67% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 820173 1.90% 87.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5504462 12.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16760873 38.78% 38.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9929358 22.97% 61.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4485318 10.38% 72.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2262602 5.23% 77.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1610546 3.73% 81.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1125217 2.60% 83.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721883 1.67% 85.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 816904 1.89% 87.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5512170 12.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43243821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43224871 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,212 +532,212 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5504462 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5512170 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153512048 # The number of ROB reads -system.cpu.rob.rob_writes 235089898 # The number of ROB writes -system.cpu.timesIdled 5458 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 232355 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153504164 # The number of ROB reads +system.cpu.rob.rob_writes 235130535 # The number of ROB writes +system.cpu.timesIdled 5262 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 237866 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.558268 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558268 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791255 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791255 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129137938 # number of integer regfile reads -system.cpu.int_regfile_writes 70566847 # number of integer regfile writes -system.cpu.fp_regfile_reads 6190616 # number of floating regfile reads -system.cpu.fp_regfile_writes 6048237 # number of floating regfile writes -system.cpu.misc_regfile_reads 714522 # number of misc regfile reads +system.cpu.cpi 0.558146 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.558146 # CPI: Total CPI of All Threads +system.cpu.ipc 1.791647 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.791647 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129142322 # number of integer regfile reads +system.cpu.int_regfile_writes 70569523 # number of integer regfile writes +system.cpu.fp_regfile_reads 6189856 # number of floating regfile reads +system.cpu.fp_regfile_writes 6047601 # number of floating regfile writes +system.cpu.misc_regfile_reads 714537 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 38347030 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 12236 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12236 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 28049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 750272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 901056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 901056 # Total data (bytes) +system.cpu.toL2Bus.throughput 37717943 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12006 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12006 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 22984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 27582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 735488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 886080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 886080 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7148500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 7030500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17584500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17871250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3370500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3590750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 9791 # number of replacements -system.cpu.icache.tagsinuse 1591.709559 # Cycle average of tags in use -system.cpu.icache.total_refs 14740526 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11723 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1257.402201 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.709559 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777202 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777202 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14740526 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14740526 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14740526 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14740526 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14740526 # number of overall hits -system.cpu.icache.overall_hits::total 14740526 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14755057 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14755057 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14755057 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14755057 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14755057 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14755057 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000985 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000985 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000985 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000985 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000985 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000985 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27458.846604 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27458.846604 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27458.846604 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27458.846604 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27458.846604 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27458.846604 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked +system.cpu.icache.tags.replacements 9559 # number of replacements +system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11492 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1282.781848 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1595.799290 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.779199 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.779199 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14741729 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14741729 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14741729 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14741729 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14741729 # number of overall hits +system.cpu.icache.overall_hits::total 14741729 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14307 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14756036 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14756036 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14756036 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14756036 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14756036 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000970 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000970 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27922.782554 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27922.782554 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27922.782554 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27922.782554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27922.782554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27922.782554 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.714286 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2808 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2808 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2808 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2808 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2808 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2808 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 297568500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 297568500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 297568500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 297568500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 297568500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 297568500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000795 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000795 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000795 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000795 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000795 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000795 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25383.306321 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25383.306321 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25383.306321 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25383.306321 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25383.306321 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000779 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25714.605813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25714.605813 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2401.280211 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8740 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3578 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.442705 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.673510 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2001.216545 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 382.390156 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061072 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011670 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073281 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8670 # 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355939 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21603146 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21603146 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492891 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492891 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28096037 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59585500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59585500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 475543278 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 475543278 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 535128778 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 535128778 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 535128778 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 535128778 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21599678 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21599678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9200 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9200 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9200 # number of overall misses +system.cpu.dcache.overall_misses::total 9200 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 60150500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 60150500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 476870547 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 476870547 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 537021047 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 537021047 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 537021047 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 537021047 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21604134 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21604134 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 219 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 219 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28100781 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28100781 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28100781 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28100781 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001265 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001265 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004566 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004566 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 237 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 237 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28105237 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28105237 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28105237 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28105237 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001263 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004219 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004219 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61365.087539 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61365.087539 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57837.907808 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57837.907808 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58210.462091 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58210.462091 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21885 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60881.072874 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60881.072874 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58069.964321 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58069.964321 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58371.852935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58371.852935 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21919 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 353 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.997167 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.235119 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109 # number of writebacks -system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6488 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6488 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6947 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6947 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6947 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6947 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 475 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 475 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6481 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6481 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6956 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6956 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6956 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6956 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116538997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116538997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151198997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151198997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151198997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151198997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35017250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35017250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116268497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116268497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151285747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151285747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151285747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151285747 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004566 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004566 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004219 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67695.312500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67695.312500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67208.187428 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67208.187428 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68259.746589 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68259.746589 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67168.398036 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67168.398036 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index b57d95ab0..847011ac3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 237458632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.tagsinuse 1418.052773 # Cycle average of tags in use -system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 6681 # number of replacements +system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.063296 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits @@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use -system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e580bbf9c..191849c1b 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074184 # Number of seconds simulated -sim_ticks 74184344000 # Number of ticks simulated -final_tick 74184344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074201 # Number of seconds simulated +sim_ticks 74201024500 # Number of ticks simulated +final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120810 # Simulator instruction rate (inst/s) -host_op_rate 132276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52014122 # Simulator tick rate (ticks/s) -host_mem_usage 249648 # Number of bytes of host memory used -host_seconds 1426.23 # Real time elapsed on the host +host_inst_rate 81530 # Simulator instruction rate (inst/s) +host_op_rate 89268 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35110326 # Simulator tick rate (ticks/s) +host_mem_usage 249620 # Number of bytes of host memory used +host_seconds 2113.37 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory -system.physmem.bytes_read::total 242944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131136 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3796 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1767705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1507164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3274869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1767705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1767705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1767705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1507164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3274869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3796 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111872 # Number of bytes read from this memory +system.physmem.bytes_read::total 243200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1748 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3800 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1769895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1507688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3277583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1769895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1769895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3801 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3798 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 242944 # Total number of bytes read from memory +system.physmem.cpureqs 3803 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 243200 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 242944 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 309 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 308 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 298 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 262 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 217 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 216 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 213 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 189 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 206 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 199 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 289 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 200 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74184191000 # Total gap between requests +system.physmem.totGap 74201006000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3796 # Categorize read packet sizes +system.physmem.readPktSize::6 3801 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 2837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,114 +149,114 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 376 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 621.446809 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.720612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1211.628472 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 135 35.90% 35.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 51 13.56% 49.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 26 6.91% 56.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29 7.71% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 14 3.72% 67.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 14 3.72% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6 1.60% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 5 1.33% 74.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 7 1.86% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 7 1.86% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 5 1.33% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 1.60% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1 0.27% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 5 1.33% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.80% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 4 1.06% 84.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 2 0.53% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.80% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.80% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1 0.27% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.27% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 5 1.33% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.53% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.27% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.80% 90.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.80% 90.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.27% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.27% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.27% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.27% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.53% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.27% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.27% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.27% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.27% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.27% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.27% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.27% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.27% 94.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.27% 94.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.27% 95.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.27% 95.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.27% 95.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 3 0.80% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.27% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.27% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.27% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.27% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.27% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.27% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.27% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.27% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.27% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.27% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 376 # Bytes accessed per row activation -system.physmem.totQLat 13471250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86310000 # Sum of mem lat for all requests -system.physmem.totBusLat 18980000 # Total cycles spent in databus access -system.physmem.totBankLat 53858750 # Total cycles spent in bank access -system.physmem.avgQLat 3548.80 # Average queueing delay per request -system.physmem.avgBankLat 14188.29 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 389 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 616.966581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 221.267348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1216.553816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 139 35.73% 35.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 59 15.17% 50.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 33 8.48% 59.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 24 6.17% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15 3.86% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 13 3.34% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 4 1.03% 73.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 7 1.80% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 1.29% 76.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 8 2.06% 78.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 1.03% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 1.03% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.77% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 3 0.77% 82.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 1.29% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 4 1.03% 84.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 4 1.03% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.26% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 1 0.26% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.77% 87.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.77% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.77% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.51% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.26% 89.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.77% 90.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.77% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.26% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.26% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.26% 91.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.26% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.51% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.26% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.26% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.26% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.26% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.26% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.26% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.26% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.26% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.26% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.26% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.26% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 4 1.03% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.26% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.26% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.26% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.26% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.26% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.26% 97.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 1 0.26% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.26% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.26% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.26% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.26% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.26% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 389 # Bytes accessed per row activation +system.physmem.totQLat 12962000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86183250 # Sum of mem lat for all requests +system.physmem.totBusLat 19005000 # Total cycles spent in databus access +system.physmem.totBankLat 54216250 # Total cycles spent in bank access +system.physmem.avgQLat 3410.16 # Average queueing delay per request +system.physmem.avgBankLat 14263.68 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22737.09 # Average memory access latency -system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22673.84 # Average memory access latency +system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3420 # Number of row buffer hits during reads +system.physmem.readRowHits 3412 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19542726.82 # Average gap between requests -system.membus.throughput 3274869 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2721 # Transaction distribution -system.membus.trans_dist::ReadResp 2721 # Transaction distribution +system.physmem.avgGap 19521443.30 # Average gap between requests +system.membus.throughput 3277583 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2726 # Transaction distribution +system.membus.trans_dist::ReadResp 2725 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 1075 # Transaction distribution system.membus.trans_dist::ReadExResp 1075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 7596 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 7596 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 242944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 242944 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 242944 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 7605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 7605 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 243200 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 243200 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 243200 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4823500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35740248 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35707998 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 94757540 # Number of BP lookups -system.cpu.branchPred.condPredicted 74764818 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6278340 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44654246 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43033777 # Number of BTB hits +system.cpu.branchPred.lookups 94803777 # Number of BP lookups +system.cpu.branchPred.condPredicted 74793629 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6279390 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44652033 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43049215 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.371075 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4354951 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88346 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.410425 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4355984 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88442 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -300,240 +300,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148368689 # number of cpu cycles simulated +system.cpu.numCycles 148402050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39647823 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380146219 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94757540 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47388728 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80358140 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27268312 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7203967 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 39645282 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380210735 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94803777 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47405199 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80366135 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283939 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7211893 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5523 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 5835 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36843987 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1833209 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148189615 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802214 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 74 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36839707 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1829204 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148218142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153165 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68000764 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5268021 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540392 7.11% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10285161 6.94% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8646262 5.83% 69.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545573 4.42% 73.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6244018 4.21% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7997629 5.40% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24661795 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68020669 45.89% 45.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5263809 3.55% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10529342 7.10% 56.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10284383 6.94% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8663442 5.85% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6544357 4.42% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6237651 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8018779 5.41% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655710 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148189615 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638663 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.562173 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45498061 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5874830 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74793705 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1202536 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20820483 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14321847 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164416 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392715815 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 749819 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20820483 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50886064 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 722985 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 600307 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70546117 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4613659 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371260855 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 344235 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3657023 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 27 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631666093 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581493948 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1564155420 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17338528 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148218142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638831 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.562032 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45496346 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5881053 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74801402 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1203851 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20835490 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14335605 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164633 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392823460 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 736203 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20835490 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50883815 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 724795 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 600466 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70555670 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4617906 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371356593 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 28 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 342994 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3662384 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1564582781 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17300681 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333621954 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25182 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25179 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13028807 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 42981884 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16417977 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5680787 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3667947 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329134626 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25185 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13032916 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43019038 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16425001 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5693552 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3686945 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329243417 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249422621 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 787073 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139456652 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 361881130 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 249464214 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 795417 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139561180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362246737 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148189615 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683132 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761818 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 148218142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.683088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761802 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56042296 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22626121 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24808060 16.74% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20320875 13.71% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12548887 8.47% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6516147 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4031410 2.72% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1113540 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182279 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56048230 37.81% 37.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22642926 15.28% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24814212 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20312337 13.70% 83.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12552656 8.47% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6518158 4.40% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4033272 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1116001 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 180350 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148189615 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148218142 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 962595 38.42% 38.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5594 0.22% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 107 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1164588 46.49% 85.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372359 14.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 965237 38.47% 38.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5595 0.22% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1168121 46.56% 85.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 370007 14.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194884583 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979638 0.39% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33073 0.01% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164452 0.07% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254844 0.10% 78.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76427 0.03% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465912 0.19% 78.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206449 0.08% 79.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71875 0.03% 79.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 79.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38337954 15.37% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13947091 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194903493 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979289 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33083 0.01% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164442 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254821 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76413 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465720 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38359883 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13948512 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249422621 # Type of FU issued -system.cpu.iq.rate 1.681100 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2505291 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010044 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646588556 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466464832 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237860517 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3738665 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2192143 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1842020 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250052019 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1875893 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2007355 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249464214 # Type of FU issued +system.cpu.iq.rate 1.681002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2509108 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010058 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646714008 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466681926 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237887502 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3737087 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2188015 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1841410 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250098110 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1875212 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2005238 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13132400 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11727 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18993 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3773343 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13169554 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11470 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18663 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3780367 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 13 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 113 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20820483 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18849 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 902 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329198829 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 786805 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 42981884 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16417977 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 20835490 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18710 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 879 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329307607 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785363 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43019038 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16425001 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 191 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18993 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3888167 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3760327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7648494 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242926605 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36835264 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496016 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 275 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18663 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3889158 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3759638 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7648796 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242968769 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36856935 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6495445 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17000 # number of nop insts executed -system.cpu.iew.exec_refs 50481074 # number of memory reference insts executed -system.cpu.iew.exec_branches 53424163 # Number of branches executed -system.cpu.iew.exec_stores 13645810 # Number of stores executed -system.cpu.iew.exec_rate 1.637317 # Inst execution rate -system.cpu.iew.wb_sent 240758455 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239702537 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148455856 # num instructions producing a value -system.cpu.iew.wb_consumers 267256641 # num instructions consuming a value +system.cpu.iew.exec_nop 16987 # number of nop insts executed +system.cpu.iew.exec_refs 50502724 # number of memory reference insts executed +system.cpu.iew.exec_branches 53433142 # Number of branches executed +system.cpu.iew.exec_stores 13645789 # Number of stores executed +system.cpu.iew.exec_rate 1.637233 # Inst execution rate +system.cpu.iew.wb_sent 240789077 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239728912 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148477198 # num instructions producing a value +system.cpu.iew.wb_consumers 267296630 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615587 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555481 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615402 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555477 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140527929 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140636703 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6124743 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127369132 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481292 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186316 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6125970 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127382652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.185870 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57689921 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31670367 24.87% 70.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13785643 10.82% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7636266 6.00% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4374586 3.43% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321093 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1699680 1.33% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1314057 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7877519 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57681624 45.28% 45.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696418 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13781439 10.82% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7634613 5.99% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4380226 3.44% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1319827 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1706186 1.34% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1307951 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7874368 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127369132 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127382652 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -544,220 +544,220 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7877519 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7874368 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448685232 # The number of ROB reads -system.cpu.rob.rob_writes 679327064 # The number of ROB writes -system.cpu.timesIdled 2810 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 179074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448810677 # The number of ROB reads +system.cpu.rob.rob_writes 679560182 # The number of ROB writes +system.cpu.timesIdled 2800 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 183908 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.861092 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861092 # CPI: Total CPI of All Threads -system.cpu.ipc 1.161317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.161317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079239284 # number of integer regfile reads -system.cpu.int_regfile_writes 384835773 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913699 # number of floating regfile reads -system.cpu.fp_regfile_writes 2498274 # number of floating regfile writes -system.cpu.misc_regfile_reads 54487026 # number of misc regfile reads +system.cpu.cpi 0.861285 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861285 # CPI: Total CPI of All Threads +system.cpu.ipc 1.161056 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.161056 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079439367 # number of integer regfile reads +system.cpu.int_regfile_writes 384873719 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913212 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497494 # number of floating regfile writes +system.cpu.misc_regfile_reads 54494427 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5142648 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution +system.cpu.toL2Bus.throughput 5172543 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3727 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 11907 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 261696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 381376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 381376 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 11979 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 263808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 383680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2998500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6138496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6609745 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2786987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 2359 # number of replacements -system.cpu.icache.tagsinuse 1350.344535 # Cycle average of tags in use -system.cpu.icache.total_refs 36838706 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4089 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9009.221326 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1350.344535 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.659348 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.659348 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36838706 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36838706 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36838706 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36838706 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36838706 # number of overall hits -system.cpu.icache.overall_hits::total 36838706 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5281 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5281 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5281 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5281 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5281 # number of overall misses -system.cpu.icache.overall_misses::total 5281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 212968998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 212968998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 212968998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 212968998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 212968998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 212968998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36843987 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36843987 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36843987 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36843987 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36843987 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36843987 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000143 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000143 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000143 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000143 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000143 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000143 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40327.399735 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40327.399735 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40327.399735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40327.399735 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked +system.cpu.icache.tags.replacements 2391 # number of replacements +system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36834377 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36834377 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36834377 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36834377 # number of overall hits +system.cpu.icache.overall_hits::total 36834377 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5330 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5330 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5330 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5330 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5330 # number of overall misses +system.cpu.icache.overall_misses::total 5330 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 215954243 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 215954243 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 215954243 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 215954243 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 215954243 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 215954243 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36839707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36839707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36839707 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36839707 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36839707 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36839707 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40516.743527 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40516.743527 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40516.743527 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40516.743527 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1739 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58.350000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 82.809524 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1190 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1190 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1190 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1190 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1190 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1190 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161081503 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 161081503 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161081503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 161081503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161081503 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 161081503 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39374.603520 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39374.603520 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39374.603520 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39374.603520 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39374.603520 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39374.603520 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1205 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1205 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1205 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1205 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1205 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1205 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4125 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4125 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4125 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4125 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4125 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4125 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 162387254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 162387254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 162387254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 162387254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 162387254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 162387254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39366.607030 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39366.607030 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1965.775294 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2123 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2730 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.777656 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 4.992159 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1426.906678 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 533.876457 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.043546 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016293 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.059991 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2037 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 85 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2122 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 17 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 17 # number of Writeback hits +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1961.044100 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2153 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2735 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.787203 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 4.994051 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1423.034105 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 533.015945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1407.131551 # Cycle average of tags in use -system.cpu.dcache.total_refs 46775584 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1853 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25243.164598 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1407.131551 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.343538 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.343538 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34374175 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34374175 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356535 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356535 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22465 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22465 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 57 # number of replacements +system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22472 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46730710 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46730710 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46730710 # number of overall hits -system.cpu.dcache.overall_hits::total 46730710 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1909 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1909 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7752 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7752 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46753571 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46753571 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46753571 # number of overall hits +system.cpu.dcache.overall_hits::total 46753571 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1913 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1913 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9661 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9661 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9661 # number of overall misses -system.cpu.dcache.overall_misses::total 9661 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 115578500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 115578500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 443691996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 443691996 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 141000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 141000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 559270496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 559270496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 559270496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 559270496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34376084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34376084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9643 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9643 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9643 # number of overall misses +system.cpu.dcache.overall_misses::total 9643 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114314976 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114314976 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 447415748 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 447415748 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 561730724 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 561730724 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 561730724 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 561730724 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34398927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34398927 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22467 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46740371 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46740371 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46740371 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46740371 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46763214 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46763214 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46763214 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46763214 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60544.002095 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60544.002095 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57235.809598 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57235.809598 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57889.503778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57889.503778 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 581 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 112 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59756.913748 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59756.913748 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57880.433118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57880.433118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58252.693560 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58252.693560 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 154 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.416667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.272727 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 17 # number of writebacks -system.cpu.dcache.writebacks::total 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6669 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6669 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1140 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6646 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6646 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7806 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7806 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7806 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7806 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 772 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 772 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1083 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1083 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1855 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1855 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1855 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1855 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49331013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 49331013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69111498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 69111498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118442511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 118442511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118442511 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 118442511 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7786 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7786 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7786 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7786 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 773 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1084 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1084 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48960262 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48960262 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69313496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 69313496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118273758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 118273758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118273758 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 118273758 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses @@ -945,14 +945,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63900.275907 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63900.275907 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63814.864266 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63814.864266 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63337.984476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63337.984476 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63942.339483 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63942.339483 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 6b5d6bef1..371d1c275 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 464144608 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1506 # number of replacements -system.cpu.icache.tagsinuse 1147.986161 # Cycle average of tags in use -system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1506 # number of replacements +system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 40 # number of replacements -system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use -system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 40 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index a79e42f60..6ce379f53 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 541126164 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 10362 # number of replacements -system.cpu.icache.tagsinuse 1591.579171 # Cycle average of tags in use -system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 10362 # number of replacements +system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2678.340865 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits @@ -274,15 +274,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2 # number of replacements -system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use -system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2 # number of replacements +system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index a9e1bd99e..2e8d78059 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144456 # Number of seconds simulated -sim_ticks 144456233500 # Number of ticks simulated -final_tick 144456233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144471 # Number of seconds simulated +sim_ticks 144470654000 # Number of ticks simulated +final_tick 144470654000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74036 # Simulator instruction rate (inst/s) -host_op_rate 124090 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 80978511 # Simulator tick rate (ticks/s) -host_mem_usage 278896 # Number of bytes of host memory used -host_seconds 1783.88 # Real time elapsed on the host +host_inst_rate 76550 # Simulator instruction rate (inst/s) +host_op_rate 128304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83736451 # Simulator tick rate (ticks/s) +host_mem_usage 279024 # Number of bytes of host memory used +host_seconds 1725.30 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362962 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125312 # Number of bytes read from this memory -system.physmem.bytes_read::total 342592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5353 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1504123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 867474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2371597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1504123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1504123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1504123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 867474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2371597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5356 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124992 # Number of bytes read from this memory +system.physmem.bytes_read::total 341760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1953 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5340 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1500429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 865172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2365602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1500429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1500429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1500429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 865172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2365602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5340 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5495 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 342592 # Total number of bytes read from memory +system.physmem.cpureqs 5492 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 341760 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 342592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 341760 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 139 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 357 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 355 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 380 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 210 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 283 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 152 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 358 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 359 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 398 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 381 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 337 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 282 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 144456205000 # Total gap between requests +system.physmem.totGap 144470612000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5356 # Categorize read packet sizes +system.physmem.readPktSize::6 5340 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,79 +149,77 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 510 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 662.337255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 234.191565 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1287.834177 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 176 34.51% 34.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 77 15.10% 49.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39 7.65% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29 5.69% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 22 4.31% 67.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12 2.35% 69.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 18 3.53% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 5 0.98% 74.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 2.55% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 6 1.18% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3 0.59% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 1.18% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.59% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 6 1.18% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 7 1.37% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1 0.20% 83.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 6 1.18% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.39% 85.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.39% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.39% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 6 1.18% 87.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.20% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.59% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.20% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.39% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.20% 89.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.39% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 3 0.59% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.59% 91.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 4 0.78% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 3 0.59% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 2 0.39% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 4 0.78% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.20% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.39% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.20% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.20% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.20% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 662.047244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.931754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1294.319008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 181 35.63% 35.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 78 15.35% 50.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 41 8.07% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 18 3.54% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 27 5.31% 67.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 9 1.77% 69.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 15 2.95% 72.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 11 2.17% 74.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.77% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 6 1.18% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.79% 78.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 1.18% 79.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.98% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 4 0.79% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 1.18% 82.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 3 0.59% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.59% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.79% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1 0.20% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.79% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.79% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3 0.59% 87.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.20% 88.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.20% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.39% 89.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 6 1.18% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.20% 90.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.20% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 3 0.59% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.39% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 3 0.59% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.20% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.39% 93.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.79% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 3 0.59% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.20% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.20% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.39% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 1 0.20% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.20% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 5 0.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 510 # Bytes accessed per row activation -system.physmem.totQLat 13729500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 120235750 # Sum of mem lat for all requests -system.physmem.totBusLat 26770000 # Total cycles spent in databus access -system.physmem.totBankLat 79736250 # Total cycles spent in bank access -system.physmem.avgQLat 2563.39 # Average queueing delay per request -system.physmem.avgBankLat 14887.28 # Average bank access latency per request -system.physmem.avgBusLat 4998.13 # Average bus latency per request -system.physmem.avgMemAccLat 22448.80 # Average memory access latency +system.physmem.bytesPerActivate::total 508 # Bytes accessed per row activation +system.physmem.totQLat 12730250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 118864000 # Sum of mem lat for all requests +system.physmem.totBusLat 26700000 # Total cycles spent in databus access +system.physmem.totBankLat 79433750 # Total cycles spent in bank access +system.physmem.avgQLat 2383.94 # Average queueing delay per request +system.physmem.avgBankLat 14875.23 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 22259.18 # Average memory access latency system.physmem.avgRdBW 2.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.37 # Average consumed read bandwidth in MB/s @@ -230,272 +228,272 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4844 # Number of row buffer hits during reads +system.physmem.readRowHits 4832 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26970912.06 # Average gap between requests -system.membus.throughput 2371597 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3826 # Transaction distribution -system.membus.trans_dist::ReadResp 3823 # Transaction distribution -system.membus.trans_dist::UpgradeReq 139 # Transaction distribution -system.membus.trans_dist::UpgradeResp 139 # Transaction distribution +system.physmem.avgGap 27054421.72 # Average gap between requests +system.membus.throughput 2365159 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3810 # Transaction distribution +system.membus.trans_dist::ReadResp 3809 # Transaction distribution +system.membus.trans_dist::UpgradeReq 152 # Transaction distribution +system.membus.trans_dist::UpgradeResp 152 # Transaction distribution system.membus.trans_dist::ReadExReq 1530 # Transaction distribution system.membus.trans_dist::ReadExResp 1530 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 10987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10987 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 342592 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 10983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10983 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 341696 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 7029500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50887361 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50657098 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18668412 # Number of BP lookups -system.cpu.branchPred.condPredicted 18668412 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1491215 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11464480 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10808529 # Number of BTB hits +system.cpu.branchPred.lookups 18662810 # Number of BP lookups +system.cpu.branchPred.condPredicted 18662810 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1489054 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11419999 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10818987 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.278406 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1321942 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 23508 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.737197 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1313526 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22992 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289199941 # number of cpu cycles simulated +system.cpu.numCycles 289223613 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23489092 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206857811 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18668412 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12130471 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54260755 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15560780 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 178047703 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7863 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22383448 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 227467 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269615649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.269321 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.757232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23462367 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206597935 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18662810 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12132513 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54232022 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15527864 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 178098132 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8383 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22359928 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 225896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269583947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.268673 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.756592 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216795166 80.41% 80.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2848237 1.06% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2316890 0.86% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2640281 0.98% 83.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3221568 1.19% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3391687 1.26% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3836150 1.42% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2560999 0.95% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32004671 11.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216790408 80.42% 80.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2847266 1.06% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2313368 0.86% 82.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2651625 0.98% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3218833 1.19% 84.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3390708 1.26% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3829918 1.42% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2557961 0.95% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31983860 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269615649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064552 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.715276 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36944387 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167005183 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41608261 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10249032 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13808786 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336293429 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13808786 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45003701 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116679127 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28084 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42750473 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51345478 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329924152 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10957 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26042658 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22711387 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 324 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 382666276 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 918470799 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 910237815 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8232984 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269583947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064527 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.714319 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36913432 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167057645 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41544375 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10286977 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13781518 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336085554 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13781518 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44957189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116645963 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 32240 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42740267 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51426770 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329706442 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10945 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26120234 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22717452 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 239 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 382540638 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917473743 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 909278159 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8195584 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 123236826 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2077 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2071 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105014998 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84558511 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30136347 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58291555 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18982732 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322974285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4304 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260692143 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115978 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 101227039 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210564251 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3059 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269615649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.966903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.344359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 123111188 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2136 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2172 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105032755 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84354587 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30100906 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58264869 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19038031 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322777816 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4259 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260629412 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116539 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 101038886 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 209946848 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3014 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269583947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.966784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.343888 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143415763 53.19% 53.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55488403 20.58% 73.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34156757 12.67% 86.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19088088 7.08% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10888681 4.04% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4144802 1.54% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1820810 0.68% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476392 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135953 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143351146 53.17% 53.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55555603 20.61% 73.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34178684 12.68% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19029881 7.06% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10872516 4.03% 97.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4173623 1.55% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1820350 0.68% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 470633 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 131511 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269615649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269583947 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 130533 4.80% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2283697 84.00% 88.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 304445 11.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130095 4.79% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2285309 84.07% 88.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 303076 11.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210883 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162146963 62.20% 62.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788849 0.30% 62.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035772 2.70% 65.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1445624 0.55% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65501773 25.13% 91.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22562279 8.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210969 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162174415 62.22% 62.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 791156 0.30% 62.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035823 2.70% 65.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1446634 0.56% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65423127 25.10% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22547288 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260692143 # Type of FU issued -system.cpu.iq.rate 0.901425 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2718675 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010429 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788942081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420863494 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255312010 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4892507 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3626050 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2350305 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259737433 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2462502 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18945833 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260629412 # Type of FU issued +system.cpu.iq.rate 0.901135 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2718480 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010430 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788786495 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420497128 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255267923 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4891295 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3603930 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2350852 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259675050 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2461873 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18886019 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27908924 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26612 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 289609 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9620630 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27705000 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26101 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 285579 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9585192 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 51419 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 50399 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13808786 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85007909 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5442016 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322978589 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 134528 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84558511 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30136347 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2042 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2673918 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13520 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 289609 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 642268 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 899522 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1541790 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258904579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64718726 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1787564 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13781518 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85016114 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5459108 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322782075 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 133200 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84354587 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30100909 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2090 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2675714 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13368 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 285579 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 639541 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 899945 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1539486 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258853338 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64649488 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1776074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87077956 # number of memory reference insts executed -system.cpu.iew.exec_branches 14272272 # Number of branches executed -system.cpu.iew.exec_stores 22359230 # Number of stores executed -system.cpu.iew.exec_rate 0.895244 # Inst execution rate -system.cpu.iew.wb_sent 258260440 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257662315 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206077428 # num instructions producing a value -system.cpu.iew.wb_consumers 369317966 # num instructions consuming a value +system.cpu.iew.exec_refs 86992429 # number of memory reference insts executed +system.cpu.iew.exec_branches 14274182 # Number of branches executed +system.cpu.iew.exec_stores 22342941 # Number of stores executed +system.cpu.iew.exec_rate 0.894994 # Inst execution rate +system.cpu.iew.wb_sent 258213659 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257618775 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206032066 # num instructions producing a value +system.cpu.iew.wb_consumers 369264105 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.890949 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557995 # average fanout of values written-back +system.cpu.iew.wb_rate 0.890725 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557953 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101692643 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101495618 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1492367 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255806863 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.865352 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.655114 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1490324 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255802429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.865367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.654211 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156513813 61.18% 61.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57168789 22.35% 83.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14010033 5.48% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12060678 4.71% 93.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4174757 1.63% 95.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2964012 1.16% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 898257 0.35% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048749 0.41% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6967775 2.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156431243 61.15% 61.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57241672 22.38% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14031050 5.49% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12055371 4.71% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4173166 1.63% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2967121 1.16% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 906774 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1044092 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6951940 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255806863 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255802429 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -506,220 +504,222 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6967775 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6951940 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571894693 # The number of ROB reads -system.cpu.rob.rob_writes 659945778 # The number of ROB writes -system.cpu.timesIdled 5917549 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19584292 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571709069 # The number of ROB reads +system.cpu.rob.rob_writes 659523764 # The number of ROB writes +system.cpu.timesIdled 5926858 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19639666 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.189728 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.189728 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456678 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456678 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 554359034 # number of integer regfile reads -system.cpu.int_regfile_writes 293931276 # number of integer regfile writes -system.cpu.fp_regfile_reads 3216619 # number of floating regfile reads -system.cpu.fp_regfile_writes 2010069 # number of floating regfile writes -system.cpu.misc_regfile_reads 133443045 # number of misc regfile reads +system.cpu.cpi 2.189907 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.189907 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456640 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456640 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 554085462 # number of integer regfile reads +system.cpu.int_regfile_writes 293886504 # number of integer regfile writes +system.cpu.fp_regfile_reads 3218743 # number of floating regfile reads +system.cpu.fp_regfile_writes 2010653 # number of floating regfile writes +system.cpu.misc_regfile_reads 133373003 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3896100 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 139 # Transaction distribution +system.cpu.toL2Bus.throughput 3891282 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7233 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 153 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 153 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13426 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 17718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 425152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 553920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 553920 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8896 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4481500 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13393 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 17708 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 423616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 552320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 552320 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 9856 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4483500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10173000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10832250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3068000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3515652 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 4678 # number of replacements -system.cpu.icache.tagsinuse 1622.603356 # Cycle average of tags in use -system.cpu.icache.total_refs 22374543 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6643 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3368.138341 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1622.603356 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.792287 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.792287 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22374545 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22374545 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22374545 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22374545 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22374545 # number of overall hits -system.cpu.icache.overall_hits::total 22374545 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8903 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8903 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8903 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8903 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8903 # number of overall misses -system.cpu.icache.overall_misses::total 8903 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 349961000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 349961000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 349961000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 349961000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 349961000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 349961000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22383448 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22383448 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22383448 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22383448 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22383448 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22383448 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 4654 # number of replacements +system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 22351029 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22351029 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22351029 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22351029 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22351029 # number of overall hits +system.cpu.icache.overall_hits::total 22351029 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8899 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8899 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8899 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8899 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8899 # number of overall misses +system.cpu.icache.overall_misses::total 8899 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 351537500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 351537500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 351537500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 351537500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 351537500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 351537500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22359928 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22359928 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22359928 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22359928 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22359928 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22359928 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39308.210715 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39308.210715 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39308.210715 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39308.210715 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1033 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39503.034049 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39503.034049 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39503.034049 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39503.034049 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39503.034049 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39503.034049 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 913 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.388889 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53.705882 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2120 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38737.726670 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38737.726670 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38650.612637 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38650.612637 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72252.900232 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66499.869349 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63174.509804 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63174.509804 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65769.729093 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65169.811321 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65550.121337 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65769.729093 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65169.811321 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65550.121337 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.511782 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.977477 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.619749 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.511782 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.977477 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.619749 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65691.484652 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72919.621749 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66493.768040 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63360.457516 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63360.457516 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65691.484652 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65430.875576 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65596.189852 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65691.484652 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65430.875576 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65596.189852 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -728,166 +728,166 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3396 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 431 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3827 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 139 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 139 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 423 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3811 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 152 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 152 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1530 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1530 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5357 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3396 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5357 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 181247500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25841000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 207088500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1390139 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1390139 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77362000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77362000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181247500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 103203000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 284450500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181247500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 103203000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 284450500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926882 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.538332 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5341 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3388 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5341 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 179944250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25531000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 205475250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1520152 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1520152 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77356000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77356000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179944250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102887000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282831250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179944250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102887000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282831250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.538201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993464 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995446 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995446 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979520 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.619593 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979520 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.619593 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53370.877503 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59955.916473 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54112.490201 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977477 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.619749 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50559.477124 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50559.477124 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53112.234357 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53112.234357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1435.278677 # Cycle average of tags in use -system.cpu.dcache.total_refs 66130970 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1999 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33082.026013 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1435.278677 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.350410 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.350410 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45616715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45616715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514054 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514054 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66130769 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66130769 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66130769 # number of overall hits -system.cpu.dcache.overall_hits::total 66130769 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 933 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 933 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1677 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1677 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses -system.cpu.dcache.overall_misses::total 2610 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56235500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56235500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104835500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104835500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 161071000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 161071000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 161071000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 161071000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45617648 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45617648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 56 # number of replacements +system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66124025 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33111.680020 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1433.333580 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349935 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349935 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 45609763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45609763 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514039 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514039 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66123802 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66123802 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66123802 # number of overall hits +system.cpu.dcache.overall_hits::total 66123802 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 934 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 934 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1692 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1692 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2626 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2626 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2626 # number of overall misses +system.cpu.dcache.overall_misses::total 2626 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55899820 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55899820 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 106273652 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 106273652 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 162173472 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 162173472 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 162173472 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 162173472 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45610697 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45610697 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66133379 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66133379 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66133379 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66133379 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 66126428 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66126428 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66126428 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66126428 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60273.847803 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60273.847803 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62513.714967 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62513.714967 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61713.026820 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61713.026820 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59849.914347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59849.914347 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62809.486998 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62809.486998 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61756.843869 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61756.843869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61756.843869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61756.843869 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 228 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 76 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 466 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 466 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1675 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1675 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32012500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32012500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101366000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101366000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133378500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 133378500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133378500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 133378500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 14 # number of writebacks +system.cpu.dcache.writebacks::total 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 472 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 472 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 475 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 475 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 475 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 475 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1689 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1689 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2151 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2151 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31756250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31756250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 102039098 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 102039098 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133795348 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 133795348 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133795348 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 133795348 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68696.351931 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68696.351931 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60517.014925 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60517.014925 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68736.471861 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68736.471861 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60413.912374 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60413.912374 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62201.463505 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62201.463505 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62201.463505 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62201.463505 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index db00eb843..8e5c309b6 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -69,15 +69,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 501907914 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.tagsinuse 1455.296642 # Cycle average of tags in use -system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2836 # number of replacements +system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits @@ -147,19 +147,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2058.178686 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.062811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits @@ -283,15 +283,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.tagsinuse 1363.457571 # Cycle average of tags in use -system.cpu.dcache.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 41 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index e45dffe9c..59af5be58 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,53 +1,53 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.870325 # Number of seconds simulated -sim_ticks 1870325497500 # Number of ticks simulated -final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.870336 # Number of seconds simulated +sim_ticks 1870335643500 # Number of ticks simulated +final_tick 1870335643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3096593 # Simulator instruction rate (inst/s) -host_op_rate 3096591 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91710635166 # Simulator tick rate (ticks/s) +host_inst_rate 1417566 # Simulator instruction rate (inst/s) +host_op_rate 1417565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41981821830 # Simulator tick rate (ticks/s) host_mem_usage 308248 # Number of bytes of host memory used -host_seconds 20.39 # Real time elapsed on the host -sim_insts 63151114 # Number of instructions simulated -sim_ops 63151114 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66666560 # Number of bytes read from this memory +host_seconds 44.55 # Real time elapsed on the host +sim_insts 63154034 # Number of instructions simulated +sim_ops 63154034 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 111168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 681792 # Number of bytes read from this memory -system.physmem.bytes_read::total 70870016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 760896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 111168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7852480 # Number of bytes written to this memory -system.physmem.bytes_written::total 7852480 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1041665 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory +system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory +system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1737 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10653 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1107344 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122695 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122695 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 406825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35644362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1416652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 364531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37891809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 406825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4198456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4198456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4198456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 406825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35644362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1416652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35658336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37898823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4203258 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4203258 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4203258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35658336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42102082 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -194,126 +194,126 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689829 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 103642 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 37651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716104 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816628 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816628 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 188 # 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number of overall (read+write) accesses +system.l2c.overall_accesses::total 3021994 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548438 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346466 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.827160 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.919643 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.880829 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.409214 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548435 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016731 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024116 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346561 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.410391 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.403441 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409847 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528545 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352807 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528696 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016731 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.171591 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352967 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528545 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352807 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528696 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016731 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.171591 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352967 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -322,34 +322,34 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81175 # number of writebacks -system.l2c.writebacks::total 81175 # number of writebacks +system.l2c.writebacks::writebacks 81316 # number of writebacks +system.l2c.writebacks::total 81316 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.435353 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685787105067 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.435353 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.027210 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.027210 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.435438 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.435438 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -385,22 +385,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9148429 # DTB read hits +system.cpu0.dtb.read_hits 9154530 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.write_hits 5932048 # DTB write hits +system.cpu0.dtb.write_hits 5936899 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses system.cpu0.dtb.write_acv 99 # DTB write access violations system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.data_hits 15080477 # DTB hits +system.cpu0.dtb.data_hits 15091429 # DTB hits system.cpu0.dtb.data_misses 7805 # DTB misses system.cpu0.dtb.data_acv 251 # DTB access violations system.cpu0.dtb.data_accesses 698037 # DTB accesses -system.cpu0.itb.fetch_hits 3854196 # ITB hits +system.cpu0.itb.fetch_hits 3855556 # ITB hits system.cpu0.itb.fetch_misses 3485 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3857681 # ITB accesses +system.cpu0.itb.fetch_accesses 3859041 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -413,55 +413,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740650883 # number of cpu cycles simulated +system.cpu0.numCycles 3740671175 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57184467 # Number of instructions committed -system.cpu0.committedOps 57184467 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 53214865 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 299670 # Number of float alu accesses -system.cpu0.num_func_calls 1398025 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6803964 # number of instructions that are conditional controls -system.cpu0.num_int_insts 53214865 # number of integer instructions -system.cpu0.num_fp_insts 299670 # number of float instructions -system.cpu0.num_int_register_reads 73271755 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39802131 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 147658 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 150767 # number of times the floating registers were written -system.cpu0.num_mem_refs 15124548 # number of memory refs -system.cpu0.num_load_insts 9178366 # Number of load instructions -system.cpu0.num_store_insts 5946182 # Number of store instructions -system.cpu0.num_idle_cycles 3683454681.064560 # Number of idle cycles -system.cpu0.num_busy_cycles 57196201.935440 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles +system.cpu0.committedInsts 57222076 # Number of instructions committed +system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses +system.cpu0.num_func_calls 1399585 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls +system.cpu0.num_int_insts 53249924 # number of integer instructions +system.cpu0.num_fp_insts 299810 # number of float instructions +system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written +system.cpu0.num_mem_refs 15135515 # number of memory refs +system.cpu0.num_load_insts 9184477 # Number of load instructions +system.cpu0.num_store_insts 5951038 # Number of store instructions +system.cpu0.num_idle_cycles 3683437331.313678 # Number of idle cycles +system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6280 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 196965 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 70940 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101631 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174730 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69573 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69565 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 141297 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1852985718000 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1852989887500 99.07% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 17236468500 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1870325290000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980730 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1870335436000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684486 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808659 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -494,37 +494,37 @@ system.cpu0.kern.syscall::144 2 0.88% 99.12% # nu system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 226 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 111 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3760 2.05% 2.12% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 167897 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal::rdps 6134 3.35% 97.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183136 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7089 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches +system.cpu0.kern.callpal::total 183291 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1155 -system.cpu0.kern.mode_good::user 1156 +system.cpu0.kern.mode_good::kernel 1157 +system.cpu0.kern.mode_good::user 1158 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.162928 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280291 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1869368290000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1869378426000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3761 # number of times the context was actually changed +system.cpu0.kern.swap_context 3763 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -556,44 +556,44 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 131960056 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 246797826 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10432 # Total snoop data (bytes) -system.iobus.throughput 1460513 # Throughput (bytes/s) -system.iobus.data_through_bus 2731634 # Total data (bytes) -system.cpu0.icache.replacements 883989 # number of replacements -system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use -system.cpu0.icache.total_refs 56307893 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 884501 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 63.660632 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.244895 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 56307893 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 56307893 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56307893 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 56307893 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56307893 # number of overall hits -system.cpu0.icache.overall_hits::total 56307893 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 884630 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 884630 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 884630 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 884630 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 884630 # number of overall misses -system.cpu0.icache.overall_misses::total 884630 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57192523 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 57192523 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57192523 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 57192523 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57192523 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 57192523 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015468 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015468 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015468 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015468 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015468 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015468 # miss rate for overall accesses +system.toL2Bus.throughput 131930075 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 246743154 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes) +system.iobus.throughput 1460500 # Throughput (bytes/s) +system.iobus.data_through_bus 2731626 # Total data (bytes) +system.cpu0.icache.tags.replacements 884406 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 56345130 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 884918 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 63.672713 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 56345130 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 56345130 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56345130 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 56345130 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56345130 # number of overall hits +system.cpu0.icache.overall_hits::total 56345130 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 885002 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 885002 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 885002 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 885002 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 885002 # number of overall misses +system.cpu0.icache.overall_misses::total 885002 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,63 +603,63 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978248 # number of replacements -system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13113195 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1978760 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.626976 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7292594 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7292594 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12750381 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12750381 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12750381 # number of overall hits -system.cpu0.dcache.overall_hits::total 12750381 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683136 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683136 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1968934 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1968934 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1968934 # number of overall misses -system.cpu0.dcache.overall_misses::total 1968934 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5743585 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188129 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 188129 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187169 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187169 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14719315 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187521 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187521 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085856 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003879 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003879 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133765 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133765 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133765 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133765 # miss rate for overall accesses +system.cpu0.dcache.tags.replacements 1978683 # number of replacements +system.cpu0.dcache.tags.tagsinuse 507.129817 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13123756 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1979195 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.630855 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129817 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7298341 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7298341 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5462261 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5462261 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186623 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 186623 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12760602 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12760602 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12760602 # number of overall hits +system.cpu0.dcache.overall_hits::total 12760602 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683328 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683328 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 286000 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 286000 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 715 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 715 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1969328 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1969328 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1969328 # number of overall misses +system.cpu0.dcache.overall_misses::total 1969328 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187418 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187418 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003817 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003817 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -668,29 +668,29 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 775494 # number of writebacks -system.cpu0.dcache.writebacks::total 775494 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775614 # number of writebacks +system.cpu0.dcache.writebacks::total 775614 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1169160 # DTB read hits +system.cpu1.dtb.read_hits 1163439 # DTB read hits system.cpu1.dtb.read_misses 3277 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 220342 # DTB read accesses -system.cpu1.dtb.write_hits 755883 # DTB write hits +system.cpu1.dtb.write_hits 751446 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_accesses 103280 # DTB write accesses -system.cpu1.dtb.data_hits 1925043 # DTB hits +system.cpu1.dtb.data_hits 1914885 # DTB hits system.cpu1.dtb.data_misses 3692 # DTB misses system.cpu1.dtb.data_acv 116 # DTB access violations system.cpu1.dtb.data_accesses 323622 # DTB accesses -system.cpu1.itb.fetch_hits 1469677 # ITB hits +system.cpu1.itb.fetch_hits 1468399 # ITB hits system.cpu1.itb.fetch_misses 1539 # ITB misses system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1471216 # ITB accesses +system.cpu1.itb.fetch_accesses 1469938 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -703,51 +703,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3740237218 # number of cpu cycles simulated +system.cpu1.numCycles 3740249123 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5966647 # Number of instructions committed -system.cpu1.committedOps 5966647 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 5582916 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 28730 # Number of float alu accesses -system.cpu1.num_func_calls 184190 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 581489 # number of instructions that are conditional controls -system.cpu1.num_int_insts 5582916 # number of integer instructions -system.cpu1.num_fp_insts 28730 # number of float instructions -system.cpu1.num_int_register_reads 7700123 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4186358 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 17955 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 17751 # number of times the floating registers were written -system.cpu1.num_mem_refs 1936419 # number of memory refs -system.cpu1.num_load_insts 1176619 # Number of load instructions -system.cpu1.num_store_insts 759800 # Number of store instructions -system.cpu1.num_idle_cycles 3734265828.606121 # Number of idle cycles -system.cpu1.num_busy_cycles 5971389.393879 # Number of busy cycles -system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles +system.cpu1.committedInsts 5931958 # Number of instructions committed +system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses +system.cpu1.num_func_calls 182742 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls +system.cpu1.num_int_insts 5550578 # number of integer instructions +system.cpu1.num_fp_insts 28590 # number of float instructions +system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written +system.cpu1.num_mem_refs 1926244 # number of memory refs +system.cpu1.num_load_insts 1170888 # Number of load instructions +system.cpu1.num_store_insts 755356 # Number of store instructions +system.cpu1.num_idle_cycles 3734312432.077611 # Number of idle cycles +system.cpu1.num_busy_cycles 5936690.922389 # Number of busy cycles +system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10388 33.53% 33.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1907 6.15% 39.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 111 0.36% 40.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18579 59.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30985 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22663 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1859112376500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1859123129500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 14176500 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 10910041500 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1870118595500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999037 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1870124548000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.552613 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.731418 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed @@ -770,67 +770,67 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 472 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26358 81.69% 83.25% # number of callpals executed -system.cpu1.kern.callpal::rdps 2589 8.02% 91.28% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.28% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.29% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 91.30% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.31% # number of callpals executed -system.cpu1.kern.callpal::rti 2608 8.08% 99.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed +system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed +system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 32267 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1034 # number of protection mode switches +system.cpu1.kern.callpal::total 32131 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches system.cpu1.kern.mode_switch::user 580 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 613 +system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 612 system.cpu1.kern.mode_good::user 580 -system.cpu1.kern.mode_good::idle 33 -system.cpu1.kern.mode_switch_good::kernel 0.592843 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 32 +system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.016113 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.334790 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1393260500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1373906500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1867980072500 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 473 # number of times the context was actually changed -system.cpu1.icache.replacements 104103 # number of replacements -system.cpu1.icache.tagsinuse 427.138444 # Cycle average of tags in use -system.cpu1.icache.total_refs 5865807 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 104615 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 56.070420 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868930362000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 427.138444 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.834255 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.834255 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5865807 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5865807 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5865807 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5865807 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5865807 # number of overall hits -system.cpu1.icache.overall_hits::total 5865807 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 104648 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 104648 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 104648 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 104648 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 104648 # number of overall misses -system.cpu1.icache.overall_misses::total 104648 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5970455 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5970455 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5970455 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5970455 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5970455 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5970455 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017528 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.017528 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017528 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.017528 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017528 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.017528 # miss rate for overall accesses +system.cpu1.kern.mode_ticks::idle 1868002681000 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 471 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 103103 # number of replacements +system.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 5832124 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 103615 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 56.286484 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1868933191000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5832124 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5832124 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5832124 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5832124 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5832124 # number of overall hits +system.cpu1.icache.overall_hits::total 5832124 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 103642 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 103642 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 103642 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 103642 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 103642 # number of overall misses +system.cpu1.icache.overall_misses::total 103642 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017461 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017461 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017461 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017461 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017461 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017461 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -840,63 +840,63 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62444 # number of replacements -system.cpu1.dcache.tagsinuse 421.660465 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1845254 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62784 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 29.390514 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851113732500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 421.660465 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.823556 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.823556 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1114890 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1114890 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 711494 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 711494 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15278 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15278 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15743 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15743 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1826384 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1826384 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1826384 # number of overall hits -system.cpu1.dcache.overall_hits::total 1826384 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41651 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41651 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 26091 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 26091 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1291 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1291 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 751 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 751 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67742 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67742 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67742 # number of overall misses -system.cpu1.dcache.overall_misses::total 67742 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1156541 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1156541 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 737585 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 737585 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16569 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 16569 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16494 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 16494 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1894126 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1894126 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1894126 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1894126 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036013 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036013 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035374 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035374 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077917 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.077917 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.045532 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.045532 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035764 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035764 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035764 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035764 # miss rate for overall accesses +system.cpu1.dcache.tags.replacements 62052 # number of replacements +system.cpu1.dcache.tags.tagsinuse 421.569557 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1836045 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 62390 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.428514 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1851115695500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.569557 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823378 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.823378 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1109514 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1109514 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 707455 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 707455 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1816969 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1816969 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1816969 # number of overall hits +system.cpu1.dcache.overall_hits::total 1816969 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41451 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41451 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 25850 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 25850 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 67301 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67301 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67301 # number of overall misses +system.cpu1.dcache.overall_misses::total 67301 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036014 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036014 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035251 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035251 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035717 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035717 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035717 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035717 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -905,8 +905,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 41317 # number of writebacks -system.cpu1.dcache.writebacks::total 41317 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41014 # number of writebacks +system.cpu1.dcache.writebacks::total 41014 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 5057d01db..7cff7197d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.829331 # Number of seconds simulated -sim_ticks 1829330593000 # Number of ticks simulated -final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.829332 # Number of seconds simulated +sim_ticks 1829332269000 # Number of ticks simulated +final_tick 1829332269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1529223 # Simulator instruction rate (inst/s) -host_op_rate 1529222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46594888750 # Simulator tick rate (ticks/s) -host_mem_usage 306208 # Number of bytes of host memory used -host_seconds 39.26 # Real time elapsed on the host -sim_insts 60037737 # Number of instructions simulated -sim_ops 60037737 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory +host_inst_rate 1710493 # Simulator instruction rate (inst/s) +host_op_rate 1710492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52117657653 # Simulator tick rate (ticks/s) +host_mem_usage 306192 # Number of bytes of host memory used +host_seconds 35.10 # Real time elapsed on the host +sim_insts 60038305 # Number of instructions simulated +sim_ops 60038305 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 70349440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7411136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1099210 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115799 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115799 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36537571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1449868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38456384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051283 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051283 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -184,18 +184,18 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests -system.membus.throughput 42552299 # Throughput (bytes/s) -system.membus.data_through_bus 77842222 # Total data (bytes) +system.membus.throughput 42552540 # Throughput (bytes/s) +system.membus.data_through_bus 77842734 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.replacements 41686 # number of replacements -system.iocache.tagsinuse 1.225558 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685780599067 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.225558 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.076597 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.076597 # Average percentage of cache occupancy +system.iocache.tags.replacements 41686 # number of replacements +system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -247,22 +247,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710417 # DTB read hits +system.cpu.dtb.read_hits 9710427 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352487 # DTB write hits +system.cpu.dtb.write_hits 6352498 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062904 # DTB hits +system.cpu.dtb.data_hits 16062925 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974615 # ITB hits +system.cpu.itb.fetch_hits 4974648 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979621 # ITB accesses +system.cpu.itb.fetch_accesses 4979654 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -275,51 +275,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658661078 # number of cpu cycles simulated +system.cpu.numCycles 3658664430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60037737 # Number of instructions committed -system.cpu.committedOps 60037737 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55912968 # Number of integer alu accesses +system.cpu.committedInsts 60038305 # Number of instructions committed +system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1484174 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110641 # number of instructions that are conditional controls -system.cpu.num_int_insts 55912968 # number of integer instructions +system.cpu.num_func_calls 1484182 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913521 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76953007 # number of times the integer registers were read -system.cpu.num_int_register_writes 41739788 # number of times the integer registers were written +system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115688 # number of memory refs -system.cpu.num_load_insts 9747503 # Number of load instructions -system.cpu.num_store_insts 6368185 # Number of store instructions -system.cpu.num_idle_cycles 3598606249.772791 # Number of idle cycles -system.cpu.num_busy_cycles 60054828.227209 # Number of busy cycles -system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983586 # Percentage of idle cycles +system.cpu.num_mem_refs 16115709 # number of memory refs +system.cpu.num_load_insts 9747513 # Number of load instructions +system.cpu.num_store_insts 6368196 # Number of store instructions +system.cpu.num_idle_cycles 3598609001.180807 # Number of idle cycles +system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles +system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983585 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211316 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182559 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811925911500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811927418500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829332061500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816366 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -358,7 +358,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175246 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -367,20 +367,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192177 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch::user 1735 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1735 +system.cpu.kern.callpal::total 192180 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320444 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081506 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.389735 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26832734500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465059000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032591000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801032784000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -413,35 +413,35 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1480182 # Throughput (bytes/s) +system.iobus.throughput 1480181 # Throughput (bytes/s) system.iobus.data_through_bus 2707742 # Total data (bytes) -system.cpu.icache.replacements 919577 # number of replacements -system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use -system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 920089 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 64.264839 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.215229 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59129371 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59129371 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59129371 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59129371 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59129371 # number of overall hits -system.cpu.icache.overall_hits::total 59129371 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920204 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920204 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920204 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920204 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920204 # number of overall misses -system.cpu.icache.overall_misses::total 920204 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60049575 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60049575 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60049575 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60049575 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60049575 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60049575 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 919609 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215244 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59129907 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920121 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263186 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215244 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 59129907 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129907 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59129907 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129907 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59129907 # number of overall hits +system.cpu.icache.overall_hits::total 59129907 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920236 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920236 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920236 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920236 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920236 # number of overall misses +system.cpu.icache.overall_misses::total 920236 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -457,75 +457,75 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920218 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659090 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963437 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511328 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511328 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384814 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384814 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511329 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357073 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511329 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357073 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,58 +534,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks -system.cpu.l2cache.writebacks::total 74287 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks +system.cpu.l2cache.writebacks::total 74291 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042707 # number of replacements -system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits -system.cpu.dcache.overall_hits::total 13655968 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses +system.cpu.dcache.tags.replacements 2042706 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14038427 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043218 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870744 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7807777 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807777 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848211 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848211 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655988 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655988 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655988 # number of overall hits +system.cpu.dcache.overall_hits::total 13655988 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses -system.cpu.dcache.overall_misses::total 2026074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199281 # 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number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses @@ -598,11 +598,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks -system.cpu.dcache.writebacks::total 833491 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833497 # number of writebacks +system.cpu.dcache.writebacks::total 833497 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 132867618 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 243048686 # Total data (bytes) +system.cpu.toL2Bus.throughput 132868790 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 243051054 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index a249cee6b..900001468 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.959865 # Number of seconds simulated -sim_ticks 1959865139500 # Number of ticks simulated -final_tick 1959865139500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961841 # Number of seconds simulated +sim_ticks 1961841175000 # Number of ticks simulated +final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1047911 # Simulator instruction rate (inst/s) -host_op_rate 1047910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33678986014 # Simulator tick rate (ticks/s) -host_mem_usage 308256 # Number of bytes of host memory used -host_seconds 58.19 # Real time elapsed on the host -sim_insts 60980539 # Number of instructions simulated -sim_ops 60980539 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 833408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24886848 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 338688 # Number of bytes read from this memory -system.physmem.bytes_read::total 28741440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 833408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7743232 # Number of bytes written to this memory -system.physmem.bytes_written::total 7743232 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13022 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388857 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5292 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449085 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120988 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120988 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12698245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1352583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 172812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14665009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425237 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441369 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3950900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3950900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3950900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12698245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1352583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 172812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18615909 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449085 # Total number of read requests seen -system.physmem.writeReqs 120988 # Total number of write requests seen -system.physmem.cpureqs 577269 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28741440 # Total number of bytes read from memory -system.physmem.bytesWritten 7743232 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28741440 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7743232 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 62 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 7195 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27763 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28133 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28495 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28031 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7895 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7532 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7275 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7314 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7257 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7316 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7066 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7523 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7683 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8132 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8336 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7679 # Track writes on a per bank basis +host_inst_rate 1094895 # Simulator instruction rate (inst/s) +host_op_rate 1094895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36191186298 # Simulator tick rate (ticks/s) +host_mem_usage 308248 # Number of bytes of host memory used +host_seconds 54.21 # Real time elapsed on the host +sim_insts 59351715 # Number of instructions simulated +sim_ops 59351715 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24914752 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 32192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 287808 # Number of bytes read from this memory +system.physmem.bytes_read::total 28716928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 831360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 32192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7746368 # Number of bytes written to this memory +system.physmem.bytes_written::total 7746368 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12990 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389293 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 503 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 4497 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448702 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121037 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121037 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 423765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12699678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 146703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14637744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 423765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3948519 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3948519 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3948519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 423765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12699678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448702 # Total number of read requests seen +system.physmem.writeReqs 121037 # Total number of write requests seen +system.physmem.cpureqs 572905 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28716928 # Total number of bytes read from memory +system.physmem.bytesWritten 7746368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28314 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28019 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28118 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27836 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27466 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27905 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27953 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27826 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28040 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28581 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28092 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28236 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7663 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7614 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7774 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7534 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7314 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6876 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7222 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7326 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7591 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8207 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7890 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1959858128500 # Total gap between requests +system.physmem.totGap 1961833946000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 449085 # Categorize read packet sizes +system.physmem.readPktSize::6 448702 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 120988 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 408321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3003 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1429 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121037 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 407897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 99 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -138,391 +138,386 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40092 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 909.867305 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 223.303664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2368.170282 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14180 35.37% 35.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6168 15.38% 50.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3902 9.73% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2490 6.21% 66.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1693 4.22% 70.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1359 3.39% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1096 2.73% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 872 2.17% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 629 1.57% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 634 1.58% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 494 1.23% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 427 1.07% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 257 0.64% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 230 0.57% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 171 0.43% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 248 0.62% 86.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 146 0.36% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 121 0.30% 87.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 95 0.24% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 102 0.25% 88.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 86 0.21% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 112 0.28% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1028 2.56% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 203 0.51% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 118 0.29% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 93 0.23% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 68 0.17% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 46 0.11% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 38 0.09% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 17 0.04% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 32 0.08% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 9 0.02% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 5 0.01% 92.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 7 0.02% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 4 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.00% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 2 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 4 0.01% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 2 0.00% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 3 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 3 0.01% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 2 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 3 0.01% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 2 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 6 0.01% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2435 6.07% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 39515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 922.589599 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 226.543369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2381.494153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 13878 35.12% 35.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6056 15.33% 50.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3741 9.47% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2391 6.05% 65.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1744 4.41% 70.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1425 3.61% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1039 2.63% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 750 1.90% 78.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 668 1.69% 80.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 592 1.50% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 528 1.34% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 459 1.16% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 301 0.76% 84.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 245 0.62% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 187 0.47% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 264 0.67% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 137 0.35% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 111 0.28% 87.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 92 0.23% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 96 0.24% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 88 0.22% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 105 0.27% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 1100 2.78% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 187 0.47% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 132 0.33% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 88 0.22% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 54 0.14% 92.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 43 0.11% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 23 0.06% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 21 0.05% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 20 0.05% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 29 0.07% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 11 0.03% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 14 0.04% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 4 0.01% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 6 0.02% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.00% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 2 0.01% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 4 0.01% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 4 0.01% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 2 0.01% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 3 0.01% 92.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 3 0.01% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 4 0.01% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 2 0.01% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 3 0.01% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 2 0.01% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.01% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.01% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.01% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 6 0.02% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2432 6.15% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 3 0.01% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 243 0.61% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 6 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 10 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 2 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 242 0.61% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 10 0.03% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 6 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 6 0.02% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17155 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40092 # Bytes accessed per row activation -system.physmem.totQLat 3740449750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12011516000 # Sum of mem lat for all requests -system.physmem.totBusLat 2245115000 # Total cycles spent in databus access -system.physmem.totBankLat 6025951250 # Total cycles spent in bank access -system.physmem.avgQLat 8330.20 # Average queueing delay per request -system.physmem.avgBankLat 13420.14 # Average bank access latency per request +system.physmem.bytesPerActivate::17984-17987 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39515 # Bytes accessed per row activation +system.physmem.totQLat 3750140000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12006448750 # Sum of mem lat for all requests +system.physmem.totBusLat 2243145000 # Total cycles spent in databus access +system.physmem.totBankLat 6013163750 # Total cycles spent in bank access +system.physmem.avgQLat 8359.11 # Average queueing delay per request +system.physmem.avgBankLat 13403.42 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26750.34 # Average memory access latency -system.physmem.avgRdBW 14.67 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26762.53 # Average memory access latency +system.physmem.avgRdBW 14.64 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.67 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.64 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.21 # Average write queue length over time -system.physmem.readRowHits 433314 # Number of row buffer hits during reads -system.physmem.writeRowHits 96597 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.84 # Row buffer hit rate for writes -system.physmem.avgGap 3437907.30 # Average gap between requests -system.membus.throughput 18676649 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292796 # Transaction distribution -system.membus.trans_dist::ReadResp 292796 # Transaction distribution -system.membus.trans_dist::WriteReq 14151 # Transaction distribution -system.membus.trans_dist::WriteResp 14151 # Transaction distribution -system.membus.trans_dist::Writeback 120988 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16779 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11846 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7198 # Transaction distribution -system.membus.trans_dist::ReadExReq 164928 # Transaction distribution -system.membus.trans_dist::ReadExResp 164057 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 974452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 42700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1056418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1099118 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82626 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31259138 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 82626 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36484672 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36567298 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36567298 # Total data (bytes) -system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 43346000 # Layer occupancy (ticks) +system.physmem.avgWrQLen 6.90 # Average write queue length over time +system.physmem.readRowHits 433153 # Number of row buffer hits during reads +system.physmem.writeRowHits 96987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes +system.physmem.avgGap 3443390.65 # Average gap between requests +system.membus.throughput 18639952 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292620 # Transaction distribution +system.membus.trans_dist::ReadResp 292620 # Transaction distribution +system.membus.trans_dist::WriteReq 12397 # Transaction distribution +system.membus.trans_dist::WriteResp 12397 # Transaction distribution +system.membus.trans_dist::Writeback 121037 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4186 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 858 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3168 # Transaction distribution +system.membus.trans_dist::ReadExReq 163944 # Transaction distribution +system.membus.trans_dist::ReadExResp 163855 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39192 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 39192 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1027313 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 36463296 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36531890 # Total data (bytes) +system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 39129000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1579141500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1559666750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3832845053 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3812357322 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376210250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.replacements 342163 # number of replacements -system.l2c.tagsinuse 65224.613124 # Cycle average of tags in use -system.l2c.total_refs 2440483 # Total number of references to valid blocks. -system.l2c.sampled_refs 407350 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.991121 # Average number of references to valid blocks. -system.l2c.warmup_cycle 8355445750 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55361.728852 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4802.377103 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4855.919486 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 161.173506 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 43.414178 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.844753 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073278 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.074095 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002459 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000662 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995249 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 678870 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 661225 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 323259 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 109447 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1772801 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 790404 # number of Writeback hits -system.l2c.Writeback_hits::total 790404 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 565 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 747 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 127727 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 43997 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171724 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 678870 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 788952 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 323259 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 153444 # number of demand (read+write) hits -system.l2c.demand_hits::total 1944525 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 678870 # number of overall hits -system.l2c.overall_hits::cpu0.data 788952 # number of overall hits -system.l2c.overall_hits::cpu1.inst 323259 # number of overall hits -system.l2c.overall_hits::cpu1.data 153444 # number of overall hits -system.l2c.overall_hits::total 1944525 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13022 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271666 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 241 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285434 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2971 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1796 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4767 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 957 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 952 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1909 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117966 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5061 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123027 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13022 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389632 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 505 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 5302 # number of demand (read+write) misses -system.l2c.demand_misses::total 408461 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13022 # number of overall misses -system.l2c.overall_misses::cpu0.data 389632 # number of overall misses -system.l2c.overall_misses::cpu1.inst 505 # number of overall misses -system.l2c.overall_misses::cpu1.data 5302 # number of overall misses -system.l2c.overall_misses::total 408461 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1040882000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 16855181499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 39850000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 21000500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17956913999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1322500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10129500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11452000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 954000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 204000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1158000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7822362000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 373828000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8196190000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1040882000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 24677543499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 39850000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 394828500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 26153103999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1040882000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 24677543499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 39850000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 394828500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 26153103999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 691892 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 932891 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 323764 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 109688 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2058235 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 790404 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 790404 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3153 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2361 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5514 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 995 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 975 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1970 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 245693 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 49058 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 294751 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 691892 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1178584 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 323764 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 158746 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2352986 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 691892 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1178584 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 323764 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 158746 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2352986 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018821 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.291209 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.001560 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002197 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138679 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942277 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760695 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.864527 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961809 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976410 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.969036 # 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number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -695,40 +693,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123321.166667 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123321.166667 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 250676.478557 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 250676.478557 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250145.399032 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250145.399032 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250145.399032 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250145.399032 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 272227 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123106.084270 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123106.084270 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251231.096482 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 251231.096482 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 250684.577139 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 250684.577139 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 274830 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27211 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27442 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.004300 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.014941 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12409133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12409133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8254729537 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8254729537 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8267138670 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8267138670 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8267138670 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8267138670 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12655383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12655383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8277077521 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8277077521 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8289732904 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8289732904 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8289732904 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8289732904 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -737,14 +735,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71316.856322 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71316.856322 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 198660.221818 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 198660.221818 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198129.192110 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198129.192110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198129.192110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198129.192110 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71097.657303 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71097.657303 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199198.053547 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199198.053547 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -762,22 +760,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7504093 # DTB read hits +system.cpu0.dtb.read_hits 8725663 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5095666 # DTB write hits +system.cpu0.dtb.write_hits 6139453 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12599759 # DTB hits +system.cpu0.dtb.data_hits 14865116 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3641096 # ITB hits +system.cpu0.itb.fetch_hits 4015307 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3645080 # ITB accesses +system.cpu0.itb.fetch_accesses 4019291 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -790,55 +788,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3919730279 # number of cpu cycles simulated +system.cpu0.numCycles 3923682350 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47851975 # Number of instructions committed -system.cpu0.committedOps 47851975 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44398232 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 209056 # Number of float alu accesses -system.cpu0.num_func_calls 1198231 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5625657 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44398232 # number of integer instructions -system.cpu0.num_fp_insts 209056 # number of float instructions -system.cpu0.num_int_register_reads 61087554 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33073995 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102127 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 103890 # number of times the floating registers were written -system.cpu0.num_mem_refs 12640550 # number of memory refs -system.cpu0.num_load_insts 7531710 # Number of load instructions -system.cpu0.num_store_insts 5108840 # Number of store instructions -system.cpu0.num_idle_cycles 3699529015.998113 # Number of idle cycles -system.cpu0.num_busy_cycles 220201263.001888 # Number of busy cycles -system.cpu0.not_idle_fraction 0.056178 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.943822 # Percentage of idle cycles +system.cpu0.committedInsts 54601969 # Number of instructions committed +system.cpu0.committedOps 54601969 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50544405 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 297630 # Number of float alu accesses +system.cpu0.num_func_calls 1438477 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6291508 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50544405 # number of integer instructions +system.cpu0.num_fp_insts 297630 # number of float instructions +system.cpu0.num_int_register_reads 69247284 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37427910 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 145753 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 148838 # number of times the floating registers were written +system.cpu0.num_mem_refs 14912078 # number of memory refs +system.cpu0.num_load_insts 8757685 # Number of load instructions +system.cpu0.num_store_insts 6154393 # Number of store instructions +system.cpu0.num_idle_cycles 3674902109.498127 # Number of idle cycles +system.cpu0.num_busy_cycles 248780240.501873 # Number of busy cycles +system.cpu0.not_idle_fraction 0.063405 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.936595 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6830 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164217 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56358 40.22% 40.22% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.41% 41.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 445 0.32% 42.04% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81223 57.96% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 140130 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55870 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.73% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 445 0.39% 51.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55425 48.69% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113844 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1901694919500 97.03% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94927000 0.00% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 766727000 0.04% 97.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 329552000 0.02% 97.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56978256500 2.91% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1959864382000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991341 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 204697 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 73289 40.68% 40.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.75% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.10% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 104766 58.15% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 180167 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71920 49.28% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 1.35% 50.72% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71914 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 145946 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1899196330000 96.81% 96.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95025500 0.00% 96.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 769055500 0.04% 96.85% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5164500 0.00% 96.85% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 61774827500 3.15% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961840403000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981321 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682381 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812417 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.686425 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810060 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -870,37 +868,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 528 0.36% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3061 2.06% 2.42% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal::swpipl 133182 89.70% 92.16% # number of callpals executed -system.cpu0.kern.callpal::rdps 6700 4.51% 96.67% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.67% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.67% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.68% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::rti 4398 2.96% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 148480 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6996 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches +system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3942 2.08% 2.13% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.16% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.16% # number of callpals executed +system.cpu0.kern.callpal::swpipl 173212 91.45% 93.61% # number of callpals executed +system.cpu0.kern.callpal::rdps 6702 3.54% 97.15% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::rti 4842 2.56% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 189397 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7440 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1372 -system.cpu0.kern.mode_good::user 1373 +system.cpu0.kern.mode_good::kernel 1368 +system.cpu0.kern.mode_good::user 1369 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.196112 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.183871 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327996 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1956039363000 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3825014500 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.310705 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958025785500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3814613000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3062 # number of times the context was actually changed +system.cpu0.kern.swap_context 3943 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -932,47 +930,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 103923821 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2101274 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2101259 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14151 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14151 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 790404 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17004 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11907 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28911 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 338243 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296693 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1383805 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3109039 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 647529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 472865 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5613238 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 44281088 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118941040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 20720896 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 17326866 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 201269890 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 201259586 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2417088 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4784493652 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.throughput 105075557 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2099191 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2099176 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12397 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12397 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 820882 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4248 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 894 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1842377 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3534341 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 160357 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 115223 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5652298 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 58955328 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 137106504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 5131392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 4050090 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 205243314 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 205232754 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3113609997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4148559004 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5406966495 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 6195378103 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1456953977 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 808879499 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 360929992 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 206344318 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1400220 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55703 # Transaction distribution -system.iobus.trans_dist::WriteResp 55703 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1391673 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7377 # Transaction distribution +system.iobus.trans_dist::ReadResp 7377 # Transaction distribution +system.iobus.trans_dist::WriteReq 53949 # Transaction distribution +system.iobus.trans_dist::WriteResp 53949 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -984,10 +982,10 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -998,10 +996,10 @@ system.iobus.pkt_count::system.tsunami.ide.pio 6672 system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126152 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1013,10 +1011,10 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 82626 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 56360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1027,11 +1025,11 @@ system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2744242 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2744242 # Total data (bytes) -system.iobus.reqLayer0.occupancy 13445000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2730242 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1053,59 +1051,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378246920 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 378297154 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28549000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26795000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.replacements 691283 # number of replacements -system.cpu0.icache.tagsinuse 508.523038 # Cycle average of tags in use -system.cpu0.icache.total_refs 47169081 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 691795 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.183611 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 38900732000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.523038 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993209 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993209 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 47169081 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47169081 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47169081 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47169081 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47169081 # number of overall hits -system.cpu0.icache.overall_hits::total 47169081 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 691913 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 691913 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 691913 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 691913 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 691913 # number of overall misses -system.cpu0.icache.overall_misses::total 691913 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9946018500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9946018500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9946018500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9946018500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9946018500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9946018500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47860994 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47860994 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47860994 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47860994 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47860994 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47860994 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014457 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014457 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014457 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014457 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014457 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014457 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14374.666324 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14374.666324 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14374.666324 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14374.666324 # average overall miss latency +system.cpu0.icache.tags.replacements 920572 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993168 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53689788 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53689788 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53689788 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53689788 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53689788 # number of overall hits +system.cpu0.icache.overall_hits::total 53689788 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 921200 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 921200 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 921200 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 921200 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 921200 # number of overall misses +system.cpu0.icache.overall_misses::total 921200 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12937764004 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12937764004 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12937764004 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12937764004 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12937764004 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12937764004 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54610988 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54610988 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54610988 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54610988 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54610988 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54610988 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016868 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016868 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016868 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016868 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016868 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016868 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14044.468089 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14044.468089 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14044.468089 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14044.468089 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1114,112 +1112,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 691913 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 691913 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 691913 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 691913 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 691913 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 691913 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8562191003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8562191003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8562191003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8562191003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8562191003 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8562191003 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014457 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014457 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014457 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12374.664160 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 921200 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 921200 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 921200 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 921200 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 921200 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 921200 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11089045996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11089045996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11089045996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11089045996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11089045996 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11089045996 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016868 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016868 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016868 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12037.609635 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1181525 # number of replacements -system.cpu0.dcache.tagsinuse 505.231432 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11411955 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1182037 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.654482 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 105721000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.231432 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986780 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986780 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6427043 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6427043 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4684362 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4684362 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139576 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139576 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146814 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 146814 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11111405 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11111405 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11111405 # number of overall hits -system.cpu0.dcache.overall_hits::total 11111405 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 936498 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 936498 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 255602 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 255602 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13508 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5738 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5738 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1192100 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1192100 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1192100 # number of overall misses -system.cpu0.dcache.overall_misses::total 1192100 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26205591500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26205591500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9945079500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9945079500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 146904500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 146904500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44028500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44028500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 36150671000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 36150671000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 36150671000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 36150671000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7363541 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7363541 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4939964 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4939964 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153084 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 153084 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152552 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 152552 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12303505 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12303505 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12303505 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12303505 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127180 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127180 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051742 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051742 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088239 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088239 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037613 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037613 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096891 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.096891 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096891 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.096891 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27982.538671 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27982.538671 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38908.457289 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38908.457289 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10875.370151 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10875.370151 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7673.143953 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7673.143953 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30325.200067 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30325.200067 # average overall miss latency +system.cpu0.dcache.tags.replacements 1349865 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5646858 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177791 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 177791 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 193304 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 193304 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 13154053 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 13154053 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 13154053 # number of overall hits +system.cpu0.dcache.overall_hits::total 13154053 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1040730 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1040730 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 297940 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 297940 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16884 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16884 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 399 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 399 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1338670 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1338670 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1338670 # number of overall misses +system.cpu0.dcache.overall_misses::total 1338670 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27787431256 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27787431256 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10644315314 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10644315314 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 223091000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 223091000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2495533 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 2495533 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38431746570 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38431746570 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38431746570 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38431746570 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8547925 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8547925 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5944798 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5944798 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194675 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 194675 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193703 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 193703 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14492723 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14492723 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14492723 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14492723 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.121752 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.121752 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050118 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.050118 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086729 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086729 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002060 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002060 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092368 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092368 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092368 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092368 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26699.942594 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26699.942594 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35726.372135 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35726.372135 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13213.160389 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13213.160389 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6254.468672 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6254.468672 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 28708.902545 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 28708.902545 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1228,62 +1226,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 678820 # number of writebacks -system.cpu0.dcache.writebacks::total 678820 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 936498 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 936498 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255602 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 255602 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13508 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13508 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5737 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5737 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1192100 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1192100 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1192100 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1192100 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24332593005 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24332593005 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9433875500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9433875500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 119888500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 119888500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32554500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32554500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 33766468505 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 33766468505 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 33766468505 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 33766468505 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465600500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465600500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2289389000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2289389000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3754989500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3754989500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127180 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127180 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051742 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051742 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088239 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088239 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037607 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037607 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096891 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096891 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096891 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096891 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25982.536006 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25982.536006 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36908.457289 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36908.457289 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8875.370151 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8875.370151 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5674.481436 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5674.481436 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 798646 # number of writebacks +system.cpu0.dcache.writebacks::total 798646 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1040730 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1040730 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297940 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 297940 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16884 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16884 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 399 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 399 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1338670 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1338670 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1338670 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1338670 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25571734744 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25571734744 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9990567686 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9990567686 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 189290000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 189290000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1697467 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1697467 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35562302430 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35562302430 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35562302430 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35562302430 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465580500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465580500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2094321000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2094321000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3559901500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3559901500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121752 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121752 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050118 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050118 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086729 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086729 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002060 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002060 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092368 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092368 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24570.959561 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24570.959561 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33532.146358 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33532.146358 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11211.205875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11211.205875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4254.303258 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4254.303258 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1295,22 +1293,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2417907 # DTB read hits +system.cpu1.dtb.read_hits 957039 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1735068 # DTB write hits +system.cpu1.dtb.write_hits 556340 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4152975 # DTB hits +system.cpu1.dtb.data_hits 1513379 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1826925 # ITB hits +system.cpu1.itb.fetch_hits 1320031 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1827989 # ITB accesses +system.cpu1.itb.fetch_accesses 1321095 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1323,51 +1321,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3917974909 # number of cpu cycles simulated +system.cpu1.numCycles 3921887017 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13128564 # Number of instructions committed -system.cpu1.committedOps 13128564 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12090481 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 177902 # Number of float alu accesses -system.cpu1.num_func_calls 416956 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1297332 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12090481 # number of integer instructions -system.cpu1.num_fp_insts 177902 # number of float instructions -system.cpu1.num_int_register_reads 16603924 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8888139 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 92328 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 94344 # number of times the floating registers were written -system.cpu1.num_mem_refs 4176284 # number of memory refs -system.cpu1.num_load_insts 2431879 # Number of load instructions -system.cpu1.num_store_insts 1744405 # Number of store instructions -system.cpu1.num_idle_cycles 3867819461.141509 # Number of idle cycles -system.cpu1.num_busy_cycles 50155447.858491 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012801 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987199 # Percentage of idle cycles +system.cpu1.committedInsts 4749746 # Number of instructions committed +system.cpu1.committedOps 4749746 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4446088 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 30301 # Number of float alu accesses +system.cpu1.num_func_calls 145582 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 455512 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4446088 # number of integer instructions +system.cpu1.num_fp_insts 30301 # number of float instructions +system.cpu1.num_int_register_reads 6169769 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3384887 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 19629 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 19442 # number of times the floating registers were written +system.cpu1.num_mem_refs 1521715 # number of memory refs +system.cpu1.num_load_insts 962201 # Number of load instructions +system.cpu1.num_store_insts 559514 # Number of store instructions +system.cpu1.num_idle_cycles 3904242469.193159 # Number of idle cycles +system.cpu1.num_busy_cycles 17644547.806841 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004499 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995501 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 79425 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27091 38.34% 38.34% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.79% 41.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 528 0.75% 41.87% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41074 58.13% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 70662 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26202 48.19% 48.19% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.62% 51.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 528 0.97% 52.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25675 47.22% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 54374 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1908747944000 97.44% 97.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700841000 0.04% 97.47% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 369371500 0.02% 97.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 49169268000 2.51% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1958987424500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967185 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2329 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 33659 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 8392 30.97% 30.97% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1970 7.27% 38.24% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 88 0.32% 38.57% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 16645 61.43% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 27095 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 8384 44.74% 44.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1970 10.51% 55.26% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 88 0.47% 55.73% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 8296 44.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 18738 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1917649813500 97.79% 97.79% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700167000 0.04% 97.83% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 60318500 0.00% 97.83% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 42533179500 2.17% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960943478500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999047 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625091 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769494 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.498408 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.691567 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1383,81 +1381,81 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 445 0.61% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2045 2.80% 3.42% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.42% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.43% # number of callpals executed -system.cpu1.kern.callpal::swpipl 64414 88.26% 91.69% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 2.94% 94.63% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.63% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.63% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.64% # number of callpals executed -system.cpu1.kern.callpal::rti 3751 5.14% 99.78% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 283 1.02% 1.06% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.07% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.03% 1.09% # number of callpals executed +system.cpu1.kern.callpal::swpipl 22604 81.73% 82.82% # number of callpals executed +system.cpu1.kern.callpal::rdps 2147 7.76% 90.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 90.60% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 90.61% # number of callpals executed +system.cpu1.kern.callpal::rti 2432 8.79% 99.41% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.44% 99.84% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 72984 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1994 # number of protection mode switches -system.cpu1.kern.mode_switch::user 369 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 821 -system.cpu1.kern.mode_good::user 369 -system.cpu1.kern.mode_good::idle 452 -system.cpu1.kern.mode_switch_good::kernel 0.411735 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 27656 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 652 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 379 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 12 +system.cpu1.kern.mode_switch_good::kernel 0.581288 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.154636 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.310632 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18283551000 0.93% 0.93% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1485621000 0.08% 1.01% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1938326244500 98.99% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2046 # number of times the context was actually changed -system.cpu1.icache.replacements 323214 # number of replacements -system.cpu1.icache.tagsinuse 446.824291 # Cycle average of tags in use -system.cpu1.icache.total_refs 12807678 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 323725 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 39.563450 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1958057375000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 446.824291 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.872704 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.872704 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 12807678 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12807678 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12807678 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12807678 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12807678 # number of overall hits -system.cpu1.icache.overall_hits::total 12807678 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 323765 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 323765 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 323765 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 323765 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 323765 # number of overall misses -system.cpu1.icache.overall_misses::total 323765 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4261948000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4261948000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4261948000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4261948000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4261948000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4261948000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13131443 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13131443 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13131443 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13131443 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13131443 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13131443 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024656 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024656 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024656 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024656 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024656 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024656 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13163.708245 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13163.708245 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13163.708245 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13163.708245 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.005811 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.245785 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2892019000 0.15% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 284 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 79630 # number of replacements +system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 4672446 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 4672446 # number of overall hits +system.cpu1.icache.overall_hits::total 4672446 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 80179 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 80179 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 80179 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 80179 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 80179 # number of overall misses +system.cpu1.icache.overall_misses::total 80179 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1082064992 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1082064992 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1082064992 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1082064992 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1082064992 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1082064992 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 4752625 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 4752625 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 4752625 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 4752625 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 4752625 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 4752625 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016870 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016870 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016870 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016870 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016870 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016870 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13495.615959 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13495.615959 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13495.615959 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13495.615959 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1466,112 +1464,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 323765 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 323765 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 323765 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 323765 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 323765 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 323765 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3614406523 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3614406523 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3614406523 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3614406523 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3614406523 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3614406523 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024656 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024656 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024656 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11163.672797 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11163.672797 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11163.672797 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 80179 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 80179 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 80179 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 80179 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 80179 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 80179 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 921458008 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 921458008 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 921458008 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 921458008 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 921458008 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 921458008 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016870 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016870 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016870 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11492.510608 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 161925 # number of replacements -system.cpu1.dcache.tagsinuse 486.809606 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3976206 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 162254 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.506058 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70872567000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 486.809606 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.950800 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.950800 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2251927 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2251927 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1621193 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1621193 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49026 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 49026 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 51669 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 51669 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3873120 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3873120 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3873120 # number of overall hits -system.cpu1.dcache.overall_hits::total 3873120 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118911 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118911 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 58093 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 58093 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9306 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9306 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6171 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6171 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 177004 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 177004 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 177004 # number of overall misses -system.cpu1.dcache.overall_misses::total 177004 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440878500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1440878500 # 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number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2370838 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1679286 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1679286 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58332 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 58332 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 57840 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 57840 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4050124 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4050124 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4050124 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4050124 # 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average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14026.397709 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14026.397709 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14026.397709 # average overall miss latency +system.cpu1.dcache.tags.replacements 40890 # number of replacements +system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 531046 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 9250 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 9250 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 9554 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 9554 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1448467 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1448467 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1448467 # number of overall hits +system.cpu1.dcache.overall_hits::total 1448467 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 31971 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 31971 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 13337 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 13337 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 850 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 850 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 495 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 495 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 45308 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 45308 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 45308 # number of overall misses +system.cpu1.dcache.overall_misses::total 45308 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 398942000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 398942000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 455916495 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 455916495 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 9380250 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 9380250 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3699073 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3699073 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 854858495 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 854858495 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 854858495 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 854858495 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 949392 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 949392 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 544383 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 544383 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 10100 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 10100 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 10049 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 10049 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1493775 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1493775 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1493775 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1493775 # 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average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18867.716408 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18867.716408 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18867.716408 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1580,66 +1578,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 111584 # number of writebacks -system.cpu1.dcache.writebacks::total 111584 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118911 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118911 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58093 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 58093 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9306 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9306 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6171 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6171 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 177004 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 177004 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 177004 # 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number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 722866000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 722866000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 741634000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 741634000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050156 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050156 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034594 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034594 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159535 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159535 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106691 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106691 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043703 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043703 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10117.281000 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10117.281000 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15934.174513 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15934.174513 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7070.545884 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7070.545884 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5275.887214 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5275.887214 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 527878500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 527878500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 546646500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 546646500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033675 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033675 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024499 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.024499 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.084158 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.084158 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.049259 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030331 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030331 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10475.649808 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10475.649808 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32026.205668 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32026.205668 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.647059 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9032.647059 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.579798 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5472.579798 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index e58c25cf4..fef6394c6 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.918467 # Number of seconds simulated -sim_ticks 1918467182000 # Number of ticks simulated -final_tick 1918467182000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.918473 # Number of seconds simulated +sim_ticks 1918473094000 # Number of ticks simulated +final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 829809 # Simulator instruction rate (inst/s) -host_op_rate 829809 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28329510825 # Simulator tick rate (ticks/s) -host_mem_usage 306208 # Number of bytes of host memory used -host_seconds 67.72 # Real time elapsed on the host -sim_insts 56194431 # Number of instructions simulated -sim_ops 56194431 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24859200 # Number of bytes read from this memory +host_inst_rate 813863 # Simulator instruction rate (inst/s) +host_op_rate 813863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27788392408 # Simulator tick rate (ticks/s) +host_mem_usage 306196 # Number of bytes of host memory used +host_seconds 69.04 # Real time elapsed on the host +sim_insts 56188014 # Number of instructions simulated +sim_ops 56188014 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28362304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404544 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404544 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388425 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28350528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7389888 # Number of bytes written to this memory +system.physmem.bytes_written::total 7389888 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443161 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115696 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115696 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12957845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1382537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14783836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3859615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3859615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3859615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12957845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1382537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18643451 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443161 # Total number of read requests seen -system.physmem.writeReqs 115696 # Total number of write requests seen -system.physmem.cpureqs 558987 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28362304 # Total number of bytes read from memory -system.physmem.bytesWritten 7404544 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28362304 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7404544 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 54 # Number of read reqs serviced by write Q +system.physmem.num_reads::total 442977 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115467 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115467 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12951700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1382533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14777652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3851963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3851963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3851963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 442977 # Total number of read requests seen +system.physmem.writeReqs 115467 # Total number of write requests seen +system.physmem.cpureqs 558574 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28350528 # Total number of bytes read from memory +system.physmem.bytesWritten 7389888 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27850 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28128 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28032 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 26738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 26867 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27091 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27474 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28095 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7621 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7634 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7863 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7544 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6982 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6321 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6315 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7316 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6513 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7108 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6910 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7064 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7822 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7859 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7707 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 26911 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 26768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27713 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27329 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28072 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28025 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28266 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7594 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7833 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7543 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7011 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6467 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7221 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6661 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7097 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6780 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7013 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7721 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7774 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7822 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1918455311000 # Total gap between requests +system.physmem.totGap 1918461222000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 443161 # Categorize read packet sizes +system.physmem.readPktSize::6 442977 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 115696 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 402425 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115467 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 402244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -128,236 +128,237 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 957.575108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.677714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2441.521254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13136 35.17% 35.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5703 15.27% 50.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3412 9.14% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2227 5.96% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1623 4.35% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1358 3.64% 73.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 966 2.59% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 781 2.09% 78.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 632 1.69% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 563 1.51% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 543 1.45% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 430 1.15% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 310 0.83% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 236 0.63% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 166 0.44% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 218 0.58% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 124 0.33% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 90 0.24% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 81 0.22% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 99 0.27% 87.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 87 0.23% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 95 0.25% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1075 2.88% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 150 0.40% 91.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 90 0.24% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 48 0.13% 91.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 42 0.11% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 35 0.09% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 29 0.08% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 22 0.06% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 18 0.05% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 29 0.08% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 17 0.05% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 5 0.01% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 12 0.03% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 7 0.02% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 8 0.02% 92.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 4 0.01% 92.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 6 0.02% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 3 0.01% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 5 0.01% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 4 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 4 0.01% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 6 0.02% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 4 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 5 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.00% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 2 0.01% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 3 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 3 0.01% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 3 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 2 0.01% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 2 0.01% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.01% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 2 0.01% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 2 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 2 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 4 0.01% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2437 6.53% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37132 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 962.378541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.718891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2449.750918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 13161 35.44% 35.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5591 15.06% 50.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3357 9.04% 59.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2263 6.09% 65.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1589 4.28% 69.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1303 3.51% 73.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 971 2.61% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 731 1.97% 78.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 647 1.74% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 569 1.53% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 543 1.46% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 425 1.14% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 308 0.83% 84.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 237 0.64% 85.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 163 0.44% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 235 0.63% 86.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 101 0.27% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 93 0.25% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 98 0.26% 87.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 98 0.26% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 85 0.23% 87.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 107 0.29% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 1046 2.82% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 157 0.42% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 87 0.23% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 55 0.15% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 46 0.12% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 40 0.11% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 31 0.08% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 18 0.05% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 16 0.04% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 26 0.07% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 8 0.02% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 8 0.02% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 15 0.04% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 14 0.04% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 2 0.01% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 4 0.01% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 3 0.01% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 4 0.01% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 3 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 2 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 3 0.01% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 3 0.01% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2437 6.56% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 15 0.04% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 239 0.64% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 8 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 242 0.65% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 9 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 2 0.01% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 2 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 2 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37346 # Bytes accessed per row activation -system.physmem.totQLat 3689041500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11833576500 # Sum of mem lat for all requests -system.physmem.totBusLat 2215535000 # Total cycles spent in databus access -system.physmem.totBankLat 5929000000 # Total cycles spent in bank access -system.physmem.avgQLat 8325.40 # Average queueing delay per request -system.physmem.avgBankLat 13380.52 # Average bank access latency per request +system.physmem.bytesPerActivate::16832-16835 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 3 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17347 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37132 # Bytes accessed per row activation +system.physmem.totQLat 3659130000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11798708750 # Sum of mem lat for all requests +system.physmem.totBusLat 2214635000 # Total cycles spent in databus access +system.physmem.totBankLat 5924943750 # Total cycles spent in bank access +system.physmem.avgQLat 8261.25 # Average queueing delay per request +system.physmem.avgBankLat 13376.80 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26705.91 # Average memory access latency +system.physmem.avgMemAccLat 26638.04 # Average memory access latency system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.86 # Average consumed write bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.85 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.67 # Average write queue length over time -system.physmem.readRowHits 427971 # Number of row buffer hits during reads -system.physmem.writeRowHits 93480 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3432819.69 # Average gap between requests -system.membus.throughput 18685123 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292355 # Transaction distribution -system.membus.trans_dist::ReadResp 292355 # Transaction distribution +system.physmem.avgWrQLen 13.19 # Average write queue length over time +system.physmem.readRowHits 427838 # Number of row buffer hits during reads +system.physmem.writeRowHits 93417 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes +system.physmem.avgGap 3435369.03 # Average gap between requests +system.membus.throughput 18671288 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292313 # Transaction distribution +system.membus.trans_dist::ReadResp 292313 # Transaction distribution system.membus.trans_dist::WriteReq 9649 # Transaction distribution system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 115696 # Transaction distribution +system.membus.trans_dist::Writeback 115467 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158289 # Transaction distribution -system.membus.trans_dist::ReadExResp 158289 # Transaction distribution +system.membus.trans_dist::ReadExReq 158147 # Transaction distribution +system.membus.trans_dist::ReadExResp 158147 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878153 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911311 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877556 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1002833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035991 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1002236 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457728 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30502284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 35766848 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35811404 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35811404 # Total data (bytes) +system.membus.tot_pkt_size::system.physmem.port 35740416 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35784972 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32374500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 32373000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1489970000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1487941500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3747469854 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3745756604 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376209000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.345466 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1752554384000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.345466 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084092 # Average percentage of cache occupancy +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -366,14 +367,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21342883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21342883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10435666030 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10435666030 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10457008913 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10457008913 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10457008913 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10457008913 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21343633 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21343633 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10434225282 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10434225282 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10455568915 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10455568915 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10455568915 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10455568915 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -390,19 +391,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123369.265896 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251147.141654 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251147.141654 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250617.349623 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250617.349623 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250617.349623 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250617.349623 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 271244 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123373.601156 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123373.601156 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251112.468281 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 251112.468281 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 250582.837987 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 250582.837987 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 272640 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27003 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27184 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.044958 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.029429 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -418,12 +419,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8274278780 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8274278780 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8286624913 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8286624913 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8286624913 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8286624913 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8272160782 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8272160782 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8284506915 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8284506915 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8284506915 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8284506915 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -434,12 +435,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199130.698402 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199130.698402 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198600.956573 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198600.956573 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198600.956573 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198600.956573 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199079.726174 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199079.726174 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -457,22 +458,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066498 # DTB read hits +system.cpu.dtb.read_hits 9065600 # DTB read hits system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6357377 # DTB write hits +system.cpu.dtb.write_hits 6356756 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15423875 # DTB hits +system.cpu.dtb.data_hits 15422356 # DTB hits system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020784 # DTB accesses -system.cpu.itb.fetch_hits 4974559 # ITB hits +system.cpu.itb.fetch_hits 4974352 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979569 # ITB accesses +system.cpu.itb.fetch_accesses 4979362 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -485,51 +486,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3836934364 # number of cpu cycles simulated +system.cpu.numCycles 3836946188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56194431 # Number of instructions committed -system.cpu.committedOps 56194431 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52065988 # Number of integer alu accesses +system.cpu.committedInsts 56188014 # Number of instructions committed +system.cpu.committedOps 56188014 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52059797 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses -system.cpu.num_func_calls 1483664 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469615 # number of instructions that are conditional controls -system.cpu.num_int_insts 52065988 # number of integer instructions +system.cpu.num_func_calls 1483456 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468822 # number of instructions that are conditional controls +system.cpu.num_int_insts 52059797 # number of integer instructions system.cpu.num_fp_insts 324527 # number of float instructions -system.cpu.num_int_register_reads 71339773 # number of times the integer registers were read -system.cpu.num_int_register_writes 38529890 # number of times the integer registers were written +system.cpu.num_int_register_reads 71330046 # number of times the integer registers were read +system.cpu.num_int_register_writes 38525190 # number of times the integer registers were written system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written -system.cpu.num_mem_refs 15476497 # number of memory refs -system.cpu.num_load_insts 9103354 # Number of load instructions -system.cpu.num_store_insts 6373143 # Number of store instructions -system.cpu.num_idle_cycles 3587701469.998130 # Number of idle cycles -system.cpu.num_busy_cycles 249232894.001870 # Number of busy cycles -system.cpu.not_idle_fraction 0.064956 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.935044 # Percentage of idle cycles +system.cpu.num_mem_refs 15474978 # number of memory refs +system.cpu.num_load_insts 9102456 # Number of load instructions +system.cpu.num_store_insts 6372522 # Number of store instructions +system.cpu.num_idle_cycles 3586988416.498130 # Number of idle cycles +system.cpu.num_busy_cycles 249957771.501870 # Number of busy cycles +system.cpu.not_idle_fraction 0.065145 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934855 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212005 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74904 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211982 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74893 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106221 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183187 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73537 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106209 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183164 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73526 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73537 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149136 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857459158500 96.82% 96.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91312500 0.00% 96.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736664500 0.04% 96.86% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 60179312500 3.14% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1918466448000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73526 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149114 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857159489000 96.80% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91367000 0.00% 96.81% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 736929000 0.04% 96.85% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 60484575000 3.15% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1918472360000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692302 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814119 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692277 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814101 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -568,7 +569,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175968 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::swpipl 175945 91.21% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -577,20 +578,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192914 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches +system.cpu.kern.callpal::total 192891 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1911 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081584 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46102035000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5243076000 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1867121335000 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 46124802000 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5245072500 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1867102483500 97.32% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4179 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -623,7 +624,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1410587 # Throughput (bytes/s) +system.iobus.throughput 1410582 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51201 # Transaction distribution @@ -709,59 +710,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378256913 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 378268915 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 928573 # number of replacements -system.cpu.icache.tagsinuse 508.447268 # Cycle average of tags in use -system.cpu.icache.total_refs 55277021 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929084 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.496258 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 38501717000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.447268 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993061 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993061 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55277021 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277021 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277021 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277021 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277021 # number of overall hits -system.cpu.icache.overall_hits::total 55277021 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929244 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929244 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929244 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929244 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929244 # number of overall misses -system.cpu.icache.overall_misses::total 929244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12990910500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12990910500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12990910500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12990910500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12990910500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12990910500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56206265 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56206265 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56206265 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56206265 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56206265 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56206265 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016533 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016533 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016533 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016533 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13980.085424 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13980.085424 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13980.085424 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13980.085424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13980.085424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13980.085424 # average overall miss latency +system.cpu.icache.tags.replacements 928665 # number of replacements +system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55270512 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55270512 # number of overall hits +system.cpu.icache.overall_hits::total 55270512 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929336 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929336 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929336 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929336 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929336 # number of overall misses +system.cpu.icache.overall_misses::total 929336 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13015346257 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13015346257 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13015346257 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13015346257 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13015346257 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13015346257 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56199848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56199848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56199848 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56199848 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56199848 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56199848 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016536 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016536 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016536 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016536 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016536 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016536 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14004.995241 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14004.995241 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14004.995241 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14004.995241 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,126 +771,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929244 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929244 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929244 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929244 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929244 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929244 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11132422500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11132422500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11132422500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11132422500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11132422500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11132422500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016533 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016533 # 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number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229410500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38847523639 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38847523639 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38847523639 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38847523639 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8884735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8884735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157181 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157181 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200257 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200257 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199236 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199236 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15041916 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15041916 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15041916 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15041916 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120394 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120394 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049456 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049456 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085985 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085985 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091357 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091357 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091357 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091357 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26401.588396 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26401.588396 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34831.661959 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34831.661959 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13323.102387 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13323.102387 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28269.644572 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28269.644572 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1046,54 +1047,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835526 # number of writebacks -system.cpu.dcache.writebacks::total 835526 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069817 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069817 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304458 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304458 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17270 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17270 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374275 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374275 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374275 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374275 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25921356500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25921356500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9930655500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9930655500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195056000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195056000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35852012000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 35852012000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35852012000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 35852012000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.writebacks::writebacks 835407 # number of writebacks +system.cpu.dcache.writebacks::total 835407 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069668 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069668 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304510 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304510 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374178 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374178 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374178 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374178 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25967193744 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25967193744 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9940394617 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9940394617 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194939500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194939500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35907588361 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 35907588361 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35907588361 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 35907588361 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424233500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424233500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435454500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435454500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120399 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120399 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086234 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086234 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091354 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091354 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24229.710782 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24229.710782 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32617.489112 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32617.489112 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11294.499131 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11294.499131 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26087.946008 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26087.946008 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26087.946008 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26087.946008 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435453000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435453000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120394 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120394 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085985 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085985 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091357 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091357 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24275.937715 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24275.937715 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32643.902062 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32643.902062 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.185899 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.185899 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1101,31 +1102,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105322456 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2023434 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023417 # Transaction distribution +system.cpu.toL2Bus.throughput 105316327 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2023326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023309 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835407 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 345993 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304442 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858468 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651931 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 5510399 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59470336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142586060 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 202056396 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 202046348 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2426797500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858652 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651517 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 5510169 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59476224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142569036 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 202045260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1393866000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1397230757 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2099055000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194639139 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 57671b2bd..29541c768 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -233,29 +233,29 @@ system.realview.nvmem.bw_total::total 75 # To system.membus.throughput 64986577 # Throughput (bytes/s) system.membus.data_through_bus 59274047 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.replacements 70658 # number of replacements -system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use -system.l2c.total_refs 1623339 # Total number of references to valid blocks. -system.l2c.sampled_refs 135810 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.953015 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.786745 # Average percentage of cache occupancy +system.l2c.tags.replacements 70658 # number of replacements +system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use +system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits @@ -486,15 +486,15 @@ system.cpu0.not_idle_fraction 0.021750 # Pe system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed -system.cpu0.icache.replacements 428546 # number of replacements -system.cpu0.icache.tagsinuse 511.015216 # Cycle average of tags in use -system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 69.480385 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 428546 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits @@ -528,15 +528,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 323609 # number of replacements -system.cpu0.dcache.tagsinuse 494.763091 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12467604 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 323981 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.482516 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 323609 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits @@ -662,15 +662,15 @@ system.cpu1.not_idle_fraction 0.022362 # Pe system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed -system.cpu1.icache.replacements 433942 # number of replacements -system.cpu1.icache.tagsinuse 475.447912 # Cycle average of tags in use -system.cpu1.icache.total_refs 31979125 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 434454 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 73.607620 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 433942 # number of replacements +system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits @@ -704,15 +704,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 294289 # number of replacements -system.cpu1.dcache.tagsinuse 447.573682 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11707745 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 294801 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.714061 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 294289 # number of replacements +system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits @@ -772,12 +772,12 @@ system.cpu1.dcache.cache_copies 0 # nu system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks system.cpu1.dcache.writebacks::total 266849 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 979b75345..486d98045 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -284,15 +284,15 @@ system.cpu.not_idle_fraction 0.016889 # Pe system.cpu.idle_fraction 0.983111 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu.icache.replacements 850590 # number of replacements -system.cpu.icache.tagsinuse 511.678593 # Cycle average of tags in use -system.cpu.icache.total_refs 60583498 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 850590 # number of replacements +system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits @@ -326,23 +326,23 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 62243 # number of replacements -system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 62243 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits @@ -434,15 +434,15 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks system.cpu.l2cache.writebacks::total 57863 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 623337 # number of replacements -system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 623337 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits @@ -501,12 +501,12 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s) system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 7372967ce..7e08761d9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.194897 # Number of seconds simulated -sim_ticks 1194896580500 # Number of ticks simulated -final_tick 1194896580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.194911 # Number of seconds simulated +sim_ticks 1194911360500 # Number of ticks simulated +final_tick 1194911360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311660 # Simulator instruction rate (inst/s) -host_op_rate 397163 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6068013925 # Simulator tick rate (ticks/s) -host_mem_usage 403588 # Number of bytes of host memory used -host_seconds 196.92 # Real time elapsed on the host -sim_insts 61371297 # Number of instructions simulated -sim_ops 78208202 # Number of ops (including micro ops) simulated +host_inst_rate 773513 # Simulator instruction rate (inst/s) +host_op_rate 985724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15060857671 # Simulator tick rate (ticks/s) +host_mem_usage 403580 # Number of bytes of host memory used +host_seconds 79.34 # Real time elapsed on the host +sim_insts 61369589 # Number of instructions simulated +sim_ops 78206230 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463972 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6626100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 464036 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6626228 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 255836 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory -system.physmem.bytes_read::total 62155108 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463972 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 255836 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4136192 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2904304 # Number of bytes read from this memory +system.physmem.bytes_read::total 62155620 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 464036 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4136576 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7163536 # Number of bytes written to this memory +system.physmem.bytes_written::total 7163920 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103607 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4079 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654628 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64628 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45406 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654636 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64634 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821464 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43438497 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821470 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43437960 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 388295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5545333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 388343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5545372 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2430537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52017144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 388295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214107 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3461548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2533528 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2430560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52016930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 388343 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3461827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2533497 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5995110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3461548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43438497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 5995357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3461827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43437960 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 388295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8078862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 388343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8078869 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2430570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58012254 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654628 # Total number of read requests seen -system.physmem.writeReqs 821464 # Total number of write requests seen +system.physmem.bw_total::cpu1.inst 214319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2430594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58012286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654636 # Total number of read requests seen +system.physmem.writeReqs 821470 # Total number of write requests seen system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425896192 # Total number of bytes read from memory -system.physmem.bytesWritten 52573696 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62155108 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7163536 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 139 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 10646 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415731 # Track reads on a per bank basis +system.physmem.bytesRead 425896704 # Total number of bytes read from memory +system.physmem.bytesWritten 52574080 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62155620 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7163920 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 10632 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 414961 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415301 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 416081 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415729 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51325 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51467 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis @@ -106,41 +106,41 @@ system.physmem.perBankWrReqs::11 51082 # Tr system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51694 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51696 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1194892168500 # Total gap between requests +system.physmem.totGap 1194906959500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159739 # Categorize read packet sizes +system.physmem.readPktSize::6 159747 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64628 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 581008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 419779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 439715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1589810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1189300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1185139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1157962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 10446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 15424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 15138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 4570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64634 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 581277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 421174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 435266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1590102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1186915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1183214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1164468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 15751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 21053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 15489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 77 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -156,10 +156,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 35716 # What write queue length does an incoming req see @@ -175,304 +175,302 @@ system.physmem.wrQLenPdf::15 35716 # Wh system.physmem.wrQLenPdf::16 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 13824.665723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 735.190153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 27804.066503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 7914 22.87% 22.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 4043 11.68% 34.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2692 7.78% 42.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1927 5.57% 47.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1400 4.05% 51.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1123 3.24% 55.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 878 2.54% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 878 2.54% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 638 1.84% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 541 1.56% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 480 1.39% 65.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 476 1.38% 66.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 262 0.76% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 253 0.73% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 191 0.55% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 292 0.84% 69.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 145 0.42% 69.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 146 0.42% 70.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 123 0.36% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 107 0.31% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 79 0.23% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 170 0.49% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 246 0.71% 74.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 151 0.44% 75.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 129 0.37% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 98 0.28% 76.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 72 0.21% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 51 0.15% 76.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 51 0.15% 76.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 71 0.21% 76.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 44 0.13% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 29 0.08% 77.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 19 0.05% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 34668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 13801.223030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 734.240341 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 27780.651463 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 7945 22.92% 22.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 4005 11.55% 34.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2676 7.72% 42.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1963 5.66% 47.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1415 4.08% 51.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1138 3.28% 55.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 895 2.58% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 859 2.48% 60.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 666 1.92% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 565 1.63% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 463 1.34% 65.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 439 1.27% 66.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 280 0.81% 67.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 254 0.73% 67.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 189 0.55% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 312 0.90% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 134 0.39% 69.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 136 0.39% 70.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 130 0.37% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 99 0.29% 70.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 89 0.26% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 164 0.47% 71.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 269 0.78% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 135 0.39% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 116 0.33% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 100 0.29% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 85 0.25% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 50 0.14% 76.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 50 0.14% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 59 0.17% 77.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 33 0.10% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 32 0.09% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 20 0.06% 77.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2367 23 0.07% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 27 0.08% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 13 0.04% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 9 0.03% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 14 0.04% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 11 0.03% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 12 0.03% 77.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 14 0.04% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 6 0.02% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 15 0.04% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 4 0.01% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 7 0.02% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 4 0.01% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 14 0.04% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 11 0.03% 77.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 7 0.02% 77.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 7 0.02% 77.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 11 0.03% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 11 0.03% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 23 0.07% 77.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 11 0.03% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 15 0.04% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 7 0.02% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 13 0.04% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 8 0.02% 77.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 13 0.04% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 9 0.03% 77.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 14 0.04% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 9 0.03% 77.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 16 0.05% 77.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 6 0.02% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 9 0.03% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 7 0.02% 77.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 9 0.03% 77.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 6 0.02% 77.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 6 0.02% 77.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3711 8 0.02% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 5 0.01% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 12 0.03% 78.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 8 0.02% 78.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 41 0.12% 78.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 78.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 4 0.01% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 4 0.01% 78.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 5 0.01% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 4 0.01% 78.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 78.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 9 0.03% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 1 0.00% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 5 0.01% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 3 0.01% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 10 0.03% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 3 0.01% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 2 0.01% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 5 0.01% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 2 0.01% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 3 0.01% 78.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 6 0.02% 78.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 2 0.01% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 3 0.01% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 5 0.01% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 4 0.01% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 3 0.01% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 3 0.01% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 170 0.49% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 3 0.01% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 1 0.00% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 4 0.01% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 4 0.01% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 2 0.01% 79.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 5 0.01% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 3 0.01% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 9 0.03% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 8 0.02% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 6 0.02% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 7 0.02% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 9 0.03% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 45 0.13% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 6 0.02% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 9 0.03% 78.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 2 0.01% 78.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 4 0.01% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 6 0.02% 78.35% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 2 0.01% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 1 0.00% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 1 0.00% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 6 0.02% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5823 1 0.00% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 1 0.00% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 6 0.02% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 6 0.02% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 180 0.52% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 1 0.00% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 4 0.01% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 1 0.00% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 5 0.01% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 1 0.00% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 3 0.01% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 2 0.01% 79.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6847 21 0.06% 79.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 2 0.01% 79.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6975 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 3 0.01% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7359 2 0.01% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 3 0.01% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 4 0.01% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 2 0.01% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 2 0.01% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 6 0.02% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 1 0.00% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 3 0.01% 79.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 4 0.01% 79.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 5 0.01% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 2 0.01% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 2 0.01% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 4 0.01% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 318 0.92% 80.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 1 0.00% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 2 0.01% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 4 0.01% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 2 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 2 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 17 0.05% 80.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10815 1 0.00% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11071 2 0.01% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11263 1 0.00% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 1 0.00% 79.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 3 0.01% 79.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 6 0.02% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 6 0.02% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 5 0.01% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 319 0.92% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 2 0.01% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 1 0.00% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 2 0.01% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9535 1 0.00% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10047 2 0.01% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 18 0.05% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::11264-11327 2 0.01% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 2 0.01% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11583 1 0.00% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11839 1 0.00% 80.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::12032-12095 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12799 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13631 2 0.01% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 2 0.01% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15935 1 0.00% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16767 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17343 1 0.00% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 2 0.01% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17791 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17919 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 2 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 1 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22591 3 0.01% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 2 0.01% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 3 0.01% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23871 1 0.00% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24191 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 2 0.01% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25279 1 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25919 2 0.01% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 3 0.01% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 1 0.00% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27903 1 0.00% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27967 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-28031 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 2 0.01% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 2 0.01% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 1 0.00% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 4 0.01% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 5 0.01% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31103 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31423 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31743 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 2 0.01% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 6 0.02% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 1 0.00% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33535 5 0.01% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 49 0.14% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33663 2 0.01% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35135 1 0.00% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38079 1 0.00% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39487 1 0.00% 80.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-41023 1 0.00% 80.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 2 0.01% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42175 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43327 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46911 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48447 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48576-48639 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53311 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53504-53567 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53760-53823 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54016-54079 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54335 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54528-54591 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55744-55807 1 0.00% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55808-55871 2 0.01% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 3 0.01% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56576-56639 1 0.00% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58880-58943 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59520-59583 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60479 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60608-60671 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62527 1 0.00% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 1 0.00% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 7 0.02% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 6201 17.92% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65920-65983 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66304-66367 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74240-74303 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::76480-76543 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::76864-76927 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::84416-84479 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::86848-86911 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::87040-87103 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::87424-87487 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97024-97087 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97472-97535 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97600-97663 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12607 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12863 2 0.01% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12991 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 3 0.01% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14847 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15167 2 0.01% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 3 0.01% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16703 2 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16895 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16959 2 0.01% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 2 0.01% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17727 1 0.00% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 2 0.01% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 1 0.00% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18752-18815 1 0.00% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19391 1 0.00% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 4 0.01% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 1 0.00% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20287 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21055 2 0.01% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22079 2 0.01% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22335 2 0.01% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22591 1 0.00% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 4 0.01% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24383 2 0.01% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 4 0.01% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25407 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25919 1 0.00% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26175 2 0.01% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26431 3 0.01% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 2 0.01% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29375 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 3 0.01% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 2 0.01% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30463 1 0.00% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 3 0.01% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 6 0.02% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31295 2 0.01% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31551 3 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31935 1 0.00% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32575 1 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 16 0.05% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33088-33151 1 0.00% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33215 2 0.01% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 36 0.10% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34367 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35647 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38207 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39551 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41279 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41407 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43584-43647 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44095 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44607 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45119 1 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45887 1 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48703 2 0.01% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 1 0.00% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50495 2 0.01% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51583 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52287 4 0.01% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52800-52863 1 0.00% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 2 0.01% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56064-56127 1 0.00% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 2 0.01% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61696-61759 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62080-62143 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62208-62271 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62976-63039 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 2 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64575 2 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64832-64895 1 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 6 0.02% 81.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 6196 17.87% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::72768-72831 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73983 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::75008-75071 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::82944-83007 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::84480-84543 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::85376-85439 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::85568-85631 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::94656-94719 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::95552-95615 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::98944-99007 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::109120-109183 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109696-109759 1 0.00% 98.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::110080-110143 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::111168-111231 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::114496-114559 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120896-120959 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121152-121215 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121728-121791 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::122112-122175 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::117440-117503 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::117952-118015 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120256-120319 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120640-120703 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121152-121215 1 0.00% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::131072-131135 336 0.97% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196160-196223 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34609 # Bytes accessed per row activation -system.physmem.totQLat 134116991750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 175932036750 # Sum of mem lat for all requests -system.physmem.totBusLat 33272445000 # Total cycles spent in databus access -system.physmem.totBankLat 8542600000 # Total cycles spent in bank access -system.physmem.avgQLat 20154.36 # Average queueing delay per request -system.physmem.avgBankLat 1283.73 # Average bank access latency per request +system.physmem.bytesPerActivate::total 34668 # Bytes accessed per row activation +system.physmem.totQLat 132807422500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 174630638750 # Sum of mem lat for all requests +system.physmem.totBusLat 33272490000 # Total cycles spent in databus access +system.physmem.totBankLat 8550726250 # Total cycles spent in bank access +system.physmem.avgQLat 19957.54 # Average queueing delay per request +system.physmem.avgBankLat 1284.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26438.10 # Average memory access latency +system.physmem.avgMemAccLat 26242.50 # Average memory access latency system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s @@ -480,12 +478,12 @@ system.physmem.avgConsumedWrBW 6.00 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 12.03 # Average write queue length over time -system.physmem.readRowHits 6636609 # Number of row buffer hits during reads -system.physmem.writeRowHits 804716 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.97 # Average write queue length over time +system.physmem.readRowHits 6636574 # Number of row buffer hits during reads +system.physmem.writeRowHits 804724 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes -system.physmem.avgGap 159828.45 # Average gap between requests +system.physmem.avgGap 159830.13 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -504,298 +502,298 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 60028731 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703147 # Transaction distribution -system.membus.trans_dist::ReadResp 7703147 # Transaction distribution +system.membus.throughput 60028739 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703151 # Transaction distribution +system.membus.trans_dist::ReadResp 7703151 # Transaction distribution system.membus.trans_dist::WriteReq 767201 # Transaction distribution system.membus.trans_dist::WriteResp 767201 # Transaction distribution -system.membus.trans_dist::Writeback 64628 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27727 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16403 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10646 # Transaction distribution -system.membus.trans_dist::ReadExReq 137752 # Transaction distribution -system.membus.trans_dist::ReadExResp 137298 # Transaction distribution +system.membus.trans_dist::Writeback 64634 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27614 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16407 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10632 # Transaction distribution +system.membus.trans_dist::ReadExReq 137758 # Transaction distribution +system.membus.trans_dist::ReadExResp 137302 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966658 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966559 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4359022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4358923 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 14942786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 14942687 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17335051 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17415028 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19823614 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19824510 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 69318644 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 69319540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71728126 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71728126 # Total data (bytes) +system.membus.tot_pkt_size::total 71729022 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71729022 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224802500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1208299500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9206920000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9149149500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) -system.membus.reqLayer3.occupancy 7965000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 7960500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 5076821641 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5034294617 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14663419999 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14663453747 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.replacements 69621 # number of replacements -system.l2c.tagsinuse 53152.412760 # Cycle average of tags in use -system.l2c.total_refs 1651309 # Total number of references to valid blocks. -system.l2c.sampled_refs 134782 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.251703 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40039.064508 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 2.667880 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001518 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4643.192238 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5788.281913 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1923.389950 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 755.813095 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.610948 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.070849 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.088322 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.029349 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011533 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.811041 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1439 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 483114 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 241880 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1868 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 372301 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 110577 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1219485 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 576235 # number of Writeback hits -system.l2c.Writeback_hits::total 576235 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1306 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 431 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits +system.l2c.tags.replacements 69629 # number of replacements +system.l2c.tags.tagsinuse 53155.534639 # Cycle average of tags in use +system.l2c.tags.total_refs 1651678 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134776 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.254986 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 40041.185718 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667860 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4638.655043 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5789.348152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1927.060090 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 756.614595 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.610980 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070780 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.088338 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011545 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.811089 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4625 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1507 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 482925 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 242050 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3554 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1806 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 372304 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 110721 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1219492 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 576641 # number of Writeback hits +system.l2c.Writeback_hits::total 576641 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1408 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 418 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1826 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 99 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65556 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 45402 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110958 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1439 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 483114 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 307436 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1868 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 372301 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155979 # number of demand (read+write) hits -system.l2c.demand_hits::total 1330443 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1439 # number of overall hits -system.l2c.overall_hits::cpu0.inst 483114 # number of overall hits -system.l2c.overall_hits::cpu0.data 307436 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1868 # number of overall hits -system.l2c.overall_hits::cpu1.inst 372301 # number of overall hits -system.l2c.overall_hits::cpu1.data 155979 # number of overall hits -system.l2c.overall_hits::total 1330443 # number of overall hits +system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65574 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 45429 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 111003 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4625 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1507 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 482925 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 307624 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 3554 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1806 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 372304 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 156150 # number of demand (read+write) hits +system.l2c.demand_hits::total 1330495 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4625 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1507 # number of overall hits +system.l2c.overall_hits::cpu0.inst 482925 # number of overall hits +system.l2c.overall_hits::cpu0.data 307624 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 3554 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1806 # number of overall hits +system.l2c.overall_hits::cpu1.inst 372304 # number of overall hits +system.l2c.overall_hits::cpu1.data 156150 # number of overall hits +system.l2c.overall_hits::total 1330495 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9717 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6837 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9715 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3992 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22442 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 3986 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3365 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 7351 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 384 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 475 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 859 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 95133 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 44601 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139734 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 3996 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1891 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22446 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3988 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3371 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 7359 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 387 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 473 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 860 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 95120 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12647628243 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4849500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070714500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167063392493 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272290763 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486202500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16758493263 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 340200250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919919006 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4849500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556917000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183821885756 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038588 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016792 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018073 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.739066 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.889681 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.801198 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.600932 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.831283 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.708986 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.591932 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495368 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.557260 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.254171 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.229406 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108639 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.254171 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.229406 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108639 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58235.386333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58485.331858 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68885.978836 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59348.458135 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.778726 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.009510 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.497347 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.825521 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.892632 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.263097 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52609.097926 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50644.309836 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 51981.966994 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67742.860920 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59174.159011 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.019809 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.545535 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.964126 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10007.457364 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.114165 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10005.068605 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52642.691369 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50700.972149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 52022.922779 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53184.125550 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53184.125550 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -977,56 +975,56 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118409228 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2504917 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2504917 # Transaction distribution +system.toL2Bus.throughput 118431561 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2504925 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2504925 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576235 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 27028 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16759 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576641 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 27027 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16760 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993919 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951089 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5837 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 14921 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753559 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2879854 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6195 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11995 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7617369 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31383352 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53719796 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 5764 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083148 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27940806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7476 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 15128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 137173582 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137173582 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4313200 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4765991701 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadExReq 262499 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262499 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951402 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5905 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 15026 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753554 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2880607 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6133 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11768 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7617950 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31371320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53730420 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 6036 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083596 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27977862 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7228 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 14216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 137209194 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137209194 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4306024 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4767819743 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2214801410 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2217282985 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2446229482 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2471819696 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10393499 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 10398000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1696938433 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1697865710 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2203617971 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 2215426419 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 4326998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 8214499 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45438572 # Throughput (bytes/s) +system.iobus.throughput 45438010 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution @@ -1184,13 +1182,13 @@ system.iobus.reqLayer25.occupancy 6488064000 # La system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 12976128000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 17765827253 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9653493 # DTB read hits -system.cpu0.dtb.read_misses 3738 # DTB read misses -system.cpu0.dtb.write_hits 7597651 # DTB write hits +system.cpu0.dtb.read_hits 9651794 # DTB read hits +system.cpu0.dtb.read_misses 3741 # DTB read misses +system.cpu0.dtb.write_hits 7596285 # DTB write hits system.cpu0.dtb.write_misses 1585 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -1198,16 +1196,16 @@ system.cpu0.dtb.flush_tlb_mva_asid 1439 # Nu system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9657231 # DTB read accesses -system.cpu0.dtb.write_accesses 7599236 # DTB write accesses +system.cpu0.dtb.read_accesses 9655535 # DTB read accesses +system.cpu0.dtb.write_accesses 7597870 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17251144 # DTB hits -system.cpu0.dtb.misses 5323 # DTB misses -system.cpu0.dtb.accesses 17256467 # DTB accesses -system.cpu0.itb.inst_hits 43299111 # ITB inst hits +system.cpu0.dtb.hits 17248079 # DTB hits +system.cpu0.dtb.misses 5326 # DTB misses +system.cpu0.dtb.accesses 17253405 # DTB accesses +system.cpu0.itb.inst_hits 43295611 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1224,79 +1222,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43301316 # ITB inst accesses -system.cpu0.itb.hits 43299111 # DTB hits +system.cpu0.itb.inst_accesses 43297816 # ITB inst accesses +system.cpu0.itb.hits 43295611 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43301316 # DTB accesses -system.cpu0.numCycles 2389793161 # number of cpu cycles simulated +system.cpu0.itb.accesses 43297816 # DTB accesses +system.cpu0.numCycles 2389822721 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42572187 # Number of instructions committed -system.cpu0.committedOps 53304847 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48061724 # Number of integer alu accesses +system.cpu0.committedInsts 42568710 # Number of instructions committed +system.cpu0.committedOps 53298123 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48055390 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403541 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582883 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48061724 # number of integer instructions +system.cpu0.num_func_calls 1403445 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582451 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48055390 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272457591 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52272439 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272420788 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52266741 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 18020656 # number of memory refs -system.cpu0.num_load_insts 10037354 # Number of load instructions -system.cpu0.num_store_insts 7983302 # Number of store instructions -system.cpu0.num_idle_cycles 2150335736.878201 # Number of idle cycles -system.cpu0.num_busy_cycles 239457424.121800 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100200 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899800 # Percentage of idle cycles +system.cpu0.num_mem_refs 18017454 # number of memory refs +system.cpu0.num_load_insts 10035613 # Number of load instructions +system.cpu0.num_store_insts 7981841 # Number of store instructions +system.cpu0.num_idle_cycles 2150296210.870201 # Number of idle cycles +system.cpu0.num_busy_cycles 239526510.129800 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100228 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899772 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51313 # number of quiesce instructions executed -system.cpu0.icache.replacements 490180 # number of replacements -system.cpu0.icache.tagsinuse 509.396236 # Cycle average of tags in use -system.cpu0.icache.total_refs 42808401 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 490692 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 87.240878 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 76020026000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.396236 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994915 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994915 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 42808401 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42808401 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 42808401 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42808401 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 42808401 # number of overall hits -system.cpu0.icache.overall_hits::total 42808401 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490693 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490693 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490693 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 490693 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 490693 # number of overall misses -system.cpu0.icache.overall_misses::total 490693 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812744000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6812744000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6812744000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6812744000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6812744000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6812744000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 43299094 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43299094 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 43299094 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43299094 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 43299094 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43299094 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011333 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011333 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011333 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011333 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011333 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011333 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13883.923349 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13883.923349 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13883.923349 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13883.923349 # average overall miss latency +system.cpu0.kern.inst.quiesce 51308 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 490004 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.392438 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 42805077 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490516 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.265404 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76030513250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.392438 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994907 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994907 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42805077 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42805077 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42805077 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42805077 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42805077 # number of overall hits +system.cpu0.icache.overall_hits::total 42805077 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490517 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490517 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490517 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490517 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490517 # number of overall misses +system.cpu0.icache.overall_misses::total 490517 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812396235 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6812396235 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6812396235 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6812396235 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6812396235 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6812396235 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43295594 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43295594 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43295594 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43295594 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43295594 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43295594 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011329 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011329 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011329 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011329 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011329 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011329 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13888.195995 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13888.195995 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13888.195995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13888.195995 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1305,120 +1303,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490693 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 490693 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 490693 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 490693 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 490693 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 490693 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5831313090 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5831313090 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5831313090 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5831313090 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5831313090 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5831313090 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 430167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 430167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 430167000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 430167000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011333 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011333 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011333 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11883.831826 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490517 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490517 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490517 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490517 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490517 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490517 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5828002765 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5828002765 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5828002765 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5828002765 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5828002765 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5828002765 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 431776750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 431776750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 431776750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 431776750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011329 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011329 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011329 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11881.347160 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 406656 # number of replacements -system.cpu0.dcache.tagsinuse 471.250698 # Cycle average of tags in use -system.cpu0.dcache.total_refs 15968393 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 407168 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 39.218192 # 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Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 39.214809 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 659626250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.882465 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919692 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.919692 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9135819 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9135819 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6493762 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6493762 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156506 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156506 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158999 # 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number of cycles access was blocked @@ -1427,66 +1425,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 376588 # number of writebacks -system.cpu0.dcache.writebacks::total 376588 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263671 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 263671 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176701 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176701 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9917 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9917 # 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average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12678.781546 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40511.307259 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40511.307259 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7995.613694 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7995.613694 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3465.332429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3465.332429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499888711 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10499888711 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499888711 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10499888711 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764207250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764207250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807935730 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807935730 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572142980 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572142980 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028061 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028061 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026482 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026482 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059606 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059606 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044304 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044304 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027406 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027406 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12700.742346 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12700.742346 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40475.797545 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40475.797545 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7922.782258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7922.782258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3498.455162 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3498.455162 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1496,26 +1494,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5706432 # DTB read hits -system.cpu1.dtb.read_misses 3576 # DTB read misses -system.cpu1.dtb.write_hits 3873109 # DTB write hits -system.cpu1.dtb.write_misses 645 # DTB write misses +system.cpu1.dtb.read_hits 5707792 # DTB read hits +system.cpu1.dtb.read_misses 3579 # DTB read misses +system.cpu1.dtb.write_hits 3874264 # DTB write hits +system.cpu1.dtb.write_misses 643 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5710008 # DTB read accesses -system.cpu1.dtb.write_accesses 3873754 # DTB write accesses +system.cpu1.dtb.read_accesses 5711371 # DTB read accesses +system.cpu1.dtb.write_accesses 3874907 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9579541 # DTB hits -system.cpu1.dtb.misses 4221 # DTB misses -system.cpu1.dtb.accesses 9583762 # DTB accesses -system.cpu1.itb.inst_hits 19379683 # ITB inst hits +system.cpu1.dtb.hits 9582056 # DTB hits +system.cpu1.dtb.misses 4222 # DTB misses +system.cpu1.dtb.accesses 9586278 # DTB accesses +system.cpu1.itb.inst_hits 19381456 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1532,79 +1530,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19381854 # ITB inst accesses -system.cpu1.itb.hits 19379683 # DTB hits +system.cpu1.itb.inst_accesses 19383627 # ITB inst accesses +system.cpu1.itb.hits 19381456 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19381854 # DTB accesses -system.cpu1.numCycles 2388360365 # number of cpu cycles simulated +system.cpu1.itb.accesses 19383627 # DTB accesses +system.cpu1.numCycles 2388389320 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18799110 # Number of instructions committed -system.cpu1.committedOps 24903355 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22267252 # Number of integer alu accesses +system.cpu1.committedInsts 18800879 # Number of instructions committed +system.cpu1.committedOps 24908107 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22271769 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796685 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514656 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22267252 # number of integer instructions +system.cpu1.num_func_calls 796713 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514831 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22271769 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130770555 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23319815 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130796956 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23323418 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10014978 # number of memory refs -system.cpu1.num_load_insts 5983060 # Number of load instructions -system.cpu1.num_store_insts 4031918 # Number of store instructions -system.cpu1.num_idle_cycles 1968746844.438183 # Number of idle cycles -system.cpu1.num_busy_cycles 419613520.561817 # Number of busy cycles -system.cpu1.not_idle_fraction 0.175691 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.824309 # Percentage of idle cycles +system.cpu1.num_mem_refs 10017504 # number of memory refs +system.cpu1.num_load_insts 5984439 # Number of load instructions +system.cpu1.num_store_insts 4033065 # Number of store instructions +system.cpu1.num_idle_cycles 1968748229.220572 # Number of idle cycles +system.cpu1.num_busy_cycles 419641090.779428 # Number of busy cycles +system.cpu1.not_idle_fraction 0.175700 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.824300 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39066 # number of quiesce instructions executed -system.cpu1.icache.replacements 376556 # number of replacements -system.cpu1.icache.tagsinuse 474.951242 # Cycle average of tags in use -system.cpu1.icache.total_refs 19002611 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 377068 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 50.395714 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 327008186500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 474.951242 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.927639 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.927639 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19002611 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19002611 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19002611 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19002611 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19002611 # number of overall hits -system.cpu1.icache.overall_hits::total 19002611 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377068 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377068 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377068 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377068 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377068 # number of overall misses -system.cpu1.icache.overall_misses::total 377068 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5155062500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5155062500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5155062500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5155062500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5155062500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5155062500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379679 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19379679 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19379679 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19379679 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19379679 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19379679 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019457 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019457 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019457 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019457 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019457 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019457 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.439899 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.439899 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13671.439899 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13671.439899 # average overall miss latency +system.cpu1.kern.inst.quiesce 39064 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 376544 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.938465 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19004396 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 377056 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 50.402052 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 327017678500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.938465 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927614 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927614 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19004396 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19004396 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19004396 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19004396 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19004396 # number of overall hits +system.cpu1.icache.overall_hits::total 19004396 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377056 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377056 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377056 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377056 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377056 # number of overall misses +system.cpu1.icache.overall_misses::total 377056 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154731460 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5154731460 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5154731460 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5154731460 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5154731460 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5154731460 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19381452 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19381452 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19381452 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19381452 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19381452 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19381452 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019454 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019454 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019454 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019454 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019454 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019454 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13670.997040 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13670.997040 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13670.997040 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13670.997040 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13670.997040 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13670.997040 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1613,120 +1611,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377068 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 377068 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 377068 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 377068 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 377068 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 377068 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4400893067 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4400893067 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4400893067 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4400893067 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4400893067 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4400893067 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6177000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6177000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6177000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6177000 # 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average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.351234 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377056 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 377056 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 377056 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 377056 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 377056 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 377056 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398633040 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398633040 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398633040 # 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mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019454 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019454 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019454 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11665.728804 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11665.728804 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11665.728804 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029683 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.029683 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12347.059834 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12347.059834 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32832.229522 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32832.229522 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7996.664956 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7996.664956 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5210.498296 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5210.498296 # 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average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21840.957120 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21840.957120 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1735,66 +1733,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 199647 # number of writebacks -system.cpu1.dcache.writebacks::total 199647 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133853 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133853 # 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number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30157000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30157000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246830 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246830 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246830 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246830 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384995764 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384995764 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3490409790 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3490409790 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30268527 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30268527 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4862569527 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4862569527 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4862569527 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4862569527 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387734500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387734500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531024500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531024500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029593 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029593 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029791 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029791 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117122 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117122 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112973 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112973 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029683 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.029683 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10346.996459 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10346.996459 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30832.185281 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30832.185281 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5996.562545 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5996.562545 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3211.266106 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3211.266106 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4875405554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4875405554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4875405554 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4875405554 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372273000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372273000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531015000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531015000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903288000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903288000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029606 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029606 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029806 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029806 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112962 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112962 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029697 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029697 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10339.570171 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10339.570171 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30921.693052 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30921.693052 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6011.287840 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6011.287840 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3223.142051 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3223.142051 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1802,12 +1800,12 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1816,10 +1814,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 626235127001 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 626235127001 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 626235127001 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 626235127001 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 624927975253 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 624927975253 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 624927975253 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 624927975253 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 934a4cb6c..955e513bb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.615622 # Number of seconds simulated -sim_ticks 2615622384000 # Number of ticks simulated -final_tick 2615622384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.615733 # Number of seconds simulated +sim_ticks 2615733285000 # Number of ticks simulated +final_tick 2615733285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264818 # Simulator instruction rate (inst/s) -host_op_rate 336993 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11506330329 # Simulator tick rate (ticks/s) -host_mem_usage 396436 # Number of bytes of host memory used -host_seconds 227.32 # Real time elapsed on the host -sim_insts 60198587 # Number of instructions simulated -sim_ops 76605405 # Number of ops (including micro ops) simulated +host_inst_rate 250012 # Simulator instruction rate (inst/s) +host_op_rate 318151 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10863402189 # Simulator tick rate (ticks/s) +host_mem_usage 396412 # Number of bytes of host memory used +host_seconds 240.78 # Real time elapsed on the host +sim_insts 60198861 # Number of instructions simulated +sim_ops 76605713 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory -system.physmem.bytes_read::total 132481840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3709760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory +system.physmem.bytes_read::total 132482416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6725832 # Number of bytes written to this memory +system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494761 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57965 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17216 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494770 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811983 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46904092 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46902103 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3476496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50650216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1418309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153099 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2571408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1418309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46904092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3476544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50648289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1418395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153050 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2571446 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1418395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46902103 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4629595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53221624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494761 # Total number of read requests seen -system.physmem.writeReqs 811983 # Total number of write requests seen -system.physmem.cpureqs 215166 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991664704 # Total number of bytes read from memory -system.physmem.bytesWritten 51966912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132481840 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6725832 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 301 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 974722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 968494 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 269471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4629594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53219735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494770 # Total number of read requests seen +system.physmem.writeReqs 811989 # Total number of write requests seen +system.physmem.cpureqs 215180 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991665280 # Total number of bytes read from memory +system.physmem.bytesWritten 51967296 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132482416 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 299 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 968107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 974725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 968490 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968523 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 968301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 967930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967683 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50853 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51127 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51430 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50878 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 967887 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967682 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49013 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50857 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51128 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51425 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50876 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 50871 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 50874 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50825 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 50676 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 50677 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2615618000000 # Total gap between requests +system.physmem.totGap 2615728912000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152685 # Categorize read packet sizes +system.physmem.readPktSize::6 152694 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57965 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1126555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 973164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1018253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3775658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2831038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2826406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2774250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 19136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 31670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 43534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 30921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 40 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57971 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1128832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 975833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1007328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3775576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2827750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2822812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2787859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 32464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 45819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 32079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -139,8 +139,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35301 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see @@ -153,17 +153,17 @@ system.physmem.wrQLenPdf::10 35304 # Wh system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,308 +171,327 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38567 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 27059.676926 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2495.376643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33105.439598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5489 14.23% 14.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3331 8.64% 22.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2176 5.64% 28.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1697 4.40% 32.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1162 3.01% 35.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1046 2.71% 38.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 828 2.15% 40.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 748 1.94% 42.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 582 1.51% 44.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 509 1.32% 45.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 411 1.07% 46.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 479 1.24% 47.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 285 0.74% 48.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 248 0.64% 49.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 187 0.48% 49.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 239 0.62% 50.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 141 0.37% 50.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 137 0.36% 51.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 106 0.27% 51.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 105 0.27% 51.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 92 0.24% 51.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 151 0.39% 52.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 970 2.52% 54.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 135 0.35% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 110 0.29% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 77 0.20% 56.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 66 0.17% 56.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 47 0.12% 56.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 64 0.17% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 37 0.10% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 25 0.06% 57.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 18 0.05% 57.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 25 0.06% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 26 0.07% 57.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 13 0.03% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 25 0.06% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 14 0.04% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 8 0.02% 57.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 18 0.05% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 9 0.02% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 17 0.04% 57.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 7 0.02% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 12 0.03% 57.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 12 0.03% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 3 0.01% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 9 0.02% 57.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 9 0.02% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 4 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 44 0.11% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 2 0.01% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 5 0.01% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 2 0.01% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 2 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 7 0.02% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 6 0.02% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 1 0.00% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 12 0.03% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 3 0.01% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 7 0.02% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 2 0.01% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 2 0.01% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 2 0.01% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 6 0.02% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 3 0.01% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 2 0.01% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 3 0.01% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 180 0.47% 58.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 1 0.00% 58.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 3 0.01% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 5 0.01% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 3 0.01% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 2 0.01% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 11 0.03% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 3 0.01% 59.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 4 0.01% 59.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 4 0.01% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 3 0.01% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 1 0.00% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 6 0.02% 59.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 4 0.01% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 5 0.01% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 3 0.01% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 2 0.01% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10815 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11263 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 2 0.01% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 2 0.01% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11647 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11839 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12351 3 0.01% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12607 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13631 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 2 0.01% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14655 2 0.01% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 3 0.01% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15743 1 0.00% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 2 0.01% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17983 1 0.00% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 2 0.01% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19071 1 0.00% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 3 0.01% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 2 0.01% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 2 0.01% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22591 4 0.01% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 3 0.01% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 5 0.01% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 2 0.01% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-25023 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25919 2 0.01% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26431 1 0.00% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 4 0.01% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 1 0.00% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28159 1 0.00% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 1 0.00% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 1 0.00% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29439 1 0.00% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 6 0.02% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 2 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 3 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 3 0.01% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 5 0.01% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 4 0.01% 60.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 56 0.15% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33663 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34111 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37439 1 0.00% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38975 1 0.00% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39999 2 0.01% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42303 1 0.00% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42559 2 0.01% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43583 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45119 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45631 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 2 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49727 2 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52480-52543 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52992-53055 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 3 0.01% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57088-57151 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60479 2 0.01% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61503 1 0.00% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 2 0.01% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63808-63871 1 0.00% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64575 1 0.00% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 14789 38.35% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-74047 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::83008-83071 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 38488 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 27115.229266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2500.122459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33119.773163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5498 14.28% 14.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3288 8.54% 22.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2221 5.77% 28.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1687 4.38% 32.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1187 3.08% 36.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1056 2.74% 38.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 814 2.11% 40.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 739 1.92% 42.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 550 1.43% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 512 1.33% 45.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 421 1.09% 46.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 397 1.03% 47.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 314 0.82% 48.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 250 0.65% 49.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 198 0.51% 49.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 236 0.61% 50.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 138 0.36% 51.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 98 0.25% 51.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 109 0.28% 51.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 78 0.20% 51.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 154 0.40% 52.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 969 2.52% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 195 0.51% 55.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 143 0.37% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 120 0.31% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 89 0.23% 56.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 73 0.19% 56.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 63 0.16% 56.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 55 0.14% 56.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 51 0.13% 56.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 29 0.08% 57.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 27 0.07% 57.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 16 0.04% 57.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 16 0.04% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 22 0.06% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 16 0.04% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 9 0.02% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 16 0.04% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 11 0.03% 57.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 9 0.02% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 4 0.01% 57.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 13 0.03% 57.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 13 0.03% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 10 0.03% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 5 0.01% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 10 0.03% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 3 0.01% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 7 0.02% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 40 0.10% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 6 0.02% 58.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 4 0.01% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 3 0.01% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 6 0.02% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 9 0.02% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 2 0.01% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 9 0.02% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 2 0.01% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 4 0.01% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 3 0.01% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 5 0.01% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 4 0.01% 58.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 4 0.01% 58.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 6 0.02% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 4 0.01% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 1 0.00% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 1 0.00% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 184 0.48% 58.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 2 0.01% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 2 0.01% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 3 0.01% 58.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 4 0.01% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 4 0.01% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 1 0.00% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 4 0.01% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 1 0.00% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8639 1 0.00% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 5 0.01% 59.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9919 1 0.00% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10175 2 0.01% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 20 0.05% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10687 1 0.00% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11071 1 0.00% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 1 0.00% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12351 2 0.01% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12607 1 0.00% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12735 1 0.00% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13759 1 0.00% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 2 0.01% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 3 0.01% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 4 0.01% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15743 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17087 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 3 0.01% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17983 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18111 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18367 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 3 0.01% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18751 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 2 0.01% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.02% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51519 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52736-52799 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55359 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 2 0.01% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64000-64063 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64768-64831 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 14794 38.44% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::76928-76991 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::81536-81599 1 0.00% 99.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::93120-93183 1 0.00% 99.06% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::106240-106303 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::106624-106687 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109440-109503 1 0.00% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::110912-110975 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::114240-114303 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::115328-115391 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::116992-117055 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120320-120383 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::111232-111295 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::114048-114111 1 0.00% 99.08% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::125696-125759 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128832-128895 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130496-130559 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130560-130623 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::161408-161471 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::190336-190399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::156992-157055 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::193280-193343 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196096-196159 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38567 # Bytes accessed per row activation -system.physmem.totQLat 306544443250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 400266823250 # Sum of mem lat for all requests -system.physmem.totBusLat 77472300000 # Total cycles spent in databus access -system.physmem.totBankLat 16250080000 # Total cycles spent in bank access -system.physmem.avgQLat 19784.13 # Average queueing delay per request -system.physmem.avgBankLat 1048.77 # Average bank access latency per request +system.physmem.bytesPerActivate::total 38488 # Bytes accessed per row activation +system.physmem.totQLat 303199099750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 396944112250 # Sum of mem lat for all requests +system.physmem.totBusLat 77472355000 # Total cycles spent in databus access +system.physmem.totBankLat 16272657500 # Total cycles spent in bank access +system.physmem.avgQLat 19568.21 # Average queueing delay per request +system.physmem.avgBankLat 1050.22 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25832.90 # Average memory access latency -system.physmem.avgRdBW 379.13 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25618.44 # Average memory access latency +system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.80 # Average write queue length over time -system.physmem.readRowHits 15469403 # Number of row buffer hits during reads -system.physmem.writeRowHits 798459 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.84 # Average write queue length over time +system.physmem.readRowHits 15469547 # Number of row buffer hits during reads +system.physmem.writeRowHits 798405 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes -system.physmem.avgGap 160401.00 # Average gap between requests +system.physmem.avgGap 160407.65 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -485,59 +504,59 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54138467 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546589 # Transaction distribution -system.membus.trans_dist::ReadResp 16546589 # Transaction distribution +system.membus.throughput 54136540 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546595 # Transaction distribution +system.membus.trans_dist::ReadResp 16546595 # Transaction distribution system.membus.trans_dist::WriteReq 763368 # Transaction distribution system.membus.trans_dist::WriteResp 763368 # Transaction distribution -system.membus.trans_dist::Writeback 57965 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution -system.membus.trans_dist::ReadExReq 132246 # Transaction distribution -system.membus.trans_dist::ReadExResp 132246 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57971 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution +system.membus.trans_dist::ReadExReq 132250 # Transaction distribution +system.membus.trans_dist::ReadExResp 132250 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893707 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893729 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280579 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32564555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32564577 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951403 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34951427 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16524280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525240 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18922393 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923357 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 139207672 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 139208632 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141605785 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141605785 # Total data (bytes) +system.membus.tot_pkt_size::total 141606749 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141606749 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206150500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206151500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17904777500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17903854000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4945376509 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4944443675 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34635651750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34633310000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -545,13 +564,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47817981 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution +system.iobus.throughput 47815955 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution system.iobus.trans_dist::WriteReq 8166 # Transaction distribution system.iobus.trans_dist::WriteResp 8166 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -573,11 +592,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -600,9 +619,9 @@ system.iobus.pkt_count::system.realview.aaci_fake.pio 16 system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -624,11 +643,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -651,11 +670,11 @@ system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073781 # Total data (bytes) +system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073785 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -701,32 +720,32 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30670848000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42022039000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996055 # DTB read hits -system.cpu.dtb.read_misses 7342 # DTB read misses -system.cpu.dtb.write_hits 11230429 # DTB write hits -system.cpu.dtb.write_misses 2216 # DTB write misses +system.cpu.dtb.read_hits 14996132 # DTB read hits +system.cpu.dtb.read_misses 7340 # DTB read misses +system.cpu.dtb.write_hits 11230462 # DTB write hits +system.cpu.dtb.write_misses 2218 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003397 # DTB read accesses -system.cpu.dtb.write_accesses 11232645 # DTB write accesses +system.cpu.dtb.read_accesses 15003472 # DTB read accesses +system.cpu.dtb.write_accesses 11232680 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226484 # DTB hits +system.cpu.dtb.hits 26226594 # DTB hits system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 26236042 # DTB accesses -system.cpu.itb.inst_hits 61492425 # ITB inst hits +system.cpu.dtb.accesses 26236152 # DTB accesses +system.cpu.itb.inst_hits 61492700 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -743,79 +762,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61496896 # ITB inst accesses -system.cpu.itb.hits 61492425 # DTB hits +system.cpu.itb.inst_accesses 61497171 # ITB inst accesses +system.cpu.itb.hits 61492700 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61496896 # DTB accesses -system.cpu.numCycles 5231244768 # number of cpu cycles simulated +system.cpu.itb.accesses 61497171 # DTB accesses +system.cpu.numCycles 5231466570 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60198587 # Number of instructions committed -system.cpu.committedOps 76605405 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872209 # Number of integer alu accesses +system.cpu.committedInsts 60198861 # Number of instructions committed +system.cpu.committedOps 76605713 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872503 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140451 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948368 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872209 # number of integer instructions +system.cpu.num_func_calls 2140458 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948408 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872503 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394776354 # number of times the integer registers were read -system.cpu.num_int_register_writes 74181797 # number of times the integer registers were written +system.cpu.num_int_register_reads 394778081 # number of times the integer registers were read +system.cpu.num_int_register_writes 74182147 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393915 # number of memory refs -system.cpu.num_load_insts 15660071 # Number of load instructions -system.cpu.num_store_insts 11733844 # Number of store instructions -system.cpu.num_idle_cycles 4582065338.612248 # Number of idle cycles -system.cpu.num_busy_cycles 649179429.387752 # Number of busy cycles -system.cpu.not_idle_fraction 0.124097 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875903 # Percentage of idle cycles +system.cpu.num_mem_refs 27394052 # number of memory refs +system.cpu.num_load_insts 15660178 # Number of load instructions +system.cpu.num_store_insts 11733874 # Number of store instructions +system.cpu.num_idle_cycles 4581968820.612248 # Number of idle cycles +system.cpu.num_busy_cycles 649497749.387752 # Number of busy cycles +system.cpu.not_idle_fraction 0.124152 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875848 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.replacements 856250 # number of replacements -system.cpu.icache.tagsinuse 510.885364 # Cycle average of tags in use -system.cpu.icache.total_refs 60635663 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856762 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.773054 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19768699000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.885364 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997823 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997823 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635663 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635663 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635663 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635663 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635663 # number of overall hits -system.cpu.icache.overall_hits::total 60635663 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856762 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856762 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856762 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856762 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856762 # number of overall misses -system.cpu.icache.overall_misses::total 856762 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11759087500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11759087500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11759087500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11759087500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11759087500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11759087500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61492425 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61492425 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61492425 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61492425 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61492425 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61492425 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702868810 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 339357750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183360141560 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183699499310 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025890 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016388 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991068 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991068 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541206 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541206 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025888 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016389 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541360 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541360 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229141 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103252 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103253 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58635.004576 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58131.501052 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.693241 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.693241 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51839.265751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51839.265751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57761.910377 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58551.336790 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58142.719135 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57761.910377 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52250.209720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52629.135548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57655.392018 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52304.247311 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52672.666029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57761.910377 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52250.209720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52629.135548 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1095,79 +1114,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 626656 # number of replacements -system.cpu.dcache.tagsinuse 511.879114 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655617 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.718150 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 650249000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.879114 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999764 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999764 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195840 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195840 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972724 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972724 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236345 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236345 # 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number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 159892750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16010772015 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16010772015 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16010772015 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16010772015 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564259 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564259 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223032 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223032 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23787291 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787291 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787291 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787291 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027166 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027166 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024477 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024477 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14618.044550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14618.044550 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42458.579339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42458.579339 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13903.717391 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13903.717391 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25877.542601 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25877.542601 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1176,54 +1195,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595512 # number of writebacks -system.cpu.dcache.writebacks::total 595512 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368347 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368347 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250279 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250279 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11453 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618626 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618626 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618626 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618626 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4641851500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4641851500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031352500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031352500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135954000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135954000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14673204000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14673204000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14673204000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14673204000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050723500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050723500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234076500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234076500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284800000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284800000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027156 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027156 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046219 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046219 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026007 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026007 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12601.844185 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12601.844185 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40080.679961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40080.679961 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11870.601589 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11870.601589 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595786 # number of writebacks +system.cpu.dcache.writebacks::total 595786 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368488 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368488 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250225 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250225 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618713 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618713 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618713 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618713 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4644879500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4644879500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10059088985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10059088985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136816250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136816250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14703968485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14703968485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14703968485 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14703968485 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050953750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050953750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234980190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234980190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208285933940 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208285933940 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12605.239519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12605.239519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40200.175782 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40200.175782 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11897.065217 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11897.065217 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1231,44 +1250,44 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 53002965 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454953 # Transaction distribution +system.cpu.toL2Bus.throughput 53012095 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2455185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2455185 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595512 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247368 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725126 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5750616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27468 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7515671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54754292 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83665829 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14140 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34916 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 138469177 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138469177 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166564 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3009252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 595786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247327 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725213 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5751160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7516299 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54757044 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83692777 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14148 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34900 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 138498869 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138498869 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3009752500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1291764000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1296058500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2507996500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2542947575 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18739000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1277,10 +1296,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1470128900250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1470128900250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1466807214000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1466807214000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 35b3a08bb..b5f8111f8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -223,27 +223,27 @@ system.realview.nvmem.bw_total::total 9 # To system.membus.throughput 55969561 # Throughput (bytes/s) system.membus.data_through_bus 130566366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.replacements 62242 # number of replacements -system.l2c.tagsinuse 50006.300222 # Cycle average of tags in use -system.l2c.total_refs 1678485 # Total number of references to valid blocks. -system.l2c.sampled_refs 127627 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.151488 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.763036 # Average percentage of cache occupancy +system.l2c.tags.replacements 62242 # number of replacements +system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use +system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits @@ -456,17 +456,17 @@ system.cpu0.not_idle_fraction 0.959732 # Pe system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu0.icache.replacements 850590 # number of replacements -system.cpu0.icache.tagsinuse 511.678593 # Cycle average of tags in use -system.cpu0.icache.total_refs 60583498 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 850590 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits @@ -512,17 +512,17 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 623334 # number of replacements -system.cpu0.dcache.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23628284 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 623846 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.875187 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 623334 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits @@ -666,12 +666,12 @@ system.cpu1.not_idle_fraction -0.942843 # Pe system.cpu1.idle_fraction 1.942843 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 3eb24dda0..56bd99bdd 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112100 # Number of seconds simulated -sim_ticks 5112099860500 # Number of ticks simulated -final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112102 # Number of seconds simulated +sim_ticks 5112102211000 # Number of ticks simulated +final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 794426 # Simulator instruction rate (inst/s) -host_op_rate 1626557 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20315509625 # Simulator tick rate (ticks/s) -host_mem_usage 586244 # Number of bytes of host memory used -host_seconds 251.64 # Real time elapsed on the host -sim_insts 199905607 # Number of instructions simulated -sim_ops 409299132 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory +host_inst_rate 878832 # Simulator instruction rate (inst/s) +host_op_rate 1799374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22473674513 # Simulator tick rate (ticks/s) +host_mem_usage 586256 # Number of bytes of host memory used +host_seconds 227.47 # Real time elapsed on the host +sim_insts 199908396 # Number of instructions simulated +sim_ops 409304707 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory -system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10605120 # Number of bytes read from this memory +system.physmem.bytes_read::total 13879360 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9264448 # Number of bytes written to this memory -system.physmem.bytes_written::total 9264448 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 37827 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 9264512 # Number of bytes written to this memory +system.physmem.bytes_written::total 9264512 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37829 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165706 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216864 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 144757 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144757 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 473568 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.data 165705 # Number of read requests responded to by this memory +system.physmem.num_reads::total 216865 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 144758 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144758 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 473593 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2074526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2714989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2074513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2715000 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1812259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1812259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1812259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 473568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1812270 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1812270 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1812270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 473593 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2074526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4527248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -192,34 +192,34 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests -system.membus.throughput 9632717 # Throughput (bytes/s) -system.membus.data_through_bus 49243411 # Total data (bytes) +system.membus.throughput 9632725 # Throughput (bytes/s) +system.membus.data_through_bus 49243475 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.replacements 47568 # number of replacements -system.iocache.tagsinuse 0.042441 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 903 # number of ReadReq misses +system.iocache.tags.replacements 47569 # number of replacements +system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses -system.iocache.demand_misses::total 47623 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses -system.iocache.overall_misses::total 47623 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses +system.iocache.demand_misses::total 47624 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses +system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -241,7 +241,7 @@ system.iocache.writebacks::total 46667 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -252,58 +252,58 @@ system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.iobus.throughput 2555194 # Throughput (bytes/s) -system.iobus.data_through_bus 13062406 # Total data (bytes) -system.cpu.numCycles 10224199744 # number of cpu cycles simulated +system.iobus.data_through_bus 13062414 # Total data (bytes) +system.cpu.numCycles 10224204444 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199905607 # Number of instructions committed -system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374462047 # Number of integer alu accesses +system.cpu.committedInsts 199908396 # Number of instructions committed +system.cpu.committedOps 409304707 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374467605 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2307315 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls -system.cpu.num_int_insts 374462047 # number of integer instructions +system.cpu.num_func_calls 2307395 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39972475 # number of instructions that are conditional controls +system.cpu.num_int_insts 374467605 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915890300 # number of times the integer registers were read -system.cpu.num_int_register_writes 480542889 # number of times the integer registers were written +system.cpu.num_int_register_reads 915905592 # number of times the integer registers were read +system.cpu.num_int_register_writes 480549431 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35654170 # number of memory refs -system.cpu.num_load_insts 27234345 # Number of load instructions -system.cpu.num_store_insts 8419825 # Number of store instructions -system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles -system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles -system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955627 # Percentage of idle cycles +system.cpu.num_mem_refs 35655576 # number of memory refs +system.cpu.num_load_insts 27235236 # Number of load instructions +system.cpu.num_store_insts 8420340 # Number of store instructions +system.cpu.num_idle_cycles 9770516372.735863 # Number of idle cycles +system.cpu.num_busy_cycles 453688071.264138 # Number of busy cycles +system.cpu.not_idle_fraction 0.044374 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955626 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790584 # number of replacements -system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use -system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits -system.cpu.icache.overall_hits::total 243492014 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses -system.cpu.icache.overall_misses::total 791103 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 790522 # number of replacements +system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243495984 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243495984 # number of overall hits +system.cpu.icache.overall_hits::total 243495984 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791041 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791041 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791041 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791041 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791041 # number of overall misses +system.cpu.icache.overall_misses::total 791041 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244287025 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244287025 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244287025 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244287025 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244287025 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244287025 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses @@ -319,15 +319,15 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3477 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.189143 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -367,39 +367,39 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7629 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12955 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12955 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12955 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12955 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12955 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12955 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8819 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8819 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8819 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8819 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8819 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8819 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21774 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21774 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21774 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21774 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21774 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21774 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405024 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405024 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405024 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405024 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405024 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405024 # miss rate for overall accesses +system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12956 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12956 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12956 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12956 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12956 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12956 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8822 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8822 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8822 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8822 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8822 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8822 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21778 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21778 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21778 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21778 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21778 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21778 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405088 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405088 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405088 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405088 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405088 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405088 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,47 +411,47 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621960 # number of replacements -system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use -system.cpu.dcache.total_refs 20168705 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622472 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.430849 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12073185 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12073185 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8093252 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8093252 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20166437 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20166437 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20166437 # number of overall hits -system.cpu.dcache.overall_hits::total 20166437 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308369 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308369 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316387 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316387 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624756 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624756 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624756 # number of overall misses -system.cpu.dcache.overall_misses::total 1624756 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8409639 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21791193 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097774 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses +system.cpu.dcache.tags.replacements 1622027 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8093747 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20167772 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20167772 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20167772 # number of overall hits +system.cpu.dcache.overall_hits::total 20167772 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308420 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308420 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316403 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316403 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624823 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624823 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624823 # number of overall misses +system.cpu.dcache.overall_misses::total 1624823 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13382445 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13382445 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8410150 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8410150 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21792595 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21792595 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21792595 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21792595 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097771 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097771 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074560 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074558 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074558 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074558 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074558 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -460,50 +460,50 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535700 # number of writebacks -system.cpu.dcache.writebacks::total 1535700 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535756 # number of writebacks +system.cpu.dcache.writebacks::total 1535756 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 54622198 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 279208723 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 25408 # Total snoop data (bytes) -system.cpu.l2cache.replacements 105930 # number of replacements -system.cpu.l2cache.tagsinuse 64819.953901 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3456506 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.325454 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51906.788145 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10422.435543 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989074 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits +system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) +system.cpu.l2cache.tags.replacements 105931 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275491 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062559 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538639 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538639 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062551 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1538695 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538695 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179721 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179721 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179738 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179738 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6502 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1455212 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2242280 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 777703 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1455282 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2242289 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6502 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1455212 # number of overall hits -system.cpu.l2cache.overall_hits::total 2242280 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777703 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1455282 # number of overall hits +system.cpu.l2cache.overall_hits::total 2242289 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses @@ -511,58 +511,58 @@ system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134393 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134393 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134392 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134392 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166639 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 179971 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166638 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179970 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166639 # number of overall misses -system.cpu.l2cache.overall_misses::total 179971 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 166638 # number of overall misses +system.cpu.l2cache.overall_misses::total 179970 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6504 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307737 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108137 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538639 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538639 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791028 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2108129 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1538695 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538695 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314114 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314114 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314130 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314130 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6504 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621851 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422251 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791028 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2422259 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6504 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621851 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422251 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791028 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2422259 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024658 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427848 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.427848 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427823 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.427823 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102746 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074299 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102741 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074298 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102746 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074299 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102741 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074298 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -571,8 +571,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98090 # number of writebacks -system.cpu.l2cache.writebacks::total 98090 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98091 # number of writebacks +system.cpu.l2cache.writebacks::total 98091 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 3847513ea..bb1dca70a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196145 # Number of seconds simulated -sim_ticks 5196144770000 # Number of ticks simulated -final_tick 5196144770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196173 # Number of seconds simulated +sim_ticks 5196173457000 # Number of ticks simulated +final_tick 5196173457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 471788 # Simulator instruction rate (inst/s) -host_op_rate 909467 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19106715414 # Simulator tick rate (ticks/s) -host_mem_usage 586268 # Number of bytes of host memory used -host_seconds 271.95 # Real time elapsed on the host -sim_insts 128304418 # Number of instructions simulated -sim_ops 247333117 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2891776 # Number of bytes read from this memory +host_inst_rate 766970 # Simulator instruction rate (inst/s) +host_op_rate 1478526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31067837744 # Simulator tick rate (ticks/s) +host_mem_usage 586132 # Number of bytes of host memory used +host_seconds 167.25 # Real time elapsed on the host +sim_insts 128277551 # Number of instructions simulated +sim_ops 247287193 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2879808 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8961408 # Number of bytes read from this memory -system.physmem.bytes_read::total 12677312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8105792 # Number of bytes written to this memory -system.physmem.bytes_written::total 8105792 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45184 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 826368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8990464 # Number of bytes read from this memory +system.physmem.bytes_read::total 12697024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 826368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 826368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8117888 # Number of bytes written to this memory +system.physmem.bytes_written::total 8117888 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44997 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140022 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198083 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126653 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126653 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 556523 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12912 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140476 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198391 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126842 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126842 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 554217 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1724626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2439753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1559963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1559963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1559963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 556523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1730209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2443534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159034 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159034 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1562282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1562282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1562282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 554217 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1724626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3999716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198083 # Total number of read requests seen -system.physmem.writeReqs 126653 # Total number of write requests seen -system.physmem.cpureqs 326336 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 12677312 # Total number of bytes read from memory -system.physmem.bytesWritten 8105792 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12677312 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8105792 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1597 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12388 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12742 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12822 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12061 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12170 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 11780 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 11808 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12505 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12558 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12047 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7920 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8110 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8533 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 8387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8388 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7744 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7959 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7196 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7383 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7714 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 159034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1730209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4005815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198391 # Total number of read requests seen +system.physmem.writeReqs 126842 # Total number of write requests seen +system.physmem.cpureqs 326873 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 12697024 # Total number of bytes read from memory +system.physmem.bytesWritten 8117888 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 12697024 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 8117888 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1638 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 12755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12296 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 12564 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 12046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 12490 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12561 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12978 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12970 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12385 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12026 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8334 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7804 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7872 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8132 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7928 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7689 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7475 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7683 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8127 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 7959 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8471 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7991 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7509 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry -system.physmem.totGap 5196144706500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry +system.physmem.totGap 5196173392500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198083 # Categorize read packet sizes +system.physmem.readPktSize::6 198391 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 126653 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 154572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1181 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126842 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 155016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1177 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1109 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1095 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -136,200 +136,201 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4302 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 4658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 458.910923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.789921 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1568.289191 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 18577 41.06% 41.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 7110 15.72% 56.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4218 9.32% 66.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2889 6.39% 72.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2001 4.42% 76.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1601 3.54% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1275 2.82% 83.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 961 2.12% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 799 1.77% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 633 1.40% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 499 1.10% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 460 1.02% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 337 0.74% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 345 0.76% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 215 0.48% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 394 0.87% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 170 0.38% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 159 0.35% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 128 0.28% 94.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 109 0.24% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 88 0.19% 94.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 127 0.28% 95.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 644 1.42% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 160 0.35% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 109 0.24% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 90 0.20% 97.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 61 0.13% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 44 0.10% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 17 0.04% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 21 0.05% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 12 0.03% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 37 0.08% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 16 0.04% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 11 0.02% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 9 0.02% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 7 0.02% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 9 0.02% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 6 0.01% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.01% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.00% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 5 0.01% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 3 0.01% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.00% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.00% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.00% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 11 0.02% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 98.25% # Bytes accessed per row activation +system.physmem.wrQLenPdf::2 5452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 45212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 459.873662 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.351443 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1570.406469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 18373 40.64% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 7212 15.95% 56.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4299 9.51% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2899 6.41% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2036 4.50% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1645 3.64% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1210 2.68% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 976 2.16% 85.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 783 1.73% 87.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 608 1.34% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 508 1.12% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 473 1.05% 90.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 299 0.66% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 322 0.71% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 227 0.50% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 394 0.87% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 154 0.34% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 143 0.32% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 136 0.30% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 125 0.28% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 123 0.27% 94.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 132 0.29% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 601 1.33% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 193 0.43% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 92 0.20% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 79 0.17% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 66 0.15% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 49 0.11% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 20 0.04% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 25 0.06% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 17 0.04% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 28 0.06% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 17 0.04% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 13 0.03% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 13 0.03% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 10 0.02% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 13 0.03% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 7 0.02% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 10 0.02% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 19 0.04% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 5 0.01% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 2 0.00% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 2 0.00% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 3 0.01% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 6 0.01% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 4 0.01% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 5 0.01% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 3 0.01% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 2 0.00% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 8 0.02% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.00% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 2 0.00% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 15 0.03% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 3 0.01% 98.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::3968-3971 1 0.00% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 14 0.03% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.00% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.00% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 13 0.03% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 3 0.01% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 3 0.01% 98.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::4480-4483 3 0.01% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.01% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 98.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5059 4 0.01% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 2 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.01% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 3 0.01% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 2 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 2 0.00% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 3 0.01% 98.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 2 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 2 0.00% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 98.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 98.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6403 1 0.00% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 4 0.01% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 12 0.03% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 5 0.01% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 8 0.02% 98.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6915 2 0.00% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.00% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 7 0.02% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 2 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 340 0.75% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 7 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 8 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 2 0.00% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 342 0.76% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 3 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 2 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 2 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 6 0.01% 99.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 10 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 237 0.52% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 13 0.03% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 17 0.04% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17283 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17603 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17859 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45242 # Bytes accessed per row activation -system.physmem.totQLat 3435518998 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7067756498 # Sum of mem lat for all requests -system.physmem.totBusLat 990065000 # Total cycles spent in databus access -system.physmem.totBankLat 2642172500 # Total cycles spent in bank access -system.physmem.avgQLat 17349.97 # Average queueing delay per request -system.physmem.avgBankLat 13343.43 # Average bank access latency per request +system.physmem.bytesPerActivate::15040-15043 2 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 5 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 241 0.53% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 16 0.04% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 8 0.02% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 6 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17411 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17475 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 45212 # Bytes accessed per row activation +system.physmem.totQLat 3446222750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7081229000 # Sum of mem lat for all requests +system.physmem.totBusLat 991555000 # Total cycles spent in databus access +system.physmem.totBankLat 2643451250 # Total cycles spent in bank access +system.physmem.avgQLat 17377.87 # Average queueing delay per request +system.physmem.avgBankLat 13329.83 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35693.40 # Average memory access latency +system.physmem.avgMemAccLat 35707.70 # Average memory access latency system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s @@ -337,99 +338,99 @@ system.physmem.avgConsumedWrBW 1.56 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.35 # Average write queue length over time -system.physmem.readRowHits 181015 # Number of row buffer hits during reads -system.physmem.writeRowHits 98394 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.69 # Row buffer hit rate for writes -system.physmem.avgGap 16001135.40 # Average gap between requests -system.membus.throughput 4358895 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 623371 # Transaction distribution -system.membus.trans_dist::ReadResp 623371 # Transaction distribution -system.membus.trans_dist::WriteReq 13727 # Transaction distribution -system.membus.trans_dist::WriteResp 13727 # Transaction distribution -system.membus.trans_dist::Writeback 126653 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2147 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1615 # Transaction distribution -system.membus.trans_dist::ReadExReq 159120 # Transaction distribution -system.membus.trans_dist::ReadExResp 159120 # Transaction distribution -system.membus.trans_dist::MessageReq 1656 # Transaction distribution -system.membus.trans_dist::MessageResp 1656 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390174 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580408 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139407 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 139407 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 529581 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 480118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1723127 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16571083 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5878592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5878592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 20783104 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22456299 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22456299 # Total data (bytes) -system.membus.snoop_data_through_bus 193152 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1348670998 # Layer occupancy (ticks) +system.physmem.avgWrQLen 12.20 # Average write queue length over time +system.physmem.readRowHits 181450 # Number of row buffer hits during reads +system.physmem.writeRowHits 98471 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes +system.physmem.avgGap 15976771.71 # Average gap between requests +system.membus.throughput 4367376 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 623405 # Transaction distribution +system.membus.trans_dist::ReadResp 623405 # Transaction distribution +system.membus.trans_dist::WriteReq 13711 # Transaction distribution +system.membus.trans_dist::WriteResp 13711 # Transaction distribution +system.membus.trans_dist::Writeback 126842 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2139 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1656 # Transaction distribution +system.membus.trans_dist::ReadExReq 159580 # Transaction distribution +system.membus.trans_dist::ReadExResp 159580 # Transaction distribution +system.membus.trans_dist::MessageReq 1655 # Transaction distribution +system.membus.trans_dist::MessageResp 1655 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 139223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 530613 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 480072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1724109 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16614957 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5866496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5866496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 20814912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22488073 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22488073 # Total data (bytes) +system.membus.snoop_data_through_bus 205568 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1351024000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 256617500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 256571500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 359320000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 359320500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3312000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3310000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2607874799 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2612485256 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 428809000 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 428859500 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 47501 # number of replacements -system.iocache.tagsinuse 0.169264 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47517 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5049524013000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.169264 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.010579 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.010579 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 834 # number of ReadReq misses -system.iocache.ReadReq_misses::total 834 # number of ReadReq misses +system.iocache.tags.replacements 47504 # number of replacements +system.iocache.tags.tagsinuse 0.125284 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 5049571138000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.125284 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007830 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007830 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses +system.iocache.ReadReq_misses::total 839 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47554 # number of demand (read+write) misses -system.iocache.demand_misses::total 47554 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47554 # number of overall misses -system.iocache.overall_misses::total 47554 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142703185 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 142703185 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10862337325 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10862337325 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11005040510 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11005040510 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11005040510 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11005040510 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 834 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 834 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47559 # number of demand (read+write) misses +system.iocache.demand_misses::total 47559 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47559 # number of overall misses +system.iocache.overall_misses::total 47559 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142400936 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 142400936 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10875044083 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10875044083 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11017445019 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11017445019 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11017445019 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11017445019 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47554 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47554 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47554 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47554 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47559 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47559 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47559 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47559 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -438,40 +439,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171106.936451 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 171106.936451 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 232498.658497 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 232498.658497 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 231421.973125 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 231421.973125 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 174194 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169726.979738 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 169726.979738 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 232770.635338 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 232770.635338 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 231658.466726 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 231658.466726 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 231658.466726 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 231658.466726 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 178608 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16040 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16401 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.859975 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.890068 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46669 # number of writebacks -system.iocache.writebacks::total 46669 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 834 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 834 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47554 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47554 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47554 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47554 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99319185 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 99319185 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8432090325 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8432090325 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8531409510 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8531409510 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47559 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47559 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47559 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47559 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98742936 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 98742936 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8443977083 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8443977083 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8542720019 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8542720019 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8542720019 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8542720019 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -480,14 +481,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119087.751799 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 119087.751799 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 180481.385381 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 180481.385381 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117691.222884 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117691.222884 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 180735.810852 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 180735.810852 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 179623.625791 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 179623.625791 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 179623.625791 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 179623.625791 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -501,16 +502,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 631272 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 230083 # Transaction distribution -system.iobus.trans_dist::ReadResp 230083 # Transaction distribution -system.iobus.trans_dist::WriteReq 57530 # Transaction distribution -system.iobus.trans_dist::WriteResp 57530 # Transaction distribution -system.iobus.trans_dist::MessageReq 1656 # Transaction distribution -system.iobus.trans_dist::MessageResp 1656 # Transaction distribution +system.iobus.throughput 631271 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 230080 # Transaction distribution +system.iobus.trans_dist::ReadResp 230080 # Transaction distribution +system.iobus.trans_dist::WriteReq 57515 # Transaction distribution +system.iobus.trans_dist::WriteResp 57515 # Transaction distribution +system.iobus.trans_dist::MessageReq 1655 # Transaction distribution +system.iobus.trans_dist::MessageResp 1655 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) @@ -526,15 +527,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 480118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95108 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 480072 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) @@ -549,12 +550,12 @@ system.iobus.pkt_count::system.pc.fake_com_2.pio 12 system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 578538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 578500 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) @@ -570,15 +571,15 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 246342 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 246316 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) @@ -593,17 +594,17 @@ system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 3027216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3280182 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3280182 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3949664 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 3280192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3280192 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3949164 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -633,85 +634,85 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424330510 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424368519 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 469308000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 469277000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52196000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53493500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.numCycles 10392289540 # number of cpu cycles simulated +system.cpu.numCycles 10392346914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128304418 # Number of instructions committed -system.cpu.committedOps 247333117 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232067207 # Number of integer alu accesses +system.cpu.committedInsts 128277551 # Number of instructions committed +system.cpu.committedOps 247287193 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232021751 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2300061 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23160261 # number of instructions that are conditional controls -system.cpu.num_int_insts 232067207 # number of integer instructions +system.cpu.num_func_calls 2299501 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23156792 # number of instructions that are conditional controls +system.cpu.num_int_insts 232021751 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567198543 # number of times the integer registers were read -system.cpu.num_int_register_writes 293301890 # number of times the integer registers were written +system.cpu.num_int_register_reads 567075946 # number of times the integer registers were read +system.cpu.num_int_register_writes 293251743 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22245318 # number of memory refs -system.cpu.num_load_insts 13878816 # Number of load instructions -system.cpu.num_store_insts 8366502 # Number of store instructions -system.cpu.num_idle_cycles 9785692797.998116 # Number of idle cycles -system.cpu.num_busy_cycles 606596742.001883 # Number of busy cycles -system.cpu.not_idle_fraction 0.058370 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941630 # Percentage of idle cycles +system.cpu.num_mem_refs 22231243 # number of memory refs +system.cpu.num_load_insts 13871494 # Number of load instructions +system.cpu.num_store_insts 8359749 # Number of store instructions +system.cpu.num_idle_cycles 9785544869.998116 # Number of idle cycles +system.cpu.num_busy_cycles 606802044.001883 # Number of busy cycles +system.cpu.not_idle_fraction 0.058389 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.941611 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 791404 # number of replacements -system.cpu.icache.tagsinuse 510.366672 # Cycle average of tags in use -system.cpu.icache.total_refs 144533937 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791916 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.511702 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 161113577000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.366672 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996810 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996810 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144533937 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144533937 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144533937 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144533937 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144533937 # number of overall hits -system.cpu.icache.overall_hits::total 144533937 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791923 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791923 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791923 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791923 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791923 # number of overall misses -system.cpu.icache.overall_misses::total 791923 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11177158500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11177158500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11177158500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11177158500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11177158500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11177158500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145325860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145325860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145325860 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145325860 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145325860 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145325860 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14113.946053 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14113.946053 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14113.946053 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14113.946053 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14113.946053 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14113.946053 # average overall miss latency +system.cpu.icache.tags.replacements 791620 # number of replacements +system.cpu.icache.tags.tagsinuse 510.364411 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144498695 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 792132 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.417444 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161170792250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.364411 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996805 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996805 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144498695 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144498695 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144498695 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144498695 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144498695 # number of overall hits +system.cpu.icache.overall_hits::total 144498695 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792139 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792139 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792139 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792139 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792139 # number of overall misses +system.cpu.icache.overall_misses::total 792139 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11198521009 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11198521009 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11198521009 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11198521009 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11198521009 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11198521009 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145290834 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145290834 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145290834 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145290834 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145290834 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145290834 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005452 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005452 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005452 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005452 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005452 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005452 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14137.065602 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14137.065602 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14137.065602 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14137.065602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14137.065602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14137.065602 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,80 +721,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791923 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791923 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791923 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791923 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791923 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791923 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9593312500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9593312500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9593312500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9593312500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9593312500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9593312500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12113.946053 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12113.946053 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12113.946053 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12113.946053 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12113.946053 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12113.946053 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792139 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 792139 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 792139 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 792139 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 792139 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 792139 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9607971991 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9607971991 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9607971991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9607971991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9607971991 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9607971991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005452 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005452 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005452 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005452 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005452 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005452 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12129.149039 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12129.149039 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12129.149039 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12129.149039 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12129.149039 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12129.149039 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3530 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.075423 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7811 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3541 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.205874 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5166918586000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.075423 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192214 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.192214 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7833 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7833 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 3473 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.080805 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7889 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3486 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.263052 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5163044300000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.080805 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192550 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.192550 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7889 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7889 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7835 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7835 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7835 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7835 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4388 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4388 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4388 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4388 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4388 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4388 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43163000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43163000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43163000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 43163000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43163000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 43163000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7891 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7891 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7891 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7891 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4335 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4335 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4335 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4335 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4335 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4335 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44091250 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44091250 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44091250 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 44091250 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44091250 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 44091250 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.359054 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.359054 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358995 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.358995 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358995 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.358995 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9836.599818 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9836.599818 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9836.599818 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9836.599818 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9836.599818 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9836.599818 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354630 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354630 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354572 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.354572 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354572 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.354572 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10170.991926 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10170.991926 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10170.991926 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10170.991926 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10170.991926 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10170.991926 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,78 +803,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 619 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 619 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4388 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4388 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4388 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4388 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4388 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4388 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34387000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34387000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34387000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34387000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34387000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34387000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.359054 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.359054 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358995 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358995 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358995 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358995 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7836.599818 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7836.599818 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7836.599818 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 892 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 892 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4335 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4335 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4335 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4335 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4335 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4335 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35418750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35418750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35418750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35418750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35418750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35418750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.354630 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.354630 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.354572 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.354572 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.354572 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.354572 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8170.415225 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8170.415225 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8170.415225 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8170.415225 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8170.415225 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8170.415225 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7412 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.056524 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13351 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7427 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.797630 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5162997491000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.056524 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316033 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.316033 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13351 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13351 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13351 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13351 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13351 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13351 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8618 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8618 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8618 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8618 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8618 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8618 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 90576000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 90576000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 90576000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 90576000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 90576000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 90576000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21969 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21969 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21969 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21969 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21969 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21969 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392280 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392280 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392280 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392280 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392280 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392280 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10510.095150 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10510.095150 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10510.095150 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10510.095150 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10510.095150 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10510.095150 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 7524 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.060120 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13176 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7539 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.747712 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5163729602000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.060120 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316258 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316258 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13177 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13177 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13177 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13177 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13177 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13177 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8707 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8707 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8707 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8707 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8707 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8707 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 93129000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 93129000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 93129000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 93129000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 93129000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 93129000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21884 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21884 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21884 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21884 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21884 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21884 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.397871 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397871 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.397871 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.397871 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397871 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.397871 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10695.876881 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10695.876881 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10695.876881 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10695.876881 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10695.876881 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10695.876881 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -882,90 +883,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2749 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2749 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8618 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8618 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8618 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8618 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8618 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8618 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 73340000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 73340000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 73340000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 73340000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 73340000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 73340000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392280 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392280 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392280 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8510.095150 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8510.095150 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8510.095150 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3011 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3011 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8707 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8707 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8707 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8707 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8707 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8707 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 75714500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 75714500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 75714500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 75714500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 75714500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 75714500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.397871 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.397871 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.397871 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.397871 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397871 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397871 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8695.819456 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8695.819456 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8695.819456 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8695.819456 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8695.819456 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8695.819456 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1622441 # number of replacements -system.cpu.dcache.tagsinuse 511.992388 # Cycle average of tags in use -system.cpu.dcache.total_refs 20034872 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622953 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.344703 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 48929000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.992388 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11992680 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11992680 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8039994 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8039994 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20032674 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20032674 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20032674 # number of overall hits -system.cpu.dcache.overall_hits::total 20032674 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308966 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308966 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316237 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316237 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1625203 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1625203 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1625203 # number of overall misses -system.cpu.dcache.overall_misses::total 1625203 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18848048000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18848048000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10644655000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10644655000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29492703000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29492703000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29492703000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29492703000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13301646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13301646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8356231 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8356231 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21657877 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21657877 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21657877 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21657877 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098406 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098406 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037844 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037844 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075040 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075040 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075040 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.188367 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.188367 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33660.371810 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33660.371810 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18147.088702 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18147.088702 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18147.088702 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18147.088702 # average overall miss latency +system.cpu.dcache.tags.replacements 1620395 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997299 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20022949 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1620907 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.352929 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 49459250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997299 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11985789 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11985789 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8034970 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8034970 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20020759 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20020759 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20020759 # number of overall hits +system.cpu.dcache.overall_hits::total 20020759 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308577 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308577 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314536 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314536 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623113 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623113 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623113 # number of overall misses +system.cpu.dcache.overall_misses::total 1623113 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18867836541 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18867836541 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10715308194 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10715308194 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29583144735 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29583144735 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29583144735 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29583144735 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13294366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13294366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8349506 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8349506 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21643872 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21643872 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21643872 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21643872 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098431 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098431 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037671 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037671 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074992 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074992 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074992 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074992 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14418.590989 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14418.590989 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34067.032689 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34067.032689 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18226.176942 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18226.176942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18226.176942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18226.176942 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -974,46 +975,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539801 # number of writebacks -system.cpu.dcache.writebacks::total 1539801 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308966 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1308966 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316237 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316237 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1625203 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1625203 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625203 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16230116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16230116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10012181000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10012181000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26242297000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26242297000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26242297000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26242297000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94201595500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94201595500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2525692000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2525692000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96727287500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96727287500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098406 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098406 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075040 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075040 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075040 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12399.188367 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12399.188367 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31660.371810 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31660.371810 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16147.088702 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16147.088702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16147.088702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16147.088702 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1537197 # number of writebacks +system.cpu.dcache.writebacks::total 1537197 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308577 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308577 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314536 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314536 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1623113 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1623113 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1623113 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1623113 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16237300459 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16237300459 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031005806 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031005806 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26268306265 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26268306265 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26268306265 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26268306265 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94200368500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94200368500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2523287500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2523287500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96723656000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96723656000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037671 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037671 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074992 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074992 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074992 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12408.364551 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12408.364551 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31891.439473 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31891.439473 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16183.904796 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16183.904796 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16183.904796 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16183.904796 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1021,175 +1022,175 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 49236259 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2696119 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2695598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543169 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 360759 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314063 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1583833 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5979450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 7815 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 17592 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7588690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50682240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 204056779 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 219328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 574336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 255532683 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 255511115 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 327616 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3834241500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 49187749 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2695979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2695445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13711 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13711 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1541100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 359066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 312361 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1584265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5972620 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 8122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 18187 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7583194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50696064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 203753837 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 242368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 606720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 255298989 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 255278509 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 309568 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3830199000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 505500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 480000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1187884500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1191344009 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3023860000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3055023235 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6582000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6503750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 12927000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13060750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.replacements 86618 # number of replacements -system.cpu.l2cache.tagsinuse 64735.286295 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3491811 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 151264 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.084217 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 49971.529408 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.027392 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.141401 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3486.795305 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11276.792789 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.762505 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.053204 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.172070 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.987782 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6224 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779038 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1279905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2067970 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543169 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543169 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 330 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 330 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 201356 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 201356 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6224 # 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number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 79984 # number of writebacks -system.cpu.l2cache.writebacks::total 79984 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 80175 # number of writebacks +system.cpu.l2cache.writebacks::total 80175 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12872 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28269 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41147 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1336 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1336 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112679 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851715758 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8037166125 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8889284383 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 679250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 860763509 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8048978841 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8910497850 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851715758 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8037166125 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8889284383 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86643520000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86643520000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2359628500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2359628500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89003148500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89003148500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021610 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019509 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.801921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.801921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358810 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358810 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063482 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063482 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 679250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 860763509 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8048978841 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8910497850 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86642397000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86642397000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2357413500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2357413500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88999810500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88999810500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001727 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362116 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362116 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001727 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087260 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063714 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001727 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087260 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063714 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66168.098042 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62664.695921 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63761.308163 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10696.720060 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10696.720060 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55606.615572 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55606.615572 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 135850 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66658.677999 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62851.938475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64054.706925 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10702.120397 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10702.120397 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55457.532890 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55457.532890 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 135850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66658.677999 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56935.953717 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57752.371215 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 135850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66658.677999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56935.953717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57752.371215 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 35c6d79b2..9728f1e09 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24560000 # Number of ticks simulated -final_tick 24560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25046000 # Number of ticks simulated +final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1785 # Simulator instruction rate (inst/s) -host_op_rate 1785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6860090 # Simulator tick rate (ticks/s) -host_mem_usage 225432 # Number of bytes of host memory used -host_seconds 3.58 # Real time elapsed on the host +host_inst_rate 25238 # Simulator instruction rate (inst/s) +host_op_rate 25236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98905790 # Simulator tick rate (ticks/s) +host_mem_usage 225424 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 781758958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 437785016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1219543974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 781758958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 781758958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 781758958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 437785016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1219543974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 766589475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 429290106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1195879582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 766589475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 766589475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24545500 # Total gap between requests +system.physmem.totGap 25031500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # By system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation -system.physmem.totQLat 1607750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11529000 # Sum of mem lat for all requests +system.physmem.totQLat 1857500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11820000 # Sum of mem lat for all requests system.physmem.totBusLat 2345000 # Total cycles spent in databus access -system.physmem.totBankLat 7576250 # Total cycles spent in bank access -system.physmem.avgQLat 3428.04 # Average queueing delay per request -system.physmem.avgBankLat 16154.05 # Average bank access latency per request +system.physmem.totBankLat 7617500 # Total cycles spent in bank access +system.physmem.avgQLat 3960.55 # Average queueing delay per request +system.physmem.avgBankLat 16242.00 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24582.09 # Average memory access latency -system.physmem.avgRdBW 1219.54 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25202.56 # Average memory access latency +system.physmem.avgRdBW 1195.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1219.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1195.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.53 # Data bus utilization in percentage +system.physmem.busUtil 9.34 # Data bus utilization in percentage system.physmem.avgRdQLen 0.47 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 402 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 52335.82 # Average gap between requests -system.membus.throughput 1219543974 # Throughput (bytes/s) +system.physmem.avgGap 53372.07 # Average gap between requests +system.membus.throughput 1195879582 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -201,10 +201,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 563500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 4381500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4378000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.5 # Layer utilization (%) system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -247,7 +247,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 49121 # number of cpu cycles simulated +system.cpu.numCycles 50093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). @@ -269,12 +269,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11658 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11606 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 510 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41745 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 460 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42717 # Number of cycles cpu's stages were not processed system.cpu.runCycles 7376 # Number of cycles cpu stages are processed. -system.cpu.activity 15.015981 # Percentage of cycles cpu is active +system.cpu.activity 14.724612 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -286,36 +286,36 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 7.687167 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.839280 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.687167 # CPI: Total CPI of All Threads -system.cpu.ipc 0.130087 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.839280 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127563 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.130087 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 44197 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127563 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45169 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 10.024226 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45228 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.829717 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46200 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.925327 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44960 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.771545 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 45932 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.470919 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47787 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.306550 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48759 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.715743 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 44663 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.663047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.075548 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 140.779037 # Cycle average of tags in use -system.cpu.icache.total_refs 560 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 140.779037 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.068740 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.068740 # Average percentage of cache occupancy +system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -328,12 +328,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24103000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24103000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24103000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24103000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24103000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24103000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24600000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24600000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24600000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24600000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24600000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24600000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -346,17 +346,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67895.774648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67895.774648 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67895.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67895.774648 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69295.774648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69295.774648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69295.774648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69295.774648 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -372,26 +372,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20462500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20462500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20462500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20462500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20462500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20462500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20800250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20800250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20800250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20800250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20800250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20800250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67756.622517 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67756.622517 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68875 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68875 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1222149837 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1198434880 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -405,22 +405,22 @@ system.cpu.toL2Bus.tot_pkt_size 30016 # Cu system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 451500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 197.103662 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.828803 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.274859 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006015 # Average percentage of cache occupancy +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 512750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -438,17 +438,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20144000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6932500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27076500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4877500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4877500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11810000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31954000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20144000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11810000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31954000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20481750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6961500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27443250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4890250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4890250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20481750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11851750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32333500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20481750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11851750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32333500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -471,17 +471,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66923.588040 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72973.684211 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68375 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66815.068493 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66815.068493 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68132.196162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68132.196162 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68045.681063 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73278.947368 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69301.136364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66989.726027 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66989.726027 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68941.364606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68941.364606 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,17 +501,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16417750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5764000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22181750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16699250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5777500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22476750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16417750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9750750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26168500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16417750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9750750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26168500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16699250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9764250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26463500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16699250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9764250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26463500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -523,27 +523,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54544.019934 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60673.684211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56014.520202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55479.235880 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60815.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56759.469697 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.747723 # Cycle average of tags in use -system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.747723 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025085 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025085 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -560,14 +560,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7336500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7336500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21108000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21108000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28444500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28444500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28444500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28444500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7410000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7410000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21312750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21312750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28722750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28722750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28722750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28722750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -584,19 +584,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75634.020619 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75634.020619 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60308.571429 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60308.571429 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63634.228188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63634.228188 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76391.752577 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76391.752577 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60893.571429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60893.571429 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64256.711409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64256.711409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.533333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -616,14 +616,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7034000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7034000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4955000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4955000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11989000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11989000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11989000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11989000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7063000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7063000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4967750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4967750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12030750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12030750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -632,14 +632,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74042.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74042.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67876.712329 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67876.712329 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74347.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74347.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68051.369863 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68051.369863 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 9e4861fce..38483afa5 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20632000 # Number of ticks simulated -final_tick 20632000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20671000 # Number of ticks simulated +final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1782 # Simulator instruction rate (inst/s) -host_op_rate 1782 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5769044 # Simulator tick rate (ticks/s) -host_mem_usage 227476 # Number of bytes of host memory used -host_seconds 3.58 # Real time elapsed on the host +host_inst_rate 25591 # Simulator instruction rate (inst/s) +host_op_rate 25589 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83008053 # Simulator tick rate (ticks/s) +host_mem_usage 227468 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 970918961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 539744087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1510663048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 970918961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 970918961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 970918961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 539744087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1510663048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 969087127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 538725751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1507812878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 969087127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 969087127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 488 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20599000 # Total gap between requests +system.physmem.totGap 20638000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see @@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # By system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation -system.physmem.totQLat 2633750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12636250 # Sum of mem lat for all requests +system.physmem.totQLat 2449250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12424250 # Sum of mem lat for all requests system.physmem.totBusLat 2440000 # Total cycles spent in databus access -system.physmem.totBankLat 7562500 # Total cycles spent in bank access -system.physmem.avgQLat 5397.03 # Average queueing delay per request -system.physmem.avgBankLat 15496.93 # Average bank access latency per request +system.physmem.totBankLat 7535000 # Total cycles spent in bank access +system.physmem.avgQLat 5018.95 # Average queueing delay per request +system.physmem.avgBankLat 15440.57 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25893.95 # Average memory access latency -system.physmem.avgRdBW 1510.66 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25459.53 # Average memory access latency +system.physmem.avgRdBW 1507.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1510.66 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1507.81 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.61 # Average read queue length over time +system.physmem.busUtil 11.78 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.60 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 419 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42211.07 # Average gap between requests -system.membus.throughput 1510663048 # Throughput (bytes/s) +system.physmem.avgGap 42290.98 # Average gap between requests +system.membus.throughput 1507812878 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -200,39 +200,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 600000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4561500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 22.1 # Layer utilization (%) -system.cpu.branchPred.lookups 2906 # Number of BP lookups -system.cpu.branchPred.condPredicted 1709 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2888 # Number of BP lookups +system.cpu.branchPred.condPredicted 1700 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2211 # Number of BTB lookups -system.cpu.branchPred.BTBHits 759 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups +system.cpu.branchPred.BTBHits 757 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.328358 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.393458 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 418 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2097 # DTB read hits +system.cpu.dtb.read_hits 2082 # DTB read hits system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2144 # DTB read accesses +system.cpu.dtb.read_accesses 2129 # DTB read accesses system.cpu.dtb.write_hits 1063 # DTB write hits system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1094 # DTB write accesses -system.cpu.dtb.data_hits 3160 # DTB hits +system.cpu.dtb.data_hits 3145 # DTB hits system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3238 # DTB accesses -system.cpu.itb.fetch_hits 2393 # ITB hits +system.cpu.dtb.data_accesses 3223 # DTB accesses +system.cpu.itb.fetch_hits 2387 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2432 # ITB accesses +system.cpu.itb.fetch_accesses 2426 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -246,237 +246,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 41265 # number of cpu cycles simulated +system.cpu.numCycles 41343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8511 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16675 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2906 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2982 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1908 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1525 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8507 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16592 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2888 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1175 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1903 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1523 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 759 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2393 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 379 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.103793 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.501598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 382 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.100776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.497742 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12125 80.26% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 320 2.12% 82.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.55% 83.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 215 1.42% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 256 1.69% 87.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 241 1.60% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.75% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 187 1.24% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1265 8.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12103 80.30% 80.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.11% 82.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 83.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 215 1.43% 85.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 257 1.71% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 241 1.60% 88.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 184 1.22% 91.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1257 8.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.070423 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.404095 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9355 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1672 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2793 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1224 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 15073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.069855 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.401325 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9323 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1686 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2770 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1220 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15419 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15336 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9566 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 693 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 555 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2621 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 448 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14692 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 1220 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9534 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 784 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2627 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 355 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14625 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 388 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11020 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18321 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18304 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 313 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10969 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18250 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18233 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6450 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 976 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2777 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1360 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 6399 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 29 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 808 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12985 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10814 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6280 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15107 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.715827 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359683 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12962 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6234 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 15073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.715651 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.357561 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10552 69.85% 69.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1715 11.35% 81.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1107 7.33% 88.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 773 5.12% 93.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 494 3.27% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 269 1.78% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 148 0.98% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 35 0.23% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10531 69.87% 69.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1674 11.11% 80.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1174 7.79% 88.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 731 4.85% 93.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 498 3.30% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 271 1.80% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 147 0.98% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15073 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 14 12.61% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 59 53.15% 65.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 38 34.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 15 13.27% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 60 53.10% 66.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 33.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7260 67.14% 67.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2415 22.33% 89.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1134 10.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7249 67.20% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2400 22.25% 89.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1133 10.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10814 # Type of FU issued -system.cpu.iq.rate 0.262062 # Inst issue rate -system.cpu.iq.fu_busy_cnt 111 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010264 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19300 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9631 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10787 # Type of FU issued +system.cpu.iq.rate 0.260915 # Inst issue rate +system.cpu.iq.fu_busy_cnt 113 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010476 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36793 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19230 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9615 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10912 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10887 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1594 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 495 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 136 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 131 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 218 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13104 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2777 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1360 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1220 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13080 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 509 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10116 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2155 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 698 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 505 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10087 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 700 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3251 # number of memory reference insts executed -system.cpu.iew.exec_branches 1595 # Number of branches executed +system.cpu.iew.exec_refs 3236 # number of memory reference insts executed +system.cpu.iew.exec_branches 1591 # Number of branches executed system.cpu.iew.exec_stores 1096 # Number of stores executed -system.cpu.iew.exec_rate 0.245147 # Inst execution rate -system.cpu.iew.wb_sent 9787 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9641 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5053 # num instructions producing a value -system.cpu.iew.wb_consumers 6805 # num instructions consuming a value +system.cpu.iew.exec_rate 0.243983 # Inst execution rate +system.cpu.iew.wb_sent 9767 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9625 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5058 # num instructions producing a value +system.cpu.iew.wb_consumers 6775 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.233636 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742542 # average fanout of values written-back +system.cpu.iew.wb_rate 0.232808 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.746568 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6713 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6689 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13883 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.460203 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266435 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13853 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.461200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.266599 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11056 79.64% 79.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1544 11.12% 90.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 511 3.68% 94.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 249 1.79% 96.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 151 1.09% 97.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 81 0.58% 97.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 113 0.81% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.25% 98.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11035 79.66% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1522 10.99% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 530 3.83% 94.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 235 1.70% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 147 1.06% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.78% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 103 0.74% 98.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.20% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 145 1.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13853 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,26 +487,26 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26491 # The number of ROB reads -system.cpu.rob.rob_writes 27437 # The number of ROB writes -system.cpu.timesIdled 274 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26158 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26435 # The number of ROB reads +system.cpu.rob.rob_writes 27385 # The number of ROB writes +system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26270 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 6.475989 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.475989 # CPI: Total CPI of All Threads -system.cpu.ipc 0.154417 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.154417 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12831 # number of integer regfile reads -system.cpu.int_regfile_writes 7294 # number of integer regfile writes +system.cpu.cpi 6.488230 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.488230 # CPI: Total CPI of All Threads +system.cpu.ipc 0.154125 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.154125 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12801 # number of integer regfile reads +system.cpu.int_regfile_writes 7277 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1513765025 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1510909003 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -521,55 +521,55 @@ system.cpu.toL2Bus.data_through_bus 31232 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 261000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.617277 # Cycle average of tags in use -system.cpu.icache.total_refs 1903 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.060510 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 159.617277 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077938 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1903 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1903 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1903 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1903 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1903 # number of overall hits -system.cpu.icache.overall_hits::total 1903 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 490 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 490 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 490 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 490 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 490 # number of overall misses -system.cpu.icache.overall_misses::total 490 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30064500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30064500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30064500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30064500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30064500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30064500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2393 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2393 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2393 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2393 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2393 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2393 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204764 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204764 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204764 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204764 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204764 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204764 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61356.122449 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61356.122449 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61356.122449 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61356.122449 # average overall miss latency +system.cpu.toL2Bus.respLayer0.occupancy 531250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits +system.cpu.icache.overall_hits::total 1898 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses +system.cpu.icache.overall_misses::total 489 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30301750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30301750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30301750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30301750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30301750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30301750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61966.768916 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61966.768916 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61966.768916 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61966.768916 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -578,48 +578,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 175 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 174 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 174 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 174 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 174 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 174 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 174 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21382000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21382000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21382000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21382000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21382000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21382000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131634 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131634 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131634 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67879.365079 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67879.365079 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67879.365079 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67879.365079 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67879.365079 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67879.365079 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21363250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21363250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21363250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21363250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21363250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21363250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67819.841270 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67819.841270 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.419406 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 159.699673 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 59.719733 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004874 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006696 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -637,17 +637,17 @@ system.cpu.l2cache.demand_misses::total 488 # nu system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21056000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8037000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29093000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5106500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5106500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21056000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13143500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34199500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21056000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13143500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34199500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21037250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7945250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28982500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5109500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5109500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21037250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13054750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34092000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21037250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13054750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34092000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) @@ -670,17 +670,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67057.324841 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79574.257426 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70103.614458 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69952.054795 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69952.054795 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67057.324841 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75537.356322 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70080.942623 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67057.324841 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75537.356322 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70080.942623 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66997.611465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78665.841584 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69837.349398 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69993.150685 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69993.150685 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69860.655738 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69860.655738 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,17 +700,17 @@ system.cpu.l2cache.demand_mshr_misses::total 488 system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17174500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6801500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23976000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4212000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4212000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17174500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11013500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28188000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17174500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11013500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28188000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17080250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6700750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23781000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4208000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4208000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17080250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10908750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27989000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17080250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10908750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27989000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses @@ -722,35 +722,35 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54695.859873 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67341.584158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57773.493976 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57698.630137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57698.630137 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54695.859873 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63295.977011 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57762.295082 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54695.859873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63295.977011 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57762.295082 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54395.700637 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66344.059406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57303.614458 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57643.835616 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57643.835616 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 106.967869 # Cycle average of tags in use -system.cpu.dcache.total_refs 2246 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.908046 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 106.967869 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026115 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026115 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1740 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1740 # number of ReadReq hits +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2246 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2246 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2246 # number of overall hits -system.cpu.dcache.overall_hits::total 2246 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits +system.cpu.dcache.overall_hits::total 2236 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -759,43 +759,43 @@ system.cpu.dcache.demand_misses::cpu.data 529 # n system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses system.cpu.dcache.overall_misses::total 529 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11698500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11698500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21723478 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21723478 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33421978 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33421978 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33421978 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33421978 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1910 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1910 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11600250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11600250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21979228 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21979228 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33579478 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33579478 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33579478 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33579478 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1900 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1900 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2775 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2775 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2775 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2775 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089005 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.089005 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2765 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2765 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2765 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2765 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089474 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.089474 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190631 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190631 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190631 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.190631 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68814.705882 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68814.705882 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60511.080780 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60511.080780 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63179.542533 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63179.542533 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1568 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.191320 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.191320 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191320 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.191320 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68236.764706 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68236.764706 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61223.476323 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61223.476323 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63477.274102 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63477.274102 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1567 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.515152 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.484848 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -815,30 +815,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8145500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8145500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5182500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5182500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13328000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13328000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13328000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13328000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052880 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052880 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8053750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8053750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13239250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13239250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13239250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13239250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053158 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053158 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062703 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062703 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80648.514851 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80648.514851 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70993.150685 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70993.150685 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79740.099010 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79740.099010 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71034.246575 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71034.246575 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index ece7545ec..2ce4c669d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 65088 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use -system.cpu.icache.total_refs 6122 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits @@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -300,15 +300,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use -system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index efc4a5915..07e82d1ad 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11848000 # Number of ticks simulated -final_tick 11848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11933500 # Number of ticks simulated +final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 800 # Simulator instruction rate (inst/s) -host_op_rate 800 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3968846 # Simulator tick rate (ticks/s) -host_mem_usage 226160 # Number of bytes of host memory used -host_seconds 2.99 # Real time elapsed on the host +host_inst_rate 492 # Simulator instruction rate (inst/s) +host_op_rate 492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2461163 # Simulator tick rate (ticks/s) +host_mem_usage 226156 # Number of bytes of host memory used +host_seconds 4.85 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory -system.physmem.bytes_read::total 17408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 17472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory -system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1010128292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 459149223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1469277515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1010128292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1010128292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1010128292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 459149223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1469277515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 272 # Total number of read requests seen +system.physmem.num_reads::total 273 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1008254075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455859555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1464113630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1008254075 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1008254075 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 273 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 17408 # Total number of bytes read from memory +system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 17472 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 17408 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -44,7 +44,7 @@ system.physmem.perBankRdReqs::4 18 # Tr system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 61 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 11758500 # Total gap between requests +system.physmem.totGap 11844000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 272 # Categorize read packet sizes +system.physmem.readPktSize::6 273 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,7 +85,7 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see @@ -164,71 +164,71 @@ system.physmem.bytesPerActivate::768 2 6.06% 93.94% # By system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation -system.physmem.totQLat 1380750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6920750 # Sum of mem lat for all requests -system.physmem.totBusLat 1360000 # Total cycles spent in databus access +system.physmem.totQLat 1190000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6735000 # Sum of mem lat for all requests +system.physmem.totBusLat 1365000 # Total cycles spent in databus access system.physmem.totBankLat 4180000 # Total cycles spent in bank access -system.physmem.avgQLat 5076.29 # Average queueing delay per request -system.physmem.avgBankLat 15367.65 # Average bank access latency per request +system.physmem.avgQLat 4358.97 # Average queueing delay per request +system.physmem.avgBankLat 15311.36 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25443.93 # Average memory access latency -system.physmem.avgRdBW 1469.28 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24670.33 # Average memory access latency +system.physmem.avgRdBW 1464.11 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1469.28 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1464.11 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.48 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.busUtil 11.44 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.56 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 239 # Number of row buffer hits during reads +system.physmem.readRowHits 240 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.87 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43229.78 # Average gap between requests -system.membus.throughput 1469277515 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 248 # Transaction distribution -system.membus.trans_dist::ReadResp 248 # Transaction distribution +system.physmem.avgGap 43384.62 # Average gap between requests +system.membus.throughput 1464113630 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 249 # Transaction distribution +system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 544 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17408 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 546 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17472 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2542750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.5 # Layer utilization (%) -system.cpu.branchPred.lookups 1157 # Number of BP lookups -system.cpu.branchPred.condPredicted 604 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 257 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 791 # Number of BTB lookups -system.cpu.branchPred.BTBHits 240 # Number of BTB hits +system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2554500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.4 # Layer utilization (%) +system.cpu.branchPred.lookups 1175 # Number of BP lookups +system.cpu.branchPred.condPredicted 618 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups +system.cpu.branchPred.BTBHits 253 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.341340 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.467662 # BTB Hit Percentage system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 704 # DTB read hits -system.cpu.dtb.read_misses 28 # DTB read misses +system.cpu.dtb.read_hits 707 # DTB read hits +system.cpu.dtb.read_misses 31 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 732 # DTB read accesses -system.cpu.dtb.write_hits 354 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses +system.cpu.dtb.read_accesses 738 # DTB read accesses +system.cpu.dtb.write_hits 371 # DTB write hits +system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 373 # DTB write accesses -system.cpu.dtb.data_hits 1058 # DTB hits -system.cpu.dtb.data_misses 47 # DTB misses +system.cpu.dtb.write_accesses 391 # DTB write accesses +system.cpu.dtb.data_hits 1078 # DTB hits +system.cpu.dtb.data_misses 51 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1105 # DTB accesses -system.cpu.itb.fetch_hits 1045 # ITB hits +system.cpu.dtb.data_accesses 1129 # DTB accesses +system.cpu.itb.fetch_hits 1067 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1075 # ITB accesses +system.cpu.itb.fetch_accesses 1097 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -242,238 +242,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23697 # number of cpu cycles simulated +system.cpu.numCycles 23868 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4326 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6897 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1157 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 858 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 471 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4327 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7029 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1175 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1212 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1121 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1118 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1045 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.895714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.301681 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 189 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.900807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.307084 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6510 84.55% 84.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 52 0.68% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 117 1.52% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91 1.18% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 172 2.23% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 75 0.97% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 61 0.79% 91.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 67 0.87% 92.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 555 7.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6591 84.47% 84.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.68% 85.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 115 1.47% 86.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.22% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 179 2.29% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 74 0.95% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.82% 91.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.83% 92.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 567 7.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.048825 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.291049 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5567 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 499 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1144 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 485 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 163 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049229 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.294495 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5563 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 577 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1156 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 498 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6120 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 6218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 485 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5671 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1044 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 32 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5812 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4232 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6563 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6551 # Number of integer rename lookups +system.cpu.rename.SquashCycles 498 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5662 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1065 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5911 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4285 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6686 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6674 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2464 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2517 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 948 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 455 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4912 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4973 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4000 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2288 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1369 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4046 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2348 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1391 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7700 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.519481 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.232756 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.518519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.233664 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6104 79.27% 79.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 546 7.09% 86.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 391 5.08% 91.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 259 3.36% 94.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 207 2.69% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 122 1.58% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48 0.62% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15 0.19% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6178 79.17% 79.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 567 7.27% 86.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 400 5.13% 91.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 263 3.37% 94.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 199 2.55% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 121 1.55% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47 0.60% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7803 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 4.55% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19 43.18% 47.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2840 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 778 19.45% 90.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 381 9.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2864 70.79% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 783 19.35% 90.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 398 9.84% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4000 # Type of FU issued -system.cpu.iq.rate 0.168798 # Inst issue rate +system.cpu.iq.FU_type_0::total 4046 # Type of FU issued +system.cpu.iq.rate 0.169516 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011000 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15794 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7204 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3598 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010875 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15980 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7325 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4037 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4083 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 533 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 161 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 177 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 485 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 153 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5240 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 498 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5317 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 948 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 455 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 159 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 212 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3798 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 733 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 202 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 214 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 739 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 191 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 322 # number of nop insts executed -system.cpu.iew.exec_refs 1106 # number of memory reference insts executed -system.cpu.iew.exec_branches 638 # Number of branches executed -system.cpu.iew.exec_stores 373 # Number of stores executed -system.cpu.iew.exec_rate 0.160273 # Inst execution rate -system.cpu.iew.wb_sent 3682 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3604 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1694 # num instructions producing a value -system.cpu.iew.wb_consumers 2179 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1130 # number of memory reference insts executed +system.cpu.iew.exec_branches 644 # Number of branches executed +system.cpu.iew.exec_stores 391 # Number of stores executed +system.cpu.iew.exec_rate 0.161513 # Inst execution rate +system.cpu.iew.wb_sent 3741 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3661 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1709 # num instructions producing a value +system.cpu.iew.wb_consumers 2209 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152087 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.777421 # average fanout of values written-back +system.cpu.iew.wb_rate 0.153385 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.773653 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2655 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2732 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.357034 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.202430 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 7305 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.352635 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.192667 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6348 87.98% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 203 2.81% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 309 4.28% 95.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 113 1.57% 96.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 69 0.96% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 52 0.72% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.46% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22 0.30% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 66 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6436 88.10% 88.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204 2.79% 90.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 308 4.22% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 114 1.56% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 0.99% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 51 0.70% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.44% 98.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 25 0.34% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7305 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -484,93 +484,93 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 66 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12133 # The number of ROB reads -system.cpu.rob.rob_writes 10960 # The number of ROB writes -system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 12303 # The number of ROB reads +system.cpu.rob.rob_writes 11127 # The number of ROB writes +system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16065 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 9.927524 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.927524 # CPI: Total CPI of All Threads -system.cpu.ipc 0.100730 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.100730 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4598 # number of integer regfile reads -system.cpu.int_regfile_writes 2789 # number of integer regfile writes +system.cpu.cpi 9.999162 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.999162 # CPI: Total CPI of All Threads +system.cpu.ipc 0.100008 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.100008 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4674 # number of integer regfile reads +system.cpu.int_regfile_writes 2826 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1469277515 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution +system.cpu.toL2Bus.throughput 1464113630 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 376 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 546 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 12032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 17408 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 17472 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 318000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 91.300481 # Cycle average of tags in use -system.cpu.icache.total_refs 795 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.251337 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 91.300481 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.044580 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.044580 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 795 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 795 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 795 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 795 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 795 # number of overall hits -system.cpu.icache.overall_hits::total 795 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses -system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16821499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16821499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16821499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16821499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16821499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16821499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1045 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1045 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1045 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1045 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1045 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1045 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239234 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.239234 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.239234 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.239234 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.239234 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.239234 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67285.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67285.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67285.996000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67285.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67285.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67285.996000 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 816 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 816 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 816 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 816 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 816 # number of overall hits +system.cpu.icache.overall_hits::total 816 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 251 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 251 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 251 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 251 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 251 # number of overall misses +system.cpu.icache.overall_misses::total 251 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16843749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16843749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16843749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16843749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16843749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16843749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235239 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.235239 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.235239 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.235239 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.235239 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.235239 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67106.569721 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67106.569721 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67106.569721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67106.569721 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -580,75 +580,75 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 63 system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12837999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12837999 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.176195 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68062.494681 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68062.494681 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 119.633346 # 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Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002799 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000860 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 248 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 249 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 188 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 273 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -660,17 +660,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67647.058824 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74545.081967 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68892.570281 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71697.916667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71697.916667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69139.194139 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69139.194139 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -679,28 +679,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 248 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56354.417671 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59385.416667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59385.416667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 44.834743 # Cycle average of tags in use -system.cpu.dcache.total_refs 761 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.952941 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 44.834743 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.010946 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.010946 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 548 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 548 # number of ReadReq hits +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 761 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 761 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 761 # number of overall hits -system.cpu.dcache.overall_hits::total 761 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 109 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 109 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 758 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 758 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 758 # number of overall hits +system.cpu.dcache.overall_hits::total 758 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses -system.cpu.dcache.overall_misses::total 190 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7852000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7852000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5307500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5307500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13159500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13159500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13159500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13159500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 657 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 657 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 194 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 194 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 194 # number of overall misses +system.cpu.dcache.overall_misses::total 194 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7467750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7467750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5336000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5336000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12803750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12803750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12803750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12803750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 658 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 951 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 951 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 951 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 951 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.165906 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.165906 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 952 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 952 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 952 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 952 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.171733 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.171733 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.199790 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.199790 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.199790 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.199790 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72036.697248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72036.697248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65524.691358 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65524.691358 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69260.526316 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69260.526316 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69260.526316 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69260.526316 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 144 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.203782 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.203782 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.203782 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.203782 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66086.283186 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66086.283186 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65876.543210 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65876.543210 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65998.711340 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65998.711340 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 48 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 105 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 105 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 105 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 109 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 109 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 109 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -805,30 +805,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4662500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4662500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1739500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1739500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6402000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6402000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092846 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092846 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4608250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4608250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1746250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1746250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6354500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6354500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6354500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6354500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092705 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092705 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089380 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.089380 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089380 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.089380 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76434.426230 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76434.426230 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72479.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72479.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75317.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75317.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75317.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75317.647059 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.089286 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.089286 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75545.081967 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75545.081967 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72760.416667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72760.416667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index cb629b252..034aea3e9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 33048 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 80.050296 # Cycle average of tags in use -system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 107.162861 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses @@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use -system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 6938f2714..22dbcae6d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16387000 # Number of ticks simulated -final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16494000 # Number of ticks simulated +final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31359 # Simulator instruction rate (inst/s) -host_op_rate 39125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111893890 # Simulator tick rate (ticks/s) -host_mem_usage 244352 # Number of bytes of host memory used +host_inst_rate 31208 # Simulator instruction rate (inst/s) +host_op_rate 38937 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 112083077 # Simulator tick rate (ticks/s) +host_mem_usage 244336 # Number of bytes of host memory used host_seconds 0.15 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17344 # Nu system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 393 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16329500 # Total gap between requests +system.physmem.totGap 16436500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # By system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2029000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests +system.physmem.totQLat 2047500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5472500 # Total cycles spent in bank access -system.physmem.avgQLat 5162.85 # Average queueing delay per request -system.physmem.avgBankLat 13924.94 # Average bank access latency per request +system.physmem.totBankLat 5445000 # Total cycles spent in bank access +system.physmem.avgQLat 5209.92 # Average queueing delay per request +system.physmem.avgBankLat 13854.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24087.79 # Average memory access latency -system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24064.89 # Average memory access latency +system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.busUtil 11.91 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41550.89 # Average gap between requests -system.membus.throughput 1534875206 # Throughput (bytes/s) +system.physmem.avgGap 41823.16 # Average gap between requests +system.membus.throughput 1524918152 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 352 # Transaction distribution system.membus.trans_dist::ReadResp 352 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution @@ -200,18 +200,18 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 25152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.4 # Layer utilization (%) -system.cpu.branchPred.lookups 2471 # Number of BP lookups -system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.3 # Layer utilization (%) +system.cpu.branchPred.lookups 2479 # Number of BP lookups +system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups -system.cpu.branchPred.BTBHits 695 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses @@ -301,129 +301,129 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 32775 # number of cpu cycles simulated +system.cpu.numCycles 32989 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2415 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2420 # Number of cycles decode is running system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2217 # Number of cycles rename is running +system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2221 # Number of cycles rename is running system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56202 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued @@ -452,84 +452,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.272189 # Inst issue rate -system.cpu.iq.fu_busy_cnt 223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8917 # Type of FU issued +system.cpu.iq.rate 0.270302 # Inst issue rate +system.cpu.iq.fu_busy_cnt 222 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3294 # number of memory reference insts executed -system.cpu.iew.exec_branches 1436 # Number of branches executed +system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.259863 # Inst execution rate +system.cpu.iew.exec_rate 0.258268 # Inst execution rate system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3885 # num instructions producing a value -system.cpu.iew.wb_consumers 7780 # num instructions consuming a value +system.cpu.iew.wb_count 8067 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3881 # num instructions producing a value +system.cpu.iew.wb_consumers 7779 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back +system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -542,23 +542,23 @@ system.cpu.commit.int_insts 4976 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23312 # The number of ROB reads -system.cpu.rob.rob_writes 23396 # The number of ROB writes -system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23271 # The number of ROB reads +system.cpu.rob.rob_writes 23399 # The number of ROB writes +system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads -system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39187 # number of integer regfile reads -system.cpu.int_regfile_writes 7985 # number of integer regfile writes +system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads +system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39193 # number of integer regfile reads +system.cpu.int_regfile_writes 7983 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2976 # number of misc regfile reads +system.cpu.misc_regfile_reads 2975 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution @@ -573,60 +573,60 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use -system.cpu.icache.total_refs 1578 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits -system.cpu.icache.overall_hits::total 1578 # number of overall hits +system.cpu.icache.tags.replacements 4 # number of replacements +system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits +system.cpu.icache.overall_hits::total 1583 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -642,36 +642,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # 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Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.113636 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 137.046036 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.393454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004182 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001416 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005598 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -692,17 +692,17 @@ system.cpu.l2cache.demand_misses::total 398 # nu system.cpu.l2cache.overall_misses::cpu.inst 271 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22187500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses @@ -783,39 +783,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54582.103321 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.937637 # Cycle average of tags in use -system.cpu.dcache.total_refs 2388 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.356164 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.937637 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020981 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020981 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1760 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1760 # number of ReadReq hits +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2366 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2366 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2366 # number of overall hits -system.cpu.dcache.overall_hits::total 2366 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits +system.cpu.dcache.overall_hits::total 2369 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses @@ -826,53 +826,53 @@ system.cpu.dcache.demand_misses::cpu.data 497 # n system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10638500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10638500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19663000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19663000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 127500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30301500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30301500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30301500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30301500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -894,30 +894,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 42ebdbb61..3ccfc050f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16387000 # Number of ticks simulated -final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16494000 # Number of ticks simulated +final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36614 # Simulator instruction rate (inst/s) -host_op_rate 45680 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 130634561 # Simulator tick rate (ticks/s) -host_mem_usage 244344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 66928 # Simulator instruction rate (inst/s) +host_op_rate 83502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 240363471 # Simulator tick rate (ticks/s) +host_mem_usage 244336 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17344 # Nu system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 393 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16329500 # Total gap between requests +system.physmem.totGap 16436500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # By system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2029000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests +system.physmem.totQLat 2047500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5472500 # Total cycles spent in bank access -system.physmem.avgQLat 5162.85 # Average queueing delay per request -system.physmem.avgBankLat 13924.94 # Average bank access latency per request +system.physmem.totBankLat 5445000 # Total cycles spent in bank access +system.physmem.avgQLat 5209.92 # Average queueing delay per request +system.physmem.avgBankLat 13854.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24087.79 # Average memory access latency -system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24064.89 # Average memory access latency +system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.busUtil 11.91 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41550.89 # Average gap between requests -system.membus.throughput 1534875206 # Throughput (bytes/s) +system.physmem.avgGap 41823.16 # Average gap between requests +system.membus.throughput 1524918152 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 352 # Transaction distribution system.membus.trans_dist::ReadResp 352 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution @@ -200,18 +200,18 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 25152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.4 # Layer utilization (%) -system.cpu.branchPred.lookups 2471 # Number of BP lookups -system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.3 # Layer utilization (%) +system.cpu.branchPred.lookups 2479 # Number of BP lookups +system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups -system.cpu.branchPred.BTBHits 695 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -256,129 +256,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32775 # number of cpu cycles simulated +system.cpu.numCycles 32989 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2415 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2420 # Number of cycles decode is running system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2217 # Number of cycles rename is running +system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2221 # Number of cycles rename is running system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56202 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued @@ -407,84 +407,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.272189 # Inst issue rate -system.cpu.iq.fu_busy_cnt 223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8917 # Type of FU issued +system.cpu.iq.rate 0.270302 # Inst issue rate +system.cpu.iq.fu_busy_cnt 222 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3294 # number of memory reference insts executed -system.cpu.iew.exec_branches 1436 # Number of branches executed +system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.259863 # Inst execution rate +system.cpu.iew.exec_rate 0.258268 # Inst execution rate system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3885 # num instructions producing a value -system.cpu.iew.wb_consumers 7780 # num instructions consuming a value +system.cpu.iew.wb_count 8067 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3881 # num instructions producing a value +system.cpu.iew.wb_consumers 7779 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back +system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -497,23 +497,23 @@ system.cpu.commit.int_insts 4976 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23312 # The number of ROB reads -system.cpu.rob.rob_writes 23396 # The number of ROB writes -system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23271 # The number of ROB reads +system.cpu.rob.rob_writes 23399 # The number of ROB writes +system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads -system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39187 # number of integer regfile reads -system.cpu.int_regfile_writes 7985 # number of integer regfile writes +system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads +system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39193 # number of integer regfile reads +system.cpu.int_regfile_writes 7983 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2976 # number of misc regfile reads +system.cpu.misc_regfile_reads 2975 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution @@ -528,60 +528,60 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use -system.cpu.icache.total_refs 1578 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits -system.cpu.icache.overall_hits::total 1578 # number of overall hits +system.cpu.icache.tags.replacements 4 # number of replacements +system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits +system.cpu.icache.overall_hits::total 1583 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -597,36 +597,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18642000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18642000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18642000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18642000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18642000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18642000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149846 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149846 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149846 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64061.855670 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64061.855670 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 183.439490 # Cycle average of tags in use -system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.113636 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 137.046036 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.393454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004182 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001416 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005598 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -647,17 +647,17 @@ system.cpu.l2cache.demand_misses::total 398 # nu system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 398 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18145000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6188500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24333500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2992500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2992500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18145000 # 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mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses @@ -738,39 +738,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54582.103321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60561.728395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55958.096591 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60737.804878 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60737.804878 # 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Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.356164 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.937637 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020981 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020981 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1760 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1760 # number of ReadReq hits +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # 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n system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10638500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10638500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19663000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19663000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 127500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30301500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30301500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30301500 # 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number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -849,30 +849,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 744017c0b..7a58b161f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 51938 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 114.614391 # Cycle average of tags in use -system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.055964 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits @@ -185,17 +185,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use -system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004702 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits @@ -313,15 +313,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use -system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 4cccc3a14..b2a150376 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24539000 # Number of ticks simulated -final_tick 24539000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24587000 # Number of ticks simulated +final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40560 # Simulator instruction rate (inst/s) -host_op_rate 40552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171130571 # Simulator tick rate (ticks/s) -host_mem_usage 226208 # Number of bytes of host memory used +host_inst_rate 41260 # Simulator instruction rate (inst/s) +host_op_rate 41253 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174426700 # Simulator tick rate (ticks/s) +host_mem_usage 226212 # Number of bytes of host memory used host_seconds 0.14 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 826765557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359916867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1186682424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 826765557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 826765557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 826765557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359916867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1186682424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 825151503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 359214219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1184365722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 825151503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 825151503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24472000 # Total gap between requests +system.physmem.totGap 24519000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::960 1 1.06% 97.87% # By system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation -system.physmem.totQLat 2632000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13115750 # Sum of mem lat for all requests +system.physmem.totQLat 2305250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12775250 # Sum of mem lat for all requests system.physmem.totBusLat 2275000 # Total cycles spent in databus access -system.physmem.totBankLat 8208750 # Total cycles spent in bank access -system.physmem.avgQLat 5784.62 # Average queueing delay per request -system.physmem.avgBankLat 18041.21 # Average bank access latency per request +system.physmem.totBankLat 8195000 # Total cycles spent in bank access +system.physmem.avgQLat 5066.48 # Average queueing delay per request +system.physmem.avgBankLat 18010.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28825.82 # Average memory access latency -system.physmem.avgRdBW 1186.68 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28077.47 # Average memory access latency +system.physmem.avgRdBW 1184.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1186.68 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1184.37 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.27 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.53 # Average read queue length over time +system.physmem.busUtil 9.25 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.52 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 361 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53784.62 # Average gap between requests -system.membus.throughput 1186682424 # Throughput (bytes/s) +system.physmem.avgGap 53887.91 # Average gap between requests +system.membus.throughput 1184365722 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -201,9 +201,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120 system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29120 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4265750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4266000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 17.4 # Layer utilization (%) system.cpu.branchPred.lookups 1157 # Number of BP lookups system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted @@ -233,7 +233,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 49079 # number of cpu cycles simulated +system.cpu.numCycles 49175 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). @@ -255,12 +255,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9516 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 488 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43696 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 43792 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.968031 # Percentage of cycles cpu is active +system.cpu.activity 10.946619 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -272,36 +272,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 8.441520 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.458032 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.441520 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118462 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.458032 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118231 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.118462 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45429 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.118231 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45525 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.436989 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46265 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 7.422471 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46361 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.733613 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46314 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 5.722420 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46410 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.633774 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47841 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 5.622776 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47937 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.522464 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46189 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.517539 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.888466 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 150.599216 # Cycle average of tags in use -system.cpu.icache.total_refs 428 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 150.599216 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073535 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073535 # Average percentage of cache occupancy +system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 13 # number of replacements +system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -314,12 +314,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25149500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25149500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25149500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25149500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25149500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25149500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25010250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25010250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25010250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25010250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25010250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25010250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -332,12 +332,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71855.714286 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71855.714286 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71855.714286 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71855.714286 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71457.857143 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71457.857143 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71457.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71457.857143 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -358,26 +358,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22969000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22969000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22969000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22969000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22969000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22969000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22679000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22679000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22679000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22679000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22679000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22679000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72003.134796 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72003.134796 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71094.043887 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71094.043887 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1191898610 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1189571725 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -392,21 +392,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 208.333773 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 152.278645 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.055128 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006358 # Average percentage of cache occupancy +system.cpu.toL2Bus.respLayer0.occupancy 543000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -424,17 +424,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22623500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6716000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29339500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3640500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3640500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22623500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10356500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32980000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22623500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10356500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32980000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22333500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6742000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29075500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3650000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3650000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22333500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10392000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32725500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22333500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10392000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32725500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -457,17 +457,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71367.507886 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77195.402299 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72622.524752 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71382.352941 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71382.352941 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71367.507886 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75047.101449 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72483.516484 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71367.507886 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75047.101449 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72483.516484 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70452.681388 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77494.252874 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71969.059406 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71568.627451 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71568.627451 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71924.175824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71924.175824 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,17 +487,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18696000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5647250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24343250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18342000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5661000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24003000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18696000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8653250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27349250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18696000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8653250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27349250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18342000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8667000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27009000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18342000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8667000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27009000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -509,51 +509,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58977.917981 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64910.919540 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60255.569307 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57861.198738 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59413.366337 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 90.129103 # Cycle average of tags in use -system.cpu.dcache.total_refs 1637 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.862319 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 90.129103 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022004 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022004 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1065 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1065 # number of ReadReq hits +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1637 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1637 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1637 # number of overall hits -system.cpu.dcache.overall_hits::total 1637 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1638 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1638 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1638 # number of overall hits +system.cpu.dcache.overall_hits::total 1638 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 451 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 451 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 451 # number of overall misses -system.cpu.dcache.overall_misses::total 451 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7478500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7478500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21383500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21383500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28862000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28862000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28862000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28862000 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 450 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses +system.cpu.dcache.overall_misses::total 450 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7523000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7523000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21590750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21590750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29113750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29113750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29113750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29113750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -562,38 +562,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2088 # system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084265 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.084265 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083405 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083405 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.215996 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.215996 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.215996 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.215996 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76311.224490 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76311.224490 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60576.487252 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60576.487252 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63995.565410 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63995.565410 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 253 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77556.701031 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77556.701031 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61163.597734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61163.597734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64697.222222 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64697.222222 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.461538 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 313 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 313 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 312 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 312 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -602,14 +602,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6809500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6809500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3694500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3694500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10504000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10504000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10504000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10504000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3704000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3704000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10539500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10539500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10539500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10539500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -618,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78270.114943 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78270.114943 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72441.176471 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72441.176471 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78568.965517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78568.965517 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72627.450980 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72627.450980 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 37ca97b46..6a930873f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21759500 # Number of ticks simulated -final_tick 21759500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21805500 # Number of ticks simulated +final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43168 # Simulator instruction rate (inst/s) -host_op_rate 43158 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 182102261 # Simulator tick rate (ticks/s) -host_mem_usage 228268 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 79844 # Simulator instruction rate (inst/s) +host_op_rate 79828 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 337538221 # Simulator tick rate (ticks/s) +host_mem_usage 228256 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 30592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 478 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 988258002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 417656656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1405914658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 988258002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 988258002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 988258002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 417656656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1405914658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 478 # Total number of read requests seen +system.physmem.num_reads::total 477 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 983238174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 416775584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1400013758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 983238174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 983238174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 477 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30592 # Total number of bytes read from memory +system.physmem.cpureqs 477 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30528 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -44,7 +44,7 @@ system.physmem.perBankRdReqs::4 7 # Tr system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 63 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 21680500 # Total gap between requests +system.physmem.totGap 21726000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 478 # Categorize read packet sizes +system.physmem.readPktSize::6 477 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,9 +85,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -150,16 +150,16 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.330097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.624939 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.862985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 241.708738 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.390708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.503517 # Bytes accessed per row activation system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2 1.94% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 4 3.88% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.91% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3 2.91% 88.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation @@ -168,51 +168,51 @@ system.physmem.bytesPerActivate::960 1 0.97% 97.09% # By system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 2435500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13501750 # Sum of mem lat for all requests -system.physmem.totBusLat 2390000 # Total cycles spent in databus access +system.physmem.totQLat 2353250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13414500 # Sum of mem lat for all requests +system.physmem.totBusLat 2385000 # Total cycles spent in databus access system.physmem.totBankLat 8676250 # Total cycles spent in bank access -system.physmem.avgQLat 5095.19 # Average queueing delay per request -system.physmem.avgBankLat 18151.15 # Average bank access latency per request +system.physmem.avgQLat 4933.44 # Average queueing delay per request +system.physmem.avgBankLat 18189.20 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28246.34 # Average memory access latency -system.physmem.avgRdBW 1405.91 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28122.64 # Average memory access latency +system.physmem.avgRdBW 1400.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1405.91 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1400.01 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.98 # Data bus utilization in percentage +system.physmem.busUtil 10.94 # Data bus utilization in percentage system.physmem.avgRdQLen 0.62 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 375 # Number of row buffer hits during reads +system.physmem.readRowHits 374 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.45 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45356.69 # Average gap between requests -system.membus.throughput 1405914658 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 427 # Transaction distribution -system.membus.trans_dist::ReadResp 427 # Transaction distribution +system.physmem.avgGap 45547.17 # Average gap between requests +system.membus.throughput 1400013758 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 426 # Transaction distribution +system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 956 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 956 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 30592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30592 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 954 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 954 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 30528 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 590000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4475750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.6 # Layer utilization (%) -system.cpu.branchPred.lookups 2196 # Number of BP lookups -system.cpu.branchPred.condPredicted 1494 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4480000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.5 # Layer utilization (%) +system.cpu.branchPred.lookups 2187 # Number of BP lookups +system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1671 # Number of BTB lookups -system.cpu.branchPred.BTBHits 505 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1664 # Number of BTB lookups +system.cpu.branchPred.BTBHits 502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.221424 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 262 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 30.168269 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -232,132 +232,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43520 # number of cpu cycles simulated +system.cpu.numCycles 43612 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8865 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13232 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 767 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3240 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1388 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1327 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8859 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13212 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2187 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3230 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1384 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1326 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.912867 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.222713 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1985 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.912746 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.223376 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11255 77.65% 77.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1338 9.23% 86.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11245 77.69% 77.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1331 9.20% 86.88% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 132 0.91% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 307 2.12% 90.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.81% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 149 1.03% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.09% 93.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 934 6.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 131 0.91% 88.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.11% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 118 0.82% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 150 1.04% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 933 6.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050460 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.304044 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8953 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1558 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3054 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.050147 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.302944 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8926 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1578 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3043 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 877 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12351 # Number of instructions handled by decode +system.cpu.decode.SquashCycles 875 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12329 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 877 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9138 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 511 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 897 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2924 # Number of cycles rename is running +system.cpu.rename.SquashCycles 875 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9108 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 901 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2916 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11915 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11899 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7195 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14132 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14128 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 7186 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14116 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14112 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3797 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2463 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3788 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 16 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2460 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9226 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8313 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3584 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8306 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3428 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2082 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.573508 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.239818 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.573817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.241522 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10895 75.16% 75.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1434 9.89% 85.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 892 6.15% 91.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 557 3.84% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 358 2.47% 97.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 226 1.56% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 86 0.59% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10881 75.17% 75.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1431 9.89% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 893 6.17% 91.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 3.82% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 356 2.46% 97.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 225 1.55% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 88 0.61% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14475 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 100 62.89% 66.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4947 59.51% 59.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4943 59.51% 59.51% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.60% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2253 27.10% 86.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 13.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2250 27.09% 86.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8313 # Type of FU issued -system.cpu.iq.rate 0.191016 # Inst issue rate -system.cpu.iq.fu_busy_cnt 159 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019127 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31318 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12850 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8306 # Type of FU issued +system.cpu.iq.rate 0.190452 # Inst issue rate +system.cpu.iq.fu_busy_cnt 160 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019263 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31282 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12675 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7463 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8470 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8464 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1300 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1297 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 35 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 877 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 334 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10786 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2463 # Number of dispatched load instructions +system.cpu.iew.iewSquashCycles 875 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10763 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2460 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 102 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 461 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2118 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 377 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7925 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1529 # number of nop insts executed -system.cpu.iew.exec_refs 3196 # number of memory reference insts executed -system.cpu.iew.exec_branches 1356 # Number of branches executed -system.cpu.iew.exec_stores 1078 # Number of stores executed -system.cpu.iew.exec_rate 0.182353 # Inst execution rate -system.cpu.iew.wb_sent 7562 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7469 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2922 # num instructions producing a value -system.cpu.iew.wb_consumers 4200 # num instructions consuming a value +system.cpu.iew.exec_nop 1525 # number of nop insts executed +system.cpu.iew.exec_refs 3189 # number of memory reference insts executed +system.cpu.iew.exec_branches 1354 # Number of branches executed +system.cpu.iew.exec_stores 1079 # Number of stores executed +system.cpu.iew.exec_rate 0.181716 # Inst execution rate +system.cpu.iew.wb_sent 7555 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7465 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2921 # num instructions producing a value +system.cpu.iew.wb_consumers 4197 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.171622 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.695714 # average fanout of values written-back +system.cpu.iew.wb_rate 0.171168 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4965 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4943 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13618 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.426862 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.205287 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13600 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.427426 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.207995 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11210 82.32% 82.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1002 7.36% 89.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 633 4.65% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 319 2.34% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 147 1.08% 97.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 94 0.69% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.49% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.29% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11198 82.34% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 7.35% 89.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 630 4.63% 94.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 315 2.32% 96.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 149 1.10% 97.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13618 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13600 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,197 +474,197 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24277 # The number of ROB reads -system.cpu.rob.rob_writes 22442 # The number of ROB writes -system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24237 # The number of ROB reads +system.cpu.rob.rob_writes 22398 # The number of ROB writes +system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29137 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 8.440652 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.440652 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118474 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.118474 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10757 # number of integer regfile reads -system.cpu.int_regfile_writes 5239 # number of integer regfile writes +system.cpu.cpi 8.458495 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.458495 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118224 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.118224 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10746 # number of integer regfile reads +system.cpu.int_regfile_writes 5233 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1414738390 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 430 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution +system.cpu.toL2Bus.throughput 1408818876 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 676 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 30784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 30784 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size 30720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 508500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.130962 # Cycle average of tags in use -system.cpu.icache.total_refs 1541 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.545723 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.130962 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078677 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078677 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1541 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1541 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1541 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1541 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1541 # number of overall hits -system.cpu.icache.overall_hits::total 1541 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses -system.cpu.icache.overall_misses::total 453 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30806000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30806000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30806000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30806000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30806000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30806000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1994 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1994 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1994 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1994 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1994 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227182 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.227182 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.227182 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.227182 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.227182 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.227182 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68004.415011 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68004.415011 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68004.415011 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68004.415011 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68004.415011 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68004.415011 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 46 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer0.occupancy 573500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.icache.tags.replacements 17 # number of replacements +system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1531 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1531 # number of overall hits +system.cpu.icache.overall_hits::total 1531 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses +system.cpu.icache.overall_misses::total 454 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31019250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31019250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31019250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31019250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31019250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31019250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1985 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1985 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1985 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1985 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1985 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228715 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.228715 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.228715 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.228715 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.228715 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.228715 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68324.339207 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68324.339207 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68324.339207 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68324.339207 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 114 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 114 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 114 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 114 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 114 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23945500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23945500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23945500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23945500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23945500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23945500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170010 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170010 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170010 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.170010 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170010 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.170010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70635.693215 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70635.693215 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70635.693215 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70635.693215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70635.693215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70635.693215 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23858000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23858000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23858000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23858000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23858000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23858000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170277 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.170277 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.170277 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70585.798817 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70585.798817 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.094003 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 427 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.007026 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 163.410737 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.683266 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004987 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006747 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # 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number of overall misses +system.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.l2cache.overall_misses::total 478 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23576500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7069500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30646000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3844000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3844000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23576500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10913500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34490000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23576500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10913500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34490000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 477 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23490000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7101750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30591750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3862250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3862250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23490000 # 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miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69209.459459 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69209.459459 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63062.842541 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63062.842541 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64846.566667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64846.566667 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.727273 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -799,30 +799,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7164000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7164000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3895999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3895999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11059999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11059999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11059999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11059999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045821 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045821 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7196250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7196250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3914249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3914249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11110499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11110499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11110499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11110499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048780 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048780 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78725.274725 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78725.274725 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76392.137255 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76392.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79079.670330 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79079.670330 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76749.980392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76749.980392 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 0d57ed336..bfb8470a6 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -83,15 +83,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 63266 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 132.545353 # Cycle average of tags in use -system.cpu.icache.total_refs 5513 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18.194719 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.064719 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13 # number of replacements +system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits @@ -161,17 +161,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.114191 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -286,15 +286,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.492114 # Cycle average of tags in use -system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 43017685d..50311c18c 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18326500 # Number of ticks simulated -final_tick 18326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18469500 # Number of ticks simulated +final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41507 # Simulator instruction rate (inst/s) -host_op_rate 41499 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131284333 # Simulator tick rate (ticks/s) -host_mem_usage 224304 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 54927 # Simulator instruction rate (inst/s) +host_op_rate 54916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 175080000 # Simulator tick rate (ticks/s) +host_mem_usage 224296 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1204812703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 352713284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1557525987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1204812703 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1204812703 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1204812703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 352713284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1557525987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1195484447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 349982403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1545466851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1195484447 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1195484447 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 446 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18199000 # Total gap between requests +system.physmem.totGap 18341000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # By system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation -system.physmem.totQLat 2004500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10972000 # Sum of mem lat for all requests +system.physmem.totQLat 1996500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10991500 # Sum of mem lat for all requests system.physmem.totBusLat 2230000 # Total cycles spent in databus access -system.physmem.totBankLat 6737500 # Total cycles spent in bank access -system.physmem.avgQLat 4494.39 # Average queueing delay per request -system.physmem.avgBankLat 15106.50 # Average bank access latency per request +system.physmem.totBankLat 6765000 # Total cycles spent in bank access +system.physmem.avgQLat 4476.46 # Average queueing delay per request +system.physmem.avgBankLat 15168.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24600.90 # Average memory access latency -system.physmem.avgRdBW 1557.53 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24644.62 # Average memory access latency +system.physmem.avgRdBW 1545.47 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1557.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1545.47 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.17 # Data bus utilization in percentage +system.physmem.busUtil 12.07 # Data bus utilization in percentage system.physmem.avgRdQLen 0.60 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 380 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40804.93 # Average gap between requests -system.membus.throughput 1557525987 # Throughput (bytes/s) +system.physmem.avgGap 41123.32 # Average gap between requests +system.membus.throughput 1545466851 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -201,10 +201,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 559500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4174500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.7 # Layer utilization (%) system.cpu.branchPred.lookups 2238 # Number of BP lookups system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect @@ -233,92 +233,92 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 36654 # number of cpu cycles simulated +system.cpu.numCycles 36940 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7507 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13158 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 7468 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1292 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched +system.cpu.fetch.Cycles 2263 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.109724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.526984 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 11808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.114583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.531247 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9595 80.92% 80.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 1.50% 82.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.48% 83.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 141 1.19% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.91% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 133 1.12% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.17% 90.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.93% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1040 8.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9545 80.84% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 1.51% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.49% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.20% 85.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.92% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.13% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.18% 90.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.061057 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.358979 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7580 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1390 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2096 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 710 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 11808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.060585 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.356280 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7545 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2098 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11719 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 710 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7768 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 673 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1984 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 273 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11300 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 232 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9692 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18178 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18123 # Number of integer rename lookups +system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7731 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1987 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11308 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 226 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9701 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18192 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18137 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4694 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4703 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 575 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10310 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4245 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3499 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4250 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11857 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.750864 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.481785 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.753980 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.485434 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8486 71.57% 71.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1113 9.39% 80.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.65% 87.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 496 4.18% 91.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 461 3.89% 95.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 303 2.56% 98.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 131 1.10% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8446 71.53% 71.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1102 9.33% 80.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 787 6.66% 87.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 501 4.24% 91.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 457 3.87% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 305 2.58% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11857 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11808 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available @@ -388,10 +388,10 @@ system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8903 # Type of FU issued -system.cpu.iq.rate 0.242893 # Inst issue rate +system.cpu.iq.rate 0.241012 # Inst issue rate system.cpu.iq.fu_busy_cnt 171 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30013 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 29964 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads @@ -408,12 +408,12 @@ system.cpu.iew.lsq.thread0.squashedStores 785 # N system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 710 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 456 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 457 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10367 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10362 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions @@ -432,35 +432,35 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3201 # number of memory reference insts executed system.cpu.iew.exec_branches 1351 # Number of branches executed system.cpu.iew.exec_stores 1523 # Number of stores executed -system.cpu.iew.exec_rate 0.231953 # Inst execution rate +system.cpu.iew.exec_rate 0.230157 # Inst execution rate system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8157 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4222 # num instructions producing a value -system.cpu.iew.wb_consumers 6684 # num instructions consuming a value +system.cpu.iew.wb_producers 4221 # num instructions producing a value +system.cpu.iew.wb_consumers 6683 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.222541 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631658 # average fanout of values written-back +system.cpu.iew.wb_rate 0.220818 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631603 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4581 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11147 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.519602 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.320329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.323963 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8765 78.63% 78.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1011 9.07% 87.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 612 5.49% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 265 2.38% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.53% 97.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 71 0.64% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.39% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8724 78.60% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1004 9.05% 87.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 606 5.46% 93.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 271 2.44% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.97% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 70 0.63% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.41% 99.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11147 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11099 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -473,22 +473,22 @@ system.cpu.commit.int_insts 5698 # Nu system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21419 # The number of ROB reads -system.cpu.rob.rob_writes 21457 # The number of ROB writes -system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24797 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21366 # The number of ROB reads +system.cpu.rob.rob_writes 21446 # The number of ROB writes +system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25132 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 6.328384 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.328384 # CPI: Total CPI of All Threads -system.cpu.ipc 0.158018 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.158018 # IPC: Total IPC of All Threads +system.cpu.cpi 6.377762 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.377762 # CPI: Total CPI of All Threads +system.cpu.ipc 0.156795 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.156795 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 13474 # number of integer regfile reads system.cpu.int_regfile_writes 7049 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1581971462 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1569723057 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -503,60 +503,60 @@ system.cpu.toL2Bus.data_through_bus 28992 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 526500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 167.412828 # Cycle average of tags in use -system.cpu.icache.total_refs 1371 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.905983 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 167.412828 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.081745 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.081745 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1371 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1371 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1371 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1371 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1371 # number of overall hits -system.cpu.icache.overall_hits::total 1371 # number of overall hits +system.cpu.toL2Bus.respLayer0.occupancy 590750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1372 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1372 # number of overall hits +system.cpu.icache.overall_hits::total 1372 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 442 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 442 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 442 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses system.cpu.icache.overall_misses::total 442 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28629500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28629500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28629500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28629500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28629500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28629500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243795 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.243795 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65424.208145 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 70.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.166667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -572,36 +572,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351 system.cpu.icache.demand_mshr_misses::total 351 # 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Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 166.296629 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.279092 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005075 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000955 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006030 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 399 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18694250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6525500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25219750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -707,51 +707,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54115.942029 # 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average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54186.231884 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64180.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55538.847118 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65101.063830 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65101.063830 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.158434 # Cycle average of tags in use -system.cpu.dcache.total_refs 2188 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.450980 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.158434 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015420 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015420 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits -system.cpu.dcache.overall_hits::total 2188 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2192 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2192 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2192 # number of overall hits +system.cpu.dcache.overall_hits::total 2192 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses -system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7358500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7358500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19767997 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19767997 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27126497 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27126497 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27126497 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27126497 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 431 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 431 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 431 # number of overall misses +system.cpu.dcache.overall_misses::total 431 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7388000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7388000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19896996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19896996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27284996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27284996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27284996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27284996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -762,36 +762,36 @@ system.cpu.dcache.overall_accesses::cpu.data 2623 system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.807692 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.807692 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59722.045317 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59722.045317 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62359.763218 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62359.763218 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.164316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164316 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164316 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164316 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71038.461538 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71038.461538 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60847.082569 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60847.082569 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63306.255220 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63306.255220 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 100 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -800,14 +800,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4188500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4188500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7865499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7865499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7865499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7865499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4197750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4197750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3687248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3687248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7884998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7884998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7884998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7884998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -816,14 +816,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76154.545455 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76154.545455 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78234.021277 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78234.021277 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76322.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76322.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 45ae1e677..6e991864c 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20764500 # Number of ticks simulated -final_tick 20764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20802500 # Number of ticks simulated +final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44697 # Simulator instruction rate (inst/s) -host_op_rate 44687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174155494 # Simulator tick rate (ticks/s) -host_mem_usage 232524 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 39959 # Simulator instruction rate (inst/s) +host_op_rate 39952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 155990706 # Simulator tick rate (ticks/s) +host_mem_usage 232536 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 890751041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 413012594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1303763635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 890751041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 890751041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 890751041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 413012594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1303763635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 889123903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 412258142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1301382045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 889123903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 889123903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20696000 # Total gap between requests +system.physmem.totGap 20733000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,9 +85,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 252 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # By system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation -system.physmem.totQLat 3131250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11791250 # Sum of mem lat for all requests +system.physmem.totQLat 2859500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11464500 # Sum of mem lat for all requests system.physmem.totBusLat 2115000 # Total cycles spent in databus access -system.physmem.totBankLat 6545000 # Total cycles spent in bank access -system.physmem.avgQLat 7402.48 # Average queueing delay per request -system.physmem.avgBankLat 15472.81 # Average bank access latency per request +system.physmem.totBankLat 6490000 # Total cycles spent in bank access +system.physmem.avgQLat 6760.05 # Average queueing delay per request +system.physmem.avgBankLat 15342.79 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27875.30 # Average memory access latency -system.physmem.avgRdBW 1303.76 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27102.84 # Average memory access latency +system.physmem.avgRdBW 1301.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1303.76 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1301.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.19 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time +system.physmem.busUtil 10.17 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.55 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48926.71 # Average gap between requests -system.membus.throughput 1303763635 # Throughput (bytes/s) +system.physmem.avgGap 49014.18 # Average gap between requests +system.membus.throughput 1301382045 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution @@ -201,10 +201,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072 system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 27072 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3936500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3938750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.9 # Layer utilization (%) system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -215,7 +215,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41530 # number of cpu cycles simulated +system.cpu.numCycles 41606 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -237,12 +237,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9717 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9660 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35284 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6246 # Number of cycles cpu stages are processed. -system.cpu.activity 15.039730 # Percentage of cycles cpu is active +system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35361 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. +system.cpu.activity 15.009854 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -254,36 +254,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.796133 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.810400 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.796133 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128269 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.810400 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128034 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.128269 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 36890 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.128034 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 36966 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.172646 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38335 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.152238 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38411 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.693234 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38497 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.679181 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38573 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.303154 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40555 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.289814 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40631 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.347700 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38373 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.343412 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.601734 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 142.226837 # Cycle average of tags in use -system.cpu.icache.total_refs 892 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.065292 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 142.226837 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069447 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069447 # Average percentage of cache occupancy +system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits @@ -296,12 +296,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25702500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25702500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25702500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25702500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25702500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25702500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25692750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25692750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25692750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25692750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25692750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25692750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -314,12 +314,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70225.409836 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70225.409836 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70225.409836 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70225.409836 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70198.770492 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70198.770492 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70198.770492 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70198.770492 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,26 +340,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21114000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21114000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21114000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21114000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21114000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21114000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20948250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20948250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20948250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20948250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20948250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20948250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72556.701031 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72556.701031 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71987.113402 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71987.113402 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1313010186 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1310611705 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -374,21 +374,21 @@ system.cpu.toL2Bus.data_through_bus 27264 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 168.609847 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 141.647687 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.962160 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004323 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005146 # Average percentage of cache occupancy +system.cpu.toL2Bus.respLayer0.occupancy 489750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -409,17 +409,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20795500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3765500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5904000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5904000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20795500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9669500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30465000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20795500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9669500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30465000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20629750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3759250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24389000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5820750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5820750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20629750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9580000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30209750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20629750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9580000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30209750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -442,17 +442,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71956.747405 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71047.169811 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71815.789474 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72888.888889 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72888.888889 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72021.276596 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72021.276596 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71383.217993 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70929.245283 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71312.865497 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71861.111111 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71861.111111 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71417.848700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71417.848700 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,17 +472,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17227750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3116250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20344000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4915500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4915500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17227750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8031750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25259500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17227750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8031750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25259500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17007250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20108500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4823250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4823250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17007250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7924500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24931750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17007250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7924500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24931750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -494,27 +494,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59611.591696 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58797.169811 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59485.380117 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60685.185185 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.185185 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58848.615917 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58514.150943 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58796.783626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59546.296296 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59546.296296 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 84.923213 # Cycle average of tags in use -system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 84.923213 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020733 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020733 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -531,14 +531,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4316000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4316000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26761000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26761000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31077000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31077000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31077000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31077000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4325500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4325500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26675750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26675750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31001250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31001250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31001250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31001250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -555,19 +555,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.098361 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.098361 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64796.610169 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64796.610169 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65563.291139 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65563.291139 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70909.836066 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70909.836066 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64590.193705 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64590.193705 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65403.481013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65403.481013 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.406250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.548387 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -587,14 +587,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5987500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5987500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9819500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9819500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9819500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9819500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3825750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3825750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5904250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5904250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9730000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9730000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9730000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9730000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -603,14 +603,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70962.962963 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70962.962963 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73919.753086 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73919.753086 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70847.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70847.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72891.975309 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72891.975309 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 404dd533e..c4b2117ab 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 55600 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 117.043638 # Cycle average of tags in use -system.cpu.icache.total_refs 5114 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19.898833 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits @@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 142.183999 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -271,15 +271,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use -system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 43264ddcf..7c9257554 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,50 +1,50 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19589000 # Number of ticks simulated -final_tick 19589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19639500 # Number of ticks simulated +final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1364 # Simulator instruction rate (inst/s) -host_op_rate 2472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4967212 # Simulator tick rate (ticks/s) +host_inst_rate 28578 # Simulator instruction rate (inst/s) +host_op_rate 51768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 104294046 # Simulator tick rate (ticks/s) host_mem_usage 245432 # Number of bytes of host memory used -host_seconds 3.94 # Real time elapsed on the host +host_seconds 0.19 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory -system.physmem.num_reads::total 413 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 891929144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 457399561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1349328705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 891929144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 891929144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 891929144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 457399561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1349328705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 414 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory +system.physmem.bytes_read::total 26624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 416 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 892894422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 462740905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1355635327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 892894422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 892894422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 417 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 414 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 26432 # Total number of bytes read from memory +system.physmem.cpureqs 417 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 26624 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 26432 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 51 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19541000 # Total gap between requests +system.physmem.totGap 19591000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 414 # Categorize read packet sizes +system.physmem.readPktSize::6 417 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,303 +149,302 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 216.275862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 131.153640 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.056442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 43 49.43% 49.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 13 14.94% 64.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 10.34% 74.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 4.60% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 7 8.05% 87.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 3.45% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.15% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.15% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.15% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.15% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 2.30% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.15% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation -system.physmem.totQLat 1394000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11081500 # Sum of mem lat for all requests -system.physmem.totBusLat 2070000 # Total cycles spent in databus access -system.physmem.totBankLat 7617500 # Total cycles spent in bank access -system.physmem.avgQLat 3367.15 # Average queueing delay per request -system.physmem.avgBankLat 18399.76 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 88 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.605669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.610045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 42 47.73% 47.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 13 14.77% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 12 13.64% 76.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 4.55% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 6 6.82% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 3.41% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.14% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.14% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.14% 94.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.14% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 2.27% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.14% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 1.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88 # Bytes accessed per row activation +system.physmem.totQLat 1395750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11125750 # Sum of mem lat for all requests +system.physmem.totBusLat 2085000 # Total cycles spent in databus access +system.physmem.totBankLat 7645000 # Total cycles spent in bank access +system.physmem.avgQLat 3347.12 # Average queueing delay per request +system.physmem.avgBankLat 18333.33 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26766.91 # Average memory access latency -system.physmem.avgRdBW 1349.33 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26680.46 # Average memory access latency +system.physmem.avgRdBW 1355.64 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1349.33 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1355.64 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.54 # Data bus utilization in percentage +system.physmem.busUtil 10.59 # Data bus utilization in percentage system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 327 # Number of row buffer hits during reads +system.physmem.readRowHits 329 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47200.48 # Average gap between requests -system.membus.throughput 1349328705 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 337 # Transaction distribution -system.membus.trans_dist::ReadResp 336 # Transaction distribution +system.physmem.avgGap 46980.82 # Average gap between requests +system.membus.throughput 1355635327 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 340 # Transaction distribution +system.membus.trans_dist::ReadResp 339 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution system.membus.trans_dist::ReadExResp 77 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 827 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26432 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26432 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26624 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 498000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3864000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.7 # Layer utilization (%) -system.cpu.branchPred.lookups 3089 # Number of BP lookups -system.cpu.branchPred.condPredicted 3089 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2286 # Number of BTB lookups -system.cpu.branchPred.BTBHits 726 # Number of BTB hits +system.membus.reqLayer0.occupancy 505500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3891500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.8 # Layer utilization (%) +system.cpu.branchPred.lookups 3060 # Number of BP lookups +system.cpu.branchPred.condPredicted 3060 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2257 # Number of BTB lookups +system.cpu.branchPred.BTBHits 719 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.758530 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 31.856447 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 208 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39179 # number of cpu cycles simulated +system.cpu.numCycles 39280 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10273 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14155 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3089 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3944 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5406 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 375 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21925 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.151015 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.666624 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10420 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14154 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3060 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 927 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3932 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5289 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 384 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1977 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.145317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.661061 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18081 82.47% 82.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 213 0.97% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 143 0.65% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 223 1.02% 85.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 185 0.84% 85.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 200 0.91% 86.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 277 1.26% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 0.72% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2445 11.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18121 82.55% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 212 0.97% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 149 0.68% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 217 0.99% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 180 0.82% 86.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 202 0.92% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 278 1.27% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 161 0.73% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2432 11.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21925 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078843 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.361290 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11051 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5299 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3578 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24188 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11417 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3782 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 753 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3333 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 783 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.fetch.rateDist::total 21952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077902 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.360336 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11197 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5173 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3579 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1866 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24141 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1866 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11552 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3842 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 569 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3343 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 780 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22717 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 669 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25230 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 54980 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54964 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 666 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25267 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55251 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 55235 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14167 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2073 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2281 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1568 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 14204 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2015 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2290 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1582 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20212 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17024 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9720 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13890 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17094 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 292 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9804 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14093 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21925 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.776465 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.650682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 21952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.778699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.655311 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16429 74.93% 74.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1551 7.07% 82.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1089 4.97% 86.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 725 3.31% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 705 3.22% 93.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 574 2.62% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 578 2.64% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 230 1.05% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 44 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16455 74.96% 74.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1544 7.03% 81.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1078 4.91% 86.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 728 3.32% 90.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 707 3.22% 93.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 584 2.66% 96.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 572 2.61% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 242 1.10% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21925 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21952 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 139 76.80% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27 14.92% 91.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 143 77.72% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.13% 91.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 8.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13662 80.25% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1972 11.58% 91.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1376 8.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13719 80.26% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1979 11.58% 91.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1382 8.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17024 # Type of FU issued -system.cpu.iq.rate 0.434518 # Inst issue rate -system.cpu.iq.fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010632 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56436 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 29967 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15651 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17094 # Type of FU issued +system.cpu.iq.rate 0.435183 # Inst issue rate +system.cpu.iq.fu_busy_cnt 184 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010764 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56608 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30145 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15699 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17198 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17271 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 173 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 170 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1228 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1237 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 633 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2975 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20240 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 40 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2281 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1568 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1866 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3033 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20334 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 50 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2290 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1582 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 114 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 683 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16133 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1855 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 891 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 113 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 578 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 691 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16182 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1848 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 912 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3133 # number of memory reference insts executed -system.cpu.iew.exec_branches 1621 # Number of branches executed -system.cpu.iew.exec_stores 1278 # Number of stores executed -system.cpu.iew.exec_rate 0.411777 # Inst execution rate -system.cpu.iew.wb_sent 15873 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15655 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10119 # num instructions producing a value -system.cpu.iew.wb_consumers 15566 # num instructions consuming a value +system.cpu.iew.exec_refs 3125 # number of memory reference insts executed +system.cpu.iew.exec_branches 1615 # Number of branches executed +system.cpu.iew.exec_stores 1277 # Number of stores executed +system.cpu.iew.exec_rate 0.411965 # Inst execution rate +system.cpu.iew.wb_sent 15923 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15703 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10139 # num instructions producing a value +system.cpu.iew.wb_consumers 15623 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399576 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.650071 # average fanout of values written-back +system.cpu.iew.wb_rate 0.399771 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.648979 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10504 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20068 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485699 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.341238 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485263 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.340827 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16495 82.20% 82.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1364 6.80% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 592 2.95% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 713 3.55% 95.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16512 82.21% 82.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1365 6.80% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 596 2.97% 91.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 708 3.52% 95.49% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71 0.35% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 213 1.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 73 0.36% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20086 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -456,138 +455,138 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9654 # Number of committed integer instructions. system.cpu.commit.function_calls 106 # Number of function calls committed. -system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40106 # The number of ROB reads -system.cpu.rob.rob_writes 42382 # The number of ROB writes -system.cpu.timesIdled 168 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17254 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40219 # The number of ROB reads +system.cpu.rob.rob_writes 42582 # The number of ROB writes +system.cpu.timesIdled 167 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17328 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 7.282342 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.282342 # CPI: Total CPI of All Threads -system.cpu.ipc 0.137318 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.137318 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28721 # number of integer regfile reads -system.cpu.int_regfile_writes 17199 # number of integer regfile writes +system.cpu.cpi 7.301115 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.301115 # CPI: Total CPI of All Threads +system.cpu.ipc 0.136965 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.136965 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28824 # number of integer regfile reads +system.cpu.int_regfile_writes 17237 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7135 # number of misc regfile reads +system.cpu.misc_regfile_reads 7122 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1355862984 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 338 # Transaction distribution +system.cpu.toL2Bus.throughput 1362152804 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 342 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 831 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 26560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26560 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 550 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 287 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 411000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 130.964375 # Cycle average of tags in use -system.cpu.icache.total_refs 1611 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 274 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.879562 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 130.964375 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.063947 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.063947 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1611 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1611 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1611 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1611 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1611 # number of overall hits -system.cpu.icache.overall_hits::total 1611 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 370 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 370 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 370 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 370 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 370 # number of overall misses -system.cpu.icache.overall_misses::total 370 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24285500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24285500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24285500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24285500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24285500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24285500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186774 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186774 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186774 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186774 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186774 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186774 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65636.486486 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65636.486486 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65636.486486 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65636.486486 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65636.486486 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65636.486486 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer0.occupancy 463250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1608 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1608 # number of overall hits +system.cpu.icache.overall_hits::total 1608 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses +system.cpu.icache.overall_misses::total 369 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24439500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24439500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24439500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24439500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24439500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24439500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1977 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1977 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1977 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1977 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1977 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1977 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186646 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186646 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186646 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186646 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186646 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186646 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66231.707317 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66231.707317 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66231.707317 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66231.707317 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 70 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 96 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 96 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 96 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 96 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 96 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18984000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18984000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18984000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18984000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18984000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18984000 # 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average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995227 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995227 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55924.270073 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57729.228487 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58113.636364 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58113.636364 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56112.637363 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61069.148936 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57800.724638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56112.637363 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61069.148936 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57800.724638 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57613.235294 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58448.051948 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58448.051948 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 81.657362 # Cycle average of tags in use -system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.553191 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 81.657362 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.019936 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.019936 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1476 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1476 # number of ReadReq hits +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2334 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2334 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2334 # number of overall hits -system.cpu.dcache.overall_hits::total 2334 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2341 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2341 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2341 # number of overall hits +system.cpu.dcache.overall_hits::total 2341 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses -system.cpu.dcache.overall_misses::total 208 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9350500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9350500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5649500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5649500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15000000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15000000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15000000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15000000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1607 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1607 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses +system.cpu.dcache.overall_misses::total 210 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9610000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9610000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5723000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5723000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15333000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15333000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15333000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15333000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1616 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1616 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2542 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2542 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2542 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2542 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081518 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081518 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082302 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.082302 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081825 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081825 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081825 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081825 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71377.862595 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71377.862595 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73370.129870 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73370.129870 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72115.384615 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72115.384615 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72115.384615 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72115.384615 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.082321 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082321 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082321 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082321 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72255.639098 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72255.639098 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74324.675325 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74324.675325 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73014.285714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73014.285714 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 163 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,38 +775,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 66 system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5495500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5495500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10484500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10484500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10484500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10484500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040448 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040448 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5151750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5151750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5538000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5538000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10689750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10689750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10689750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10689750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055862 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055862 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76753.846154 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76753.846154 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71370.129870 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71370.129870 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76891.791045 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76891.791045 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71922.077922 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71922.077922 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 7844ef634..f38f31bd7 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -69,15 +69,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 56716 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 105.550219 # Cycle average of tags in use -system.cpu.icache.total_refs 6637 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits @@ -147,17 +147,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 134.034140 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004090 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -272,15 +272,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 80.797237 # Cycle average of tags in use -system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 6de850a93..099eda912 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 23841000 # Number of ticks simulated -final_tick 23841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24404000 # Number of ticks simulated +final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85306 # Simulator instruction rate (inst/s) -host_op_rate 85298 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 159545701 # Simulator tick rate (ticks/s) +host_inst_rate 52847 # Simulator instruction rate (inst/s) +host_op_rate 52845 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101181200 # Simulator tick rate (ticks/s) host_mem_usage 228064 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_seconds 0.24 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory -system.physmem.bytes_read::total 62400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 62336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 975 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1677781972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 939557904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2617339877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1677781972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1677781972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1677781972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 939557904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2617339877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 975 # Total number of read requests seen +system.physmem.num_reads::total 974 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1636453040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 917882314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2554335355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1636453040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1636453040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1636453040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 917882314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2554335355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 974 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 975 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 62400 # Total number of bytes read from memory +system.physmem.cpureqs 974 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 62336 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62400 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 62336 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 154 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 153 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 77 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 86 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 87 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 41 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 39 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23399000 # Total gap between requests +system.physmem.totGap 24245500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 975 # Categorize read packet sizes +system.physmem.readPktSize::6 974 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,100 +149,101 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 309.392265 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 160.897114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 490.133684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 75 41.44% 41.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 28 15.47% 56.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 19 10.50% 67.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 20 11.05% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 1.10% 79.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 4 2.21% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 4 2.21% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 3 1.66% 85.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 2 1.10% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 4 2.21% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 1.10% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 0.55% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1 0.55% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 1.10% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 2 1.10% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 1.10% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 0.55% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 1 0.55% 95.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 1 0.55% 96.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 0.55% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 2 1.10% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 0.55% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 1 0.55% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 2 1.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 181 # Bytes accessed per row activation -system.physmem.totQLat 6851500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 28281500 # Sum of mem lat for all requests -system.physmem.totBusLat 4875000 # Total cycles spent in databus access -system.physmem.totBankLat 16555000 # Total cycles spent in bank access -system.physmem.avgQLat 7027.18 # Average queueing delay per request -system.physmem.avgBankLat 16979.49 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.957672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.277128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 472.297416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 80 42.33% 42.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 30 15.87% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 19 10.05% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 20 10.58% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 1.59% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 5 2.65% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 2.12% 85.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 3 1.59% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 0.53% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 6 3.17% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 0.53% 91.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 0.53% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 0.53% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 1.06% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.53% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 1.06% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 0.53% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 1 0.53% 95.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 0.53% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 1 0.53% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 1.06% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 0.53% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 0.53% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 1 0.53% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 1 0.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 189 # Bytes accessed per row activation +system.physmem.totQLat 8948500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 30593500 # Sum of mem lat for all requests +system.physmem.totBusLat 4870000 # Total cycles spent in databus access +system.physmem.totBankLat 16775000 # Total cycles spent in bank access +system.physmem.avgQLat 9187.37 # Average queueing delay per request +system.physmem.avgBankLat 17222.79 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29006.67 # Average memory access latency -system.physmem.avgRdBW 2617.34 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 31410.16 # Average memory access latency +system.physmem.avgRdBW 2554.34 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2617.34 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2554.34 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 20.45 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.19 # Average read queue length over time +system.physmem.busUtil 19.96 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.25 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 794 # Number of row buffer hits during reads +system.physmem.readRowHits 785 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23998.97 # Average gap between requests -system.membus.throughput 2617339877 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 829 # Transaction distribution -system.membus.trans_dist::ReadResp 829 # Transaction distribution +system.physmem.avgGap 24892.71 # Average gap between requests +system.membus.throughput 2554335355 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 828 # Transaction distribution +system.membus.trans_dist::ReadResp 828 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1950 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1950 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 62400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 62400 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 62400 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 1948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1948 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 62336 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 62336 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 62336 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9055000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 38.0 # Layer utilization (%) -system.cpu.branchPred.lookups 6923 # Number of BP lookups -system.cpu.branchPred.condPredicted 3910 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1532 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5090 # Number of BTB lookups -system.cpu.branchPred.BTBHits 950 # Number of BTB hits +system.membus.reqLayer0.occupancy 1227000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 9049000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 37.1 # Layer utilization (%) +system.cpu.branchPred.lookups 6717 # Number of BP lookups +system.cpu.branchPred.condPredicted 3814 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1469 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4787 # Number of BTB lookups +system.cpu.branchPred.BTBHits 874 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.664047 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 864 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 198 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 18.257781 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 896 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 177 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4694 # DTB read hits +system.cpu.dtb.read_hits 4630 # DTB read hits system.cpu.dtb.read_misses 109 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4803 # DTB read accesses -system.cpu.dtb.write_hits 2055 # DTB write hits -system.cpu.dtb.write_misses 93 # DTB write misses +system.cpu.dtb.read_accesses 4739 # DTB read accesses +system.cpu.dtb.write_hits 2007 # DTB write hits +system.cpu.dtb.write_misses 95 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2148 # DTB write accesses -system.cpu.dtb.data_hits 6749 # DTB hits -system.cpu.dtb.data_misses 202 # DTB misses +system.cpu.dtb.write_accesses 2102 # DTB write accesses +system.cpu.dtb.data_hits 6637 # DTB hits +system.cpu.dtb.data_misses 204 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6951 # DTB accesses -system.cpu.itb.fetch_hits 5431 # ITB hits -system.cpu.itb.fetch_misses 58 # ITB misses +system.cpu.dtb.data_accesses 6841 # DTB accesses +system.cpu.itb.fetch_hits 5430 # ITB hits +system.cpu.itb.fetch_misses 55 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5489 # ITB accesses +system.cpu.itb.fetch_accesses 5485 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -257,350 +258,350 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 47683 # number of cpu cycles simulated +system.cpu.numCycles 48809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1647 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 37826 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6923 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1814 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6352 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1907 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 435 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5431 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 913 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28904 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.308677 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.731944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1620 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 37306 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6717 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1770 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6254 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1868 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 368 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5430 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 908 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.300949 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.721933 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22552 78.02% 78.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 590 2.04% 80.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 356 1.23% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 460 1.59% 82.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 445 1.54% 84.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 430 1.49% 85.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 481 1.66% 87.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 392 1.36% 88.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3198 11.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22422 78.19% 78.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 547 1.91% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 376 1.31% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 432 1.51% 82.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 434 1.51% 84.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 433 1.51% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 459 1.60% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 528 1.84% 89.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3045 10.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28904 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.145188 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.793281 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 39785 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9139 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5505 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 442 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2806 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 644 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 419 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 33037 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 796 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2806 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 40500 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6036 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5106 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2260 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30593 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2227 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 22886 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 37694 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37660 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 28676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137618 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.764326 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 39987 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8556 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5391 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2766 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 575 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 354 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 32748 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 724 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2766 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 40726 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5410 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 972 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5017 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2276 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30111 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 2293 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22579 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 37089 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 37055 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13746 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 54 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5822 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3090 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1408 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 13439 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 57 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6273 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3023 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 3019 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1424 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 3003 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1402 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26797 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 83 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 22164 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 13006 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8107 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28904 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.766814 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.345310 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 26482 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21796 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12686 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8147 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.760078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.341515 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19221 66.50% 66.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3610 12.49% 78.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2656 9.19% 88.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1611 5.57% 93.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1014 3.51% 97.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 491 1.70% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 230 0.80% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 50 0.17% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 21 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19237 67.08% 67.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3397 11.85% 78.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2648 9.23% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1591 5.55% 93.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1050 3.66% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 477 1.66% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 210 0.73% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 43 0.15% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 23 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28904 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28676 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 2.84% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 106 60.23% 63.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 65 36.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7 4.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 102 58.29% 62.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 66 37.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7310 65.49% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2686 24.06% 89.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1161 10.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7221 65.66% 65.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2635 23.96% 89.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1137 10.34% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11162 # Type of FU issued +system.cpu.iq.FU_type_0::total 10998 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7255 65.94% 65.96% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2595 23.59% 89.57% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1147 10.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7106 65.81% 65.83% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.84% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.84% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2582 23.91% 89.77% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1105 10.23% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11002 # Type of FU issued +system.cpu.iq.FU_type_1::total 10798 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14565 65.71% 65.73% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 65.74% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 65.74% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::MemRead 5281 23.83% 89.59% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2308 10.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14327 65.73% 65.75% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 65.76% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.78% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::MemRead 5217 23.94% 89.71% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2242 10.29% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 22164 # Type of FU issued -system.cpu.iq.rate 0.464820 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 86 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 90 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 176 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.003880 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004061 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.007941 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 73490 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 39895 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19126 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type::total 21796 # Type of FU issued +system.cpu.iq.rate 0.446557 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 89 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 86 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 175 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004083 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.003946 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008029 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 72523 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 39256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 18760 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22314 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21945 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 52 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1907 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 543 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1840 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 358 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 56 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 48 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1836 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 559 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1820 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 537 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 384 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2806 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2710 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 27087 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 546 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6109 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2832 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 83 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 255 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1333 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20623 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2441 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2376 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4817 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1541 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2766 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 26762 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 628 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 6026 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2758 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 20 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 225 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1292 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20286 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2395 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2362 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4757 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1510 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 115 # number of nop insts executed -system.cpu.iew.exec_nop::1 92 # number of nop insts executed -system.cpu.iew.exec_nop::total 207 # number of nop insts executed -system.cpu.iew.exec_refs::0 3520 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3467 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6987 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1642 # Number of branches executed -system.cpu.iew.exec_branches::1 1654 # Number of branches executed -system.cpu.iew.exec_branches::total 3296 # Number of branches executed -system.cpu.iew.exec_stores::0 1079 # Number of stores executed -system.cpu.iew.exec_stores::1 1091 # Number of stores executed -system.cpu.iew.exec_stores::total 2170 # Number of stores executed -system.cpu.iew.exec_rate 0.432502 # Inst execution rate -system.cpu.iew.wb_sent::0 9753 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9719 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19472 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9565 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9581 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19146 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4912 # num instructions producing a value -system.cpu.iew.wb_producers::1 4854 # num instructions producing a value -system.cpu.iew.wb_producers::total 9766 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6410 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6363 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12773 # num instructions consuming a value +system.cpu.iew.exec_nop::0 112 # number of nop insts executed +system.cpu.iew.exec_nop::1 87 # number of nop insts executed +system.cpu.iew.exec_nop::total 199 # number of nop insts executed +system.cpu.iew.exec_refs::0 3467 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3404 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6871 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1580 # Number of branches executed +system.cpu.iew.exec_branches::1 1582 # Number of branches executed +system.cpu.iew.exec_branches::total 3162 # Number of branches executed +system.cpu.iew.exec_stores::0 1072 # Number of stores executed +system.cpu.iew.exec_stores::1 1042 # Number of stores executed +system.cpu.iew.exec_stores::total 2114 # Number of stores executed +system.cpu.iew.exec_rate 0.415620 # Inst execution rate +system.cpu.iew.wb_sent::0 9597 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9491 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19088 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9418 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9362 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18780 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4881 # num instructions producing a value +system.cpu.iew.wb_producers::1 4800 # num instructions producing a value +system.cpu.iew.wb_producers::total 9681 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6383 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6247 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12630 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.200596 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.200931 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.401527 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.766303 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.762848 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.764582 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.192956 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.191809 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.384765 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.764687 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.768369 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.766508 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 14336 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13991 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1138 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.443084 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.197327 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1133 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.446662 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.213615 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22992 79.72% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3164 10.97% 90.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1129 3.91% 94.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 501 1.74% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 358 1.24% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 236 0.82% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 188 0.65% 99.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70 0.24% 99.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 203 0.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22891 80.01% 80.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3017 10.55% 90.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1097 3.83% 94.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 546 1.91% 96.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 330 1.15% 97.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 253 0.88% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 201 0.70% 99.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 61 0.21% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 214 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 28610 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6390 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -631,210 +632,210 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 203 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132883 # The number of ROB reads -system.cpu.rob.rob_writes 57054 # The number of ROB writes -system.cpu.timesIdled 370 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18779 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 131690 # The number of ROB reads +system.cpu.rob.rob_writes 56322 # The number of ROB writes +system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20133 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6373 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 7.482034 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.483208 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.741310 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.133654 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.133633 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.267286 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25857 # number of integer regfile reads -system.cpu.int_regfile_writes 14461 # number of integer regfile writes +system.cpu.cpi::0 7.658716 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.659918 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.829659 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.130570 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.130550 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.261120 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25473 # number of integer regfile reads +system.cpu.int_regfile_writes 14213 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.toL2Bus.throughput 2622708779 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 831 # Transaction distribution +system.cpu.toL2Bus.throughput 2559580397 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1252 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1952 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40064 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 62528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 62528 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size 62464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 940500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 525000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.cpu.icache.replacements::0 6 # number of replacements -system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 313.799979 # Cycle average of tags in use -system.cpu.icache.total_refs 4370 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.969697 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 313.799979 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.153223 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.153223 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4370 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4370 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4370 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4370 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4370 # number of overall hits -system.cpu.icache.overall_hits::total 4370 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1055 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1055 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1055 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1055 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1055 # number of overall misses -system.cpu.icache.overall_misses::total 1055 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 67889996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 67889996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 67889996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 67889996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 67889996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 67889996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5425 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5425 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5425 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5425 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5425 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5425 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194470 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194470 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194470 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194470 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194470 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194470 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64350.707109 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64350.707109 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64350.707109 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64350.707109 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64350.707109 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64350.707109 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2740 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer0.occupancy 1029500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 566500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.cpu.icache.tags.replacements::0 6 # number of replacements +system.cpu.icache.tags.replacements::1 0 # number of replacements +system.cpu.icache.tags.replacements::total 6 # number of replacements +system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4375 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4375 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4375 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4375 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4375 # number of overall hits +system.cpu.icache.overall_hits::total 4375 # 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mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61683.076923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.200000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64543.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61683.076923 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61815.705128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67138.480392 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63127.113527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69203.767123 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69203.767123 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61815.705128 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61815.705128 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements::0 0 # number of replacements -system.cpu.dcache.replacements::1 0 # number of replacements -system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 213.416851 # Cycle average of tags in use -system.cpu.dcache.total_refs 4586 # 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.837143 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 211.884963 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.051730 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.051730 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3469 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3469 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1024 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4493 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4493 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4493 # number of overall hits +system.cpu.dcache.overall_hits::total 4493 # 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average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69739.999029 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69739.999029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69739.999029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69739.999029 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4722 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 128 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.328125 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.358974 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 122 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 122 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 567 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 567 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 689 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 689 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 689 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 689 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 560 # 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number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16628000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16628000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10609995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10609995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27237995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27237995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27237995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27237995 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052375 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16427250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16427250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12061996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12061996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28489246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28489246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28489246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28489246 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053783 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053783 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062222 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062222 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062222 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062222 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81509.803922 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81509.803922 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72671.198630 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72671.198630 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77822.842857 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77822.842857 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77822.842857 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77822.842857 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063371 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063371 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063371 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063371 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80525.735294 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80525.735294 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82616.410959 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82616.410959 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81397.845714 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81397.845714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81397.845714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81397.845714 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index d7ab6a34e..60e6f3a9f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27167500 # Number of ticks simulated -final_tick 27167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27282000 # Number of ticks simulated +final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49297 # Simulator instruction rate (inst/s) -host_op_rate 49293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88314525 # Simulator tick rate (ticks/s) -host_mem_usage 232472 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host +host_inst_rate 50184 # Simulator instruction rate (inst/s) +host_op_rate 50180 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90285398 # Simulator tick rate (ticks/s) +host_mem_usage 232468 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 702015276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 325094322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1027109598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 702015276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 702015276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 702015276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 325094322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1027109598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 699068983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 323729932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1022798915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 699068983 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 699068983 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 27134000 # Total gap between requests +system.physmem.totGap 27248500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # By system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation -system.physmem.totQLat 1645750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10137000 # Sum of mem lat for all requests +system.physmem.totQLat 1525500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10030500 # Sum of mem lat for all requests system.physmem.totBusLat 2180000 # Total cycles spent in databus access -system.physmem.totBankLat 6311250 # Total cycles spent in bank access -system.physmem.avgQLat 3774.66 # Average queueing delay per request -system.physmem.avgBankLat 14475.34 # Average bank access latency per request +system.physmem.totBankLat 6325000 # Total cycles spent in bank access +system.physmem.avgQLat 3498.85 # Average queueing delay per request +system.physmem.avgBankLat 14506.88 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23250.00 # Average memory access latency -system.physmem.avgRdBW 1027.11 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23005.73 # Average memory access latency +system.physmem.avgRdBW 1022.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1027.11 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1022.80 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 8.02 # Data bus utilization in percentage +system.physmem.busUtil 7.99 # Data bus utilization in percentage system.physmem.avgRdQLen 0.37 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 387 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 62233.94 # Average gap between requests -system.membus.throughput 1024753842 # Throughput (bytes/s) +system.physmem.avgGap 62496.56 # Average gap between requests +system.membus.throughput 1020453046 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution @@ -203,7 +203,7 @@ system.membus.data_through_bus 27840 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4057250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4055250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.9 # Layer utilization (%) system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted @@ -215,7 +215,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 54336 # number of cpu cycles simulated +system.cpu.numCycles 54565 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -237,12 +237,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21896 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21826 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36768 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 430 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 36997 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 32.332155 # Percentage of cycles cpu is active +system.cpu.activity 32.196463 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -254,36 +254,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.583696 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.598800 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.583696 # CPI: Total CPI of All Threads -system.cpu.ipc 0.279042 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.598800 # CPI: Total CPI of All Threads +system.cpu.ipc 0.277870 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.279042 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 40910 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.277870 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 41139 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.709217 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44983 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.605516 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45212 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.213266 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45533 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 17.141024 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 45762 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 16.201045 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 51458 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 16.133052 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 51687 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.296673 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45027 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.274443 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 17.132288 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 168.384950 # Cycle average of tags in use -system.cpu.icache.total_refs 3004 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 168.384950 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.082219 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.082219 # Average percentage of cache occupancy +system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -296,12 +296,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25319500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25319500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25319500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25319500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25319500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25319500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25440250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25440250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25440250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25440250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25440250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25440250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -314,12 +314,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66455.380577 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66455.380577 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66455.380577 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66455.380577 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66772.309711 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66772.309711 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66772.309711 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66772.309711 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,26 +340,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20038500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20038500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20038500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20038500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20038500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20038500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19991500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19991500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19991500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19991500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19991500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19991500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66573.089701 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66573.089701 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66416.943522 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66416.943522 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1029465354 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1025144784 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -374,21 +374,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 448500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 507000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 199.348050 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 167.722707 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.625344 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006084 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -406,17 +406,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19715000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3728500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23443500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5878000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5878000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19715000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9606500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29321500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19715000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9606500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29321500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19668000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3736000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23404000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5885250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5885250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19668000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9621250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29289250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19668000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9621250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29289250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -439,17 +439,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.454849 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70349.056604 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66600.852273 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69152.941176 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69152.941176 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67097.254005 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67097.254005 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65779.264214 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70490.566038 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66488.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.235294 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.235294 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67023.455378 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67023.455378 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -469,17 +469,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16042000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19118500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15937500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19013500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16042000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7917250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23959250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16042000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7917250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23959250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15937500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7916750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23854250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15937500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7916750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23854250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -491,27 +491,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53652.173913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58047.169811 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54313.920455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53302.675585 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58037.735849 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54015.625000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 98.129274 # Cycle average of tags in use -system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 98.129274 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023957 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023957 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -530,14 +530,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4284500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4284500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25306500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25306500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29591000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29591000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29591000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29591000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4310500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4310500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25385000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25385000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29695500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29695500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29695500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29695500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -556,19 +556,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73870.689655 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73870.689655 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.009479 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.009479 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61647.916667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61647.916667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1016 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74318.965517 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74318.965517 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60154.028436 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60154.028436 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61865.625000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61865.625000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.882353 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.969697 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -588,14 +588,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9749000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9749000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9749000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9749000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3790500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3790500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5973250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5973250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9763750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9763750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9763750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9763750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -604,14 +604,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71377.358491 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71377.358491 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70188.235294 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70188.235294 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71518.867925 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71518.867925 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70273.529412 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70273.529412 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 3e2a9c814..5128d5dc2 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 26399500 # Number of ticks simulated -final_tick 26399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 26524500 # Number of ticks simulated +final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93938 # Simulator instruction rate (inst/s) -host_op_rate 93929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171756334 # Simulator tick rate (ticks/s) +host_inst_rate 52714 # Simulator instruction rate (inst/s) +host_op_rate 52709 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96835127 # Simulator tick rate (ticks/s) host_mem_usage 234512 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_seconds 0.27 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 812136593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 356370386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1168506979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 812136593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 812136593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 812136593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 356370386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1168506979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 482 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26239500 # Total gap between requests +system.physmem.totGap 26363500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # By system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation -system.physmem.totQLat 1765750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10927000 # Sum of mem lat for all requests +system.physmem.totQLat 1755500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests system.physmem.totBusLat 2410000 # Total cycles spent in databus access -system.physmem.totBankLat 6751250 # Total cycles spent in bank access -system.physmem.avgQLat 3663.38 # Average queueing delay per request -system.physmem.avgBankLat 14006.74 # Average bank access latency per request +system.physmem.totBankLat 6765000 # Total cycles spent in bank access +system.physmem.avgQLat 3642.12 # Average queueing delay per request +system.physmem.avgBankLat 14035.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22670.12 # Average memory access latency -system.physmem.avgRdBW 1168.51 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22677.39 # Average memory access latency +system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1168.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.13 # Data bus utilization in percentage +system.physmem.busUtil 9.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.41 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 430 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54438.80 # Average gap between requests -system.membus.throughput 1168506979 # Throughput (bytes/s) +system.physmem.avgGap 54696.06 # Average gap between requests +system.membus.throughput 1163000245 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution @@ -200,104 +200,104 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 583000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4486500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 17.0 # Layer utilization (%) -system.cpu.branchPred.lookups 6719 # Number of BP lookups -system.cpu.branchPred.condPredicted 4457 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1075 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5025 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2433 # Number of BTB hits +system.cpu.branchPred.lookups 6716 # Number of BP lookups +system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2432 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.417910 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 52800 # number of cpu cycles simulated +system.cpu.numCycles 53050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12414 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31130 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6719 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2877 # Number of branches that fetch has predicted taken +system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3041 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8772 # Number of cycles fetch has spent blocked +system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 994 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5381 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33187 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.938018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.130523 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24054 72.48% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4509 13.59% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 475 1.43% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33187 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127254 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.589583 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13016 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9761 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8340 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29004 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13656 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 501 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8734 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7953 # Number of cycles rename is running +system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8344 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7952 # Number of cycles rename is running system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26651 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 23943 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49443 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 49443 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 49456 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10124 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3527 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2284 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22510 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22518 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21113 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5507 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21122 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33187 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.636183 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.261114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23946 72.15% 72.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3557 10.72% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2326 7.01% 89.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1693 5.10% 94.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 889 2.68% 97.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 472 1.42% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 239 0.72% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33187 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available @@ -333,113 +333,113 @@ system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15643 74.09% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15651 74.10% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2108 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21113 # Type of FU issued -system.cpu.iq.rate 0.399867 # Inst issue rate +system.cpu.iq.FU_type_0::total 21122 # Type of FU issued +system.cpu.iq.rate 0.398153 # Inst issue rate system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006963 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75656 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31087 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19513 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21260 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21269 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1302 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 836 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 398 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3527 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2284 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 359 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24307 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 399 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1209 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20068 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 946 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1045 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1048 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1134 # number of nop insts executed system.cpu.iew.exec_refs 5224 # number of memory reference insts executed -system.cpu.iew.exec_branches 4238 # Number of branches executed +system.cpu.iew.exec_branches 4239 # Number of branches executed system.cpu.iew.exec_stores 2022 # Number of stores executed -system.cpu.iew.exec_rate 0.380076 # Inst execution rate -system.cpu.iew.wb_sent 19741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19513 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9111 # num instructions producing a value -system.cpu.iew.wb_consumers 11226 # num instructions consuming a value +system.cpu.iew.exec_rate 0.378398 # Inst execution rate +system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19522 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9120 # num instructions producing a value +system.cpu.iew.wb_consumers 11235 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.369564 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.811598 # average fanout of values written-back +system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1075 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31317 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.484146 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.180879 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23994 76.62% 76.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4076 13.02% 89.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 763 2.44% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 350 1.12% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 272 0.87% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 322 1.03% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 115 0.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -450,24 +450,24 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54580 # The number of ROB reads -system.cpu.rob.rob_writes 50280 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19613 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54596 # The number of ROB reads +system.cpu.rob.rob_writes 50298 # The number of ROB writes +system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.657523 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.657523 # CPI: Total CPI of All Threads -system.cpu.ipc 0.273409 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.273409 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32029 # number of integer regfile reads -system.cpu.int_regfile_writes 17831 # number of integer regfile writes +system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads +system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32043 # number of integer regfile reads +system.cpu.int_regfile_writes 17841 # number of integer regfile writes system.cpu.misc_regfile_reads 6919 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1173355556 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution @@ -482,55 +482,55 @@ system.cpu.toL2Bus.data_through_bus 30976 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 505500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 187.819339 # Cycle average of tags in use -system.cpu.icache.total_refs 4874 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.462908 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 187.819339 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.091709 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.091709 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4874 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4874 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4874 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4874 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4874 # number of overall hits -system.cpu.icache.overall_hits::total 4874 # number of overall hits +system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4873 # 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Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 187.205303 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.510503 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001053 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006766 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 399 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8512750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses @@ -683,27 +683,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52981.343284 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59523.437500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54030.701754 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56593.373494 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56593.373494 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52981.343284 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57869.047619 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54471.991701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52981.343284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57869.047619 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54471.991701 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 98.861742 # Cycle average of tags in use -system.cpu.dcache.total_refs 4001 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.217687 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 98.861742 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024136 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024136 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -722,14 +722,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7949500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7949500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24575974 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24575974 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32525474 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32525474 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32525474 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32525474 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32684224 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -748,19 +748,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63091.269841 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63091.269841 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60087.955990 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60087.955990 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60795.278505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60795.278505 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.035714 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -780,14 +780,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4656000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4656000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5790000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5790000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10446000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10446000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4664500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5801750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5801750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10466250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -796,14 +796,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69759.036145 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69759.036145 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index b595d4238..ac8c29d55 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 82736 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use -system.cpu.icache.total_refs 14928 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -268,15 +268,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use -system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 21486e70f..a1275a141 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1454144 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 265.013024 # Cycle average of tags in use -system.cpu.icache.total_refs 499617 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.129401 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits @@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 481.542013 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.014695 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 481.542013 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses @@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use -system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 287.259400 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 8803a901a..2e9aa5100 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -118,15 +118,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 500032 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 152 # number of replacements -system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 152 # number of replacements +system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits @@ -160,15 +160,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 61 # number of replacements -system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 61 # number of replacements +system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits @@ -267,15 +267,15 @@ system.cpu1.num_idle_cycles 0 # Nu system.cpu1.num_busy_cycles 500032 # Number of busy cycles system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.icache.replacements 152 # number of replacements -system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 152 # number of replacements +system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits @@ -309,15 +309,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 61 # number of replacements -system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 61 # number of replacements +system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits @@ -416,15 +416,15 @@ system.cpu2.num_idle_cycles 0 # Nu system.cpu2.num_busy_cycles 500032 # Number of busy cycles system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.icache.replacements 152 # number of replacements -system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu2.icache.tags.replacements 152 # number of replacements +system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits @@ -458,15 +458,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 61 # number of replacements -system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu2.dcache.tags.replacements 61 # number of replacements +system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits @@ -565,15 +565,15 @@ system.cpu3.num_idle_cycles 0 # Nu system.cpu3.num_busy_cycles 500032 # Number of busy cycles system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.icache.replacements 152 # number of replacements -system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu3.icache.tags.replacements 152 # number of replacements +system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits @@ -607,15 +607,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 61 # number of replacements -system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu3.dcache.tags.replacements 61 # number of replacements +system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits @@ -659,31 +659,31 @@ system.cpu3.dcache.cache_copies 0 # nu system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks system.cpu3.dcache.writebacks::total 29 # number of writebacks system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use -system.l2c.total_refs 332 # Total number of references to valid blocks. -system.l2c.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.avg_refs 0.113233 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.029950 # Average percentage of cache occupancy +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use +system.l2c.tags.total_refs 332 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index e6052b6f1..d89f8b6a1 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -171,15 +171,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 1458048 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 152 # number of replacements -system.cpu0.icache.tagsinuse 216.376897 # Cycle average of tags in use -system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.422611 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 152 # number of replacements +system.cpu0.icache.tags.tagsinuse 216.376897 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.422611 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits @@ -249,15 +249,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 47883.369330 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 61 # number of replacements -system.cpu0.dcache.tagsinuse 273.500146 # Cycle average of tags in use -system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.534180 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 61 # number of replacements +system.cpu0.dcache.tags.tagsinuse 273.500146 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.534180 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits @@ -404,15 +404,15 @@ system.cpu1.num_idle_cycles 0 # Nu system.cpu1.num_busy_cycles 1458048 # Number of busy cycles system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.icache.replacements 152 # number of replacements -system.cpu1.icache.tagsinuse 216.373058 # Cycle average of tags in use -system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.422604 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 152 # number of replacements +system.cpu1.icache.tags.tagsinuse 216.373058 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 499549 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 1078.939525 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.422604 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits @@ -482,15 +482,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 47902.807775 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 61 # number of replacements -system.cpu1.dcache.tagsinuse 273.495183 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.534170 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 61 # number of replacements +system.cpu1.dcache.tags.tagsinuse 273.495183 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.534170 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits @@ -637,15 +637,15 @@ system.cpu2.num_idle_cycles 0 # Nu system.cpu2.num_busy_cycles 1458048 # Number of busy cycles system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.icache.replacements 152 # number of replacements -system.cpu2.icache.tagsinuse 216.369218 # Cycle average of tags in use -system.cpu2.icache.total_refs 499542 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 1078.924406 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.422596 # Average percentage of cache occupancy +system.cpu2.icache.tags.replacements 152 # number of replacements +system.cpu2.icache.tags.tagsinuse 216.369218 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 499542 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 1078.924406 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.422596 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits @@ -715,15 +715,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 47922.246220 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 61 # number of replacements -system.cpu2.dcache.tagsinuse 273.490220 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.534161 # Average percentage of cache occupancy +system.cpu2.dcache.tags.replacements 61 # number of replacements +system.cpu2.dcache.tags.tagsinuse 273.490220 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 180309 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.534161 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits @@ -870,15 +870,15 @@ system.cpu3.num_idle_cycles 0 # Nu system.cpu3.num_busy_cycles 1458048 # Number of busy cycles system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.icache.replacements 152 # number of replacements -system.cpu3.icache.tagsinuse 216.365379 # Cycle average of tags in use -system.cpu3.icache.total_refs 499535 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 1078.909287 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.422589 # Average percentage of cache occupancy +system.cpu3.icache.tags.replacements 152 # number of replacements +system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 1078.909287 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.422589 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits @@ -948,15 +948,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 61 # number of replacements -system.cpu3.dcache.tagsinuse 273.485257 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.534151 # Average percentage of cache occupancy +system.cpu3.dcache.tags.replacements 61 # number of replacements +system.cpu3.dcache.tags.tagsinuse 273.485257 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 180307 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 389.431965 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.534151 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits @@ -1048,31 +1048,31 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52306.695464 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 1943.172107 # Cycle average of tags in use -system.l2c.total_refs 332 # Total number of references to valid blocks. -system.l2c.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.avg_refs 0.113233 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.029650 # Average percentage of cache occupancy +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use +system.l2c.tags.total_refs 332 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 6295c2feb..aa46bcce7 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000110 # Number of seconds simulated -sim_ticks 110344500 # Number of ticks simulated -final_tick 110344500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000111 # Number of seconds simulated +sim_ticks 110804500 # Number of ticks simulated +final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97195 # Simulator instruction rate (inst/s) -host_op_rate 97194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10306929 # Simulator tick rate (ticks/s) -host_mem_usage 249456 # Number of bytes of host memory used -host_seconds 10.71 # Real time elapsed on the host -sim_insts 1040548 # Number of instructions simulated -sim_ops 1040548 # Number of ops (including micro ops) simulated +host_inst_rate 110530 # Simulator instruction rate (inst/s) +host_op_rate 110530 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11745373 # Simulator tick rate (ticks/s) +host_mem_usage 249508 # Number of bytes of host memory used +host_seconds 9.43 # Real time elapsed on the host +sim_insts 1042724 # Number of instructions simulated +sim_ops 1042724 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42176 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 4672 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 73 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 659 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 206480613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 97440289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 46400138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11600034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1740005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7540022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 3480010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7540022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 382221135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 206480613 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 46400138 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1740005 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 3480010 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 258100766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 206480613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 97440289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 46400138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11600034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1740005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7540022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 3480010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7540022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 382221135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 205623418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 97035770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 5775939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7508720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 42164353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11551877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 3465563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7508720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380634361 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205623418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 5775939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 42164353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 3465563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 257029272 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205623418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 660 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 736 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 42176 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 75 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis @@ -100,7 +100,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 110316500 # Total gap between requests +system.physmem.totGap 110776500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -115,9 +115,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -180,9 +180,9 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 282 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.796288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.984215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.500000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.723314 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 317.555625 # Bytes accessed per row activation system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation @@ -197,402 +197,402 @@ system.physmem.bytesPerActivate::704 2 1.56% 91.41% # By system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 0.78% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 0.78% 98.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation -system.physmem.totQLat 3607500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 17921250 # Sum of mem lat for all requests +system.physmem.totQLat 3818750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 18118750 # Sum of mem lat for all requests system.physmem.totBusLat 3300000 # Total cycles spent in databus access -system.physmem.totBankLat 11013750 # Total cycles spent in bank access -system.physmem.avgQLat 5465.91 # Average queueing delay per request -system.physmem.avgBankLat 16687.50 # Average bank access latency per request +system.physmem.totBankLat 11000000 # Total cycles spent in bank access +system.physmem.avgQLat 5785.98 # Average queueing delay per request +system.physmem.avgBankLat 16666.67 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27153.41 # Average memory access latency -system.physmem.avgRdBW 382.22 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27452.65 # Average memory access latency +system.physmem.avgRdBW 380.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 382.22 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 380.63 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.99 # Data bus utilization in percentage +system.physmem.busUtil 2.97 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 532 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 167146.21 # Average gap between requests -system.membus.throughput 382221135 # Throughput (bytes/s) +system.physmem.avgGap 167843.18 # Average gap between requests +system.membus.throughput 380634361 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 529 # Transaction distribution system.membus.trans_dist::ReadResp 528 # Transaction distribution -system.membus.trans_dist::UpgradeReq 284 # Transaction distribution -system.membus.trans_dist::UpgradeResp 75 # Transaction distribution -system.membus.trans_dist::ReadExReq 164 # Transaction distribution +system.membus.trans_dist::UpgradeReq 287 # Transaction distribution +system.membus.trans_dist::UpgradeResp 76 # Transaction distribution +system.membus.trans_dist::ReadExReq 163 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 1711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1711 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 906000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer0.occupancy 6286926 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 5.7 # Layer utilization (%) -system.toL2Bus.throughput 1697085038 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2531 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2530 # Transaction distribution +system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.7 # Layer utilization (%) +system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 585 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 356 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 850 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 371 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5415 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 135488 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 51776 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1621980 # Layer occupancy (ticks) +system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2642498 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1437498 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1913498 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1155972 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1929492 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1158481 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 1.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1936496 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 1.8 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1165479 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) -system.cpu0.branchPred.lookups 82851 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80650 # Number of conditional branches predicted +system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 82992 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 80180 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78131 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.444500 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 220690 # number of cpu cycles simulated +system.cpu0.numCycles 221610 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17257 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 491686 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82851 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78643 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 161395 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13763 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1562 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 494 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 196421 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.503225 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215279 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35026 17.83% 17.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79943 40.70% 58.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 973 0.50% 59.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 76047 38.72% 98.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2457 1.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 196421 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.375418 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.227949 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17908 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15370 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 160419 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 285 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2439 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 488842 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2439 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18575 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 759 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14008 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 160070 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 570 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 485981 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 199 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 332328 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 969157 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 969157 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 319407 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing +system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename +system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 970872 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3600 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 155469 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 78571 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75822 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75638 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 406410 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 403726 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 135 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10718 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9636 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 196421 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055412 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097532 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34004 17.31% 17.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4909 2.50% 19.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77804 39.61% 59.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77117 39.26% 98.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1569 0.80% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 649 0.33% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 196421 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 170720 42.29% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155014 38.40% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77992 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 403726 # Type of FU issued -system.cpu0.iq.rate 1.829381 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000550 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1004230 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 418093 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 401910 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued +system.cpu0.iq.rate 1.824931 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 403948 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 75361 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2176 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2439 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 333 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 32 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 483693 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 155469 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 78571 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 342 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1448 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 402662 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 154684 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1064 # Number of squashed instructions skipped in execute +system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 76372 # number of nop insts executed -system.cpu0.iew.exec_refs 232577 # number of memory reference insts executed -system.cpu0.iew.exec_branches 79993 # Number of branches executed -system.cpu0.iew.exec_stores 77893 # Number of stores executed -system.cpu0.iew.exec_rate 1.824559 # Inst execution rate -system.cpu0.iew.wb_sent 402239 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 401910 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238133 # num instructions producing a value -system.cpu0.iew.wb_consumers 240585 # num instructions consuming a value +system.cpu0.iew.exec_nop 76515 # number of nop insts executed +system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed +system.cpu0.iew.exec_branches 80132 # Number of branches executed +system.cpu0.iew.exec_stores 78029 # Number of stores executed +system.cpu0.iew.exec_rate 1.820098 # Inst execution rate +system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238549 # num instructions producing a value +system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.821152 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989808 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12210 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 193982 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430442 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136125 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34427 17.75% 17.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79760 41.12% 58.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2402 1.24% 60.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 529 0.27% 60.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 75180 38.76% 99.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 442 0.23% 99.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 241 0.12% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 308 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 193982 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 471462 # Number of instructions committed -system.cpu0.commit.committedOps 471462 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 472284 # Number of instructions committed +system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 230446 # Number of memory references committed -system.cpu0.commit.loads 153293 # Number of loads committed +system.cpu0.commit.refs 230857 # Number of memory references committed +system.cpu0.commit.loads 153567 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 79040 # Number of branches committed +system.cpu0.commit.branches 79177 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 317738 # Number of committed integer instructions. +system.cpu0.commit.int_insts 318286 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 308 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 676185 # The number of ROB reads -system.cpu0.rob.rob_writes 969800 # The number of ROB writes +system.cpu0.rob.rob_reads 677374 # The number of ROB reads +system.cpu0.rob.rob_writes 971507 # The number of ROB writes system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24269 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 395606 # Number of Instructions Simulated -system.cpu0.committedOps 395606 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 395606 # Number of Instructions Simulated -system.cpu0.cpi 0.557853 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.557853 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.792587 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.792587 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 720352 # number of integer regfile reads -system.cpu0.int_regfile_writes 324661 # number of integer regfile writes +system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 396291 # Number of Instructions Simulated +system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated +system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 721592 # number of integer regfile reads +system.cpu0.int_regfile_writes 325227 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 234400 # number of misc regfile reads +system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 297 # number of replacements -system.cpu0.icache.tagsinuse 241.066229 # Cycle average of tags in use -system.cpu0.icache.total_refs 5081 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.655877 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 241.066229 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.470832 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.470832 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5081 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5081 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5081 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5081 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5081 # number of overall hits -system.cpu0.icache.overall_hits::total 5081 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 754 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 754 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 754 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 754 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 754 # number of overall misses -system.cpu0.icache.overall_misses::total 754 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 34643000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 34643000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 34643000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 34643000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 34643000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 34643000 # number of overall miss cycles +system.cpu0.icache.tags.replacements 297 # number of replacements +system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits +system.cpu0.icache.overall_hits::total 5079 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses +system.cpu0.icache.overall_misses::total 756 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 35147245 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 35147245 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 35147245 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 35147245 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 35147245 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129220 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.129220 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129220 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.129220 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129220 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.129220 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 45945.623342 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 45945.623342 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 45945.623342 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 45945.623342 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 45945.623342 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 45945.623342 # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,582 +601,583 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 166 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 166 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 166 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 168 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27250252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27250252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27250252 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27250252 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 141.846177 # Cycle average of tags in use -system.cpu0.dcache.total_refs 155338 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 913.752941 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 141.846177 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.277043 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.277043 # 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number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006082 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006082 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006082 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006082 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31405.172414 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31405.172414 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65129.324771 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 65129.324771 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19833.333333 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19833.333333 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50731.842271 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50731.842271 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 499 # number of cycles access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006096 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.761905 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 220 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 590 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 590 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses +system.cpu0.dcache.demand_mshr_hits::cpu0.data 593 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13908502 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002347 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002347 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002269 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002269 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32448.935484 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32448.935484 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44988.571429 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44988.571429 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17833.333333 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17833.333333 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 58259 # Number of BP lookups -system.cpu1.branchPred.condPredicted 55591 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 52252 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 51480 # Number of BTB hits +system.cpu1.branchPred.lookups 43495 # Number of BP lookups +system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.522545 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 650 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 176870 # number of cpu cycles simulated +system.cpu1.numCycles 177681 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 24483 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 332703 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 58259 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 52130 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 112942 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3669 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 23224 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 755 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 15523 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 171052 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.945040 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.217476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 58110 33.97% 33.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 56330 32.93% 66.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4061 2.37% 69.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3192 1.87% 71.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 642 0.38% 71.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 43436 25.39% 96.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1285 0.75% 97.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 751 0.44% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 171052 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.329389 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.881060 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27575 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 21737 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 108940 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3156 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2318 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 329200 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2318 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28271 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 9057 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11940 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 106039 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 6101 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 326983 # Number of instructions processed by rename -system.cpu1.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 231035 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 638817 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 638817 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 218174 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12861 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1086 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1205 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8759 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 95375 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 46677 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 44840 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 41648 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 274055 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 4247 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 274319 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 86 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10569 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10360 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 171052 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.603717 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.300528 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 420697 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 55274 32.31% 32.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16462 9.62% 41.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 46955 27.45% 69.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 47561 27.80% 97.19% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3274 1.91% 99.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1158 0.68% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 171052 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 6.05% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 54 19.22% 25.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 74.73% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 130533 47.58% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 97787 35.65% 83.23% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 45999 16.77% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 274319 # Type of FU issued -system.cpu1.iq.rate 1.550964 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 281 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001024 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 720057 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 288914 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 272470 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued +system.cpu1.iq.rate 1.067177 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 274600 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 41423 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2326 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2318 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 743 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 324068 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 95375 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 46677 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1041 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 924 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1387 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 273134 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 94466 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1185 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 45766 # number of nop insts executed -system.cpu1.iew.exec_refs 140389 # number of memory reference insts executed -system.cpu1.iew.exec_branches 55097 # Number of branches executed -system.cpu1.iew.exec_stores 45923 # Number of stores executed -system.cpu1.iew.exec_rate 1.544264 # Inst execution rate -system.cpu1.iew.wb_sent 272765 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 272470 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 157153 # num instructions producing a value -system.cpu1.iew.wb_consumers 161823 # num instructions consuming a value +system.cpu1.iew.exec_nop 30958 # number of nop insts executed +system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed +system.cpu1.iew.exec_branches 40129 # Number of branches executed +system.cpu1.iew.exec_stores 26101 # Number of stores executed +system.cpu1.iew.exec_rate 1.060603 # Inst execution rate +system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 102456 # num instructions producing a value +system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.540510 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.971141 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12117 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 3751 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161408 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.932674 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.096378 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 51564 31.95% 31.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 53244 32.99% 64.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6086 3.77% 68.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 4696 2.91% 71.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 41954 25.99% 98.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 476 0.29% 98.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 816 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161408 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 311949 # Number of instructions committed -system.cpu1.commit.committedOps 311949 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 212432 # Number of instructions committed +system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 138308 # Number of memory references committed -system.cpu1.commit.loads 93049 # Number of loads committed -system.cpu1.commit.membars 3038 # Number of memory barriers committed -system.cpu1.commit.branches 54264 # Number of branches committed +system.cpu1.commit.refs 83673 # Number of memory references committed +system.cpu1.commit.loads 58239 # Number of loads committed +system.cpu1.commit.membars 7917 # Number of memory barriers committed +system.cpu1.commit.branches 39308 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 214693 # Number of committed integer instructions. +system.cpu1.commit.int_insts 145097 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 484071 # The number of ROB reads -system.cpu1.rob.rob_writes 650455 # The number of ROB writes -system.cpu1.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5818 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43818 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 263856 # Number of Instructions Simulated -system.cpu1.committedOps 263856 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 263856 # Number of Instructions Simulated -system.cpu1.cpi 0.670328 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.670328 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.491808 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.491808 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 479823 # number of integer regfile reads -system.cpu1.int_regfile_writes 223101 # number of integer regfile writes +system.cpu1.rob.rob_reads 388816 # The number of ROB reads +system.cpu1.rob.rob_writes 452512 # The number of ROB writes +system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 174425 # Number of Instructions Simulated +system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated +system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 315718 # number of integer regfile reads +system.cpu1.int_regfile_writes 148477 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 141972 # number of misc regfile reads +system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 82.334562 # Cycle average of tags in use -system.cpu1.icache.total_refs 15036 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 35.378824 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 82.334562 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.160810 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.160810 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 15036 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15036 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15036 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15036 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15036 # number of overall hits -system.cpu1.icache.overall_hits::total 15036 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 487 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 487 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 487 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 487 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 487 # number of overall misses -system.cpu1.icache.overall_misses::total 487 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 12109000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 12109000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 12109000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 12109000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 12109000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 12109000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15523 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15523 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15523 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15523 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15523 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15523 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031373 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.031373 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031373 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.031373 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031373 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.031373 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24864.476386 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24864.476386 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24864.476386 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24864.476386 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 318 # number of replacements +system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits +system.cpu1.icache.overall_hits::total 25178 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses +system.cpu1.icache.overall_misses::total 478 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9721502 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 9721502 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9721502 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 9721502 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9721502 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 9721502 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027379 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027379 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027379 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22874.122353 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 50 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 26.168894 # Cycle average of tags in use -system.cpu1.dcache.total_refs 51272 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1831.142857 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 26.168894 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.051111 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.051111 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 52686 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 52686 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 45050 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 45050 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 97736 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 97736 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 97736 # number of overall hits -system.cpu1.dcache.overall_hits::total 97736 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 340 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 340 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 142 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 142 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 482 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 482 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 482 # number of overall misses -system.cpu1.dcache.overall_misses::total 482 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5254500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5254500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3040000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3040000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 532000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 532000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8294500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8294500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8294500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8294500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 53026 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 53026 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 45192 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 45192 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 98218 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 98218 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 98218 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 98218 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.006412 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.006412 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003142 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003142 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.835821 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004907 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004907 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004907 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004907 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15454.411765 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15454.411765 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21408.450704 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21408.450704 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9500 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9500 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17208.506224 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17208.506224 # average overall miss latency +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits +system.cpu1.dcache.overall_hits::total 62948 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses +system.cpu1.dcache.overall_misses::total 451 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,473 +1186,473 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 185 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1346027 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1346027 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1452501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1452501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 420000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 420000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2798528 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2798528 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2798528 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2798528 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002923 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002923 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.835821 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002678 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002678 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 8684.045161 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 8684.045161 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13449.083333 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13449.083333 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7500 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7500 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 40256 # Number of BP lookups -system.cpu2.branchPred.condPredicted 37554 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1244 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 34216 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 33404 # Number of BTB hits +system.cpu2.branchPred.lookups 51236 # Number of BP lookups +system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.626841 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 656 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 176505 # number of cpu cycles simulated +system.cpu2.numCycles 177316 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 35945 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 212693 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 40256 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 34060 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 82824 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3666 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 45362 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 27473 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 251 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 174585 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.218278 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 1.916616 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 91761 52.56% 52.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 44191 25.31% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 10007 5.73% 83.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3161 1.81% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 734 0.42% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 19642 11.25% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1038 0.59% 97.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 777 0.45% 98.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3274 1.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 174585 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.228073 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.205025 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 44684 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 38236 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 73287 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 8707 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2345 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 209159 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2345 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 45347 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 25711 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11752 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 64880 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 17224 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 207132 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 18 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 141115 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 375802 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 375802 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 128666 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12449 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1089 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1217 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19740 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 53610 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 22854 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 26965 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 17848 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 166370 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 10183 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 172186 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 129 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 10670 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10572 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 174585 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.986259 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.235789 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 537620 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 89355 51.18% 51.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 33684 19.29% 70.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 23026 13.19% 83.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 23727 13.59% 97.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3246 1.86% 99.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1164 0.67% 99.78% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 273 0.16% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 174585 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 12 4.35% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 54 19.57% 23.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 76.09% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 88373 51.32% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 61586 35.77% 87.09% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 22227 12.91% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 172186 # Type of FU issued -system.cpu2.iq.rate 0.975530 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 276 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001603 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 519362 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 187269 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 170462 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued +system.cpu2.iq.rate 1.322842 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 172462 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 17592 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2439 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1401 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2345 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 684 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 204373 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 344 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 53610 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 22854 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 451 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 900 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1351 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 171090 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 52536 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1096 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 27820 # number of nop insts executed -system.cpu2.iew.exec_refs 74679 # number of memory reference insts executed -system.cpu2.iew.exec_branches 36982 # Number of branches executed -system.cpu2.iew.exec_stores 22143 # Number of stores executed -system.cpu2.iew.exec_rate 0.969321 # Inst execution rate -system.cpu2.iew.wb_sent 170734 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 170462 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 91387 # num instructions producing a value -system.cpu2.iew.wb_consumers 96059 # num instructions consuming a value +system.cpu2.iew.exec_nop 38706 # number of nop insts executed +system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed +system.cpu2.iew.exec_branches 47927 # Number of branches executed +system.cpu2.iew.exec_stores 36792 # Number of stores executed +system.cpu2.iew.exec_rate 1.316311 # Inst execution rate +system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131730 # num instructions producing a value +system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.965763 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.951363 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12267 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9515 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1244 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 164914 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.164777 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.788510 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 91274 55.35% 55.35% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 35097 21.28% 76.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6075 3.68% 80.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 10441 6.33% 86.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1560 0.95% 87.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 18154 11.01% 98.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 495 0.30% 98.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 812 0.49% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 164914 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 192088 # Number of instructions committed -system.cpu2.commit.committedOps 192088 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 264916 # Number of instructions committed +system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 72624 # Number of memory references committed -system.cpu2.commit.loads 51171 # Number of loads committed -system.cpu2.commit.membars 8798 # Number of memory barriers committed -system.cpu2.commit.branches 36206 # Number of branches committed +system.cpu2.commit.refs 112806 # Number of memory references committed +system.cpu2.commit.loads 76707 # Number of loads committed +system.cpu2.commit.membars 5024 # Number of memory barriers committed +system.cpu2.commit.branches 47088 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 130952 # Number of committed integer instructions. +system.cpu2.commit.int_insts 182014 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 367870 # The number of ROB reads -system.cpu2.rob.rob_writes 411061 # The number of ROB writes -system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1920 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 44183 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 156297 # Number of Instructions Simulated -system.cpu2.committedOps 156297 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 156297 # Number of Instructions Simulated -system.cpu2.cpi 1.129292 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.129292 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.885510 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.885510 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 282509 # number of integer regfile reads -system.cpu2.int_regfile_writes 133289 # number of integer regfile writes +system.cpu2.rob.rob_reads 437936 # The number of ROB reads +system.cpu2.rob.rob_writes 557643 # The number of ROB writes +system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 222015 # Number of Instructions Simulated +system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated +system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 403571 # number of integer regfile reads +system.cpu2.int_regfile_writes 188531 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 76201 # number of misc regfile reads +system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.replacements 318 # number of replacements -system.cpu2.icache.tagsinuse 76.657940 # Cycle average of tags in use -system.cpu2.icache.total_refs 26999 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 63.081776 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 76.657940 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.149723 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.149723 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 26999 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 26999 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 26999 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 26999 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 26999 # number of overall hits -system.cpu2.icache.overall_hits::total 26999 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 474 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 474 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 474 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 474 # number of overall misses -system.cpu2.icache.overall_misses::total 474 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6632500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6632500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6632500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6632500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6632500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6632500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 27473 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 27473 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 27473 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 27473 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 27473 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 27473 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.017253 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.017253 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.017253 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.017253 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.017253 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.017253 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13992.616034 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13992.616034 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13992.616034 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13992.616034 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked +system.cpu2.icache.tags.replacements 317 # number of replacements +system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits +system.cpu2.icache.overall_hits::total 19274 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses +system.cpu2.icache.overall_misses::total 493 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521742 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11521742 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11521742 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11521742 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11521742 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11521742 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19767 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19767 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19767 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19767 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19767 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19767 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024941 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024941 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024941 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024941 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024941 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024941 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23370.673428 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23370.673428 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23370.673428 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 46 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 46 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 46 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 428 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 428 # 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number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1142519 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1142519 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1333500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1333500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 425000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 425000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2476019 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2476019 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2476019 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2476019 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004609 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004609 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004724 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004724 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.760563 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.760563 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004653 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004653 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7096.391304 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7096.391304 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13202.970297 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13202.970297 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7870.370370 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7870.370370 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 182 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 216 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 216 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 216 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526780 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526780 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1514240 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1514240 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 460993 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 460993 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3041020 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3041020 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003025 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 52069 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49356 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1283 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 46005 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 45233 # Number of BTB hits +system.cpu3.branchPred.lookups 56317 # Number of BP lookups +system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.321922 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 642 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 176161 # number of cpu cycles simulated +system.cpu3.numCycles 176970 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 28821 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 290359 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 52069 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45875 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 102938 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3745 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 32453 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7327 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 20536 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 174715 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.661901 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.131946 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 71777 41.08% 41.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 52540 30.07% 71.15% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 6531 3.74% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3210 1.84% 76.73% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 677 0.39% 77.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 34730 19.88% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1243 0.71% 97.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 745 0.43% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3262 1.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 174715 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.295576 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.648259 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 34404 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 28518 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 96588 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5492 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2386 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 286754 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2386 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 35116 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 15951 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11812 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 91334 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 10789 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 284513 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 198512 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 543834 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 543834 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 185460 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 13052 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1098 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1218 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 13448 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 80352 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 37945 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 38583 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 32886 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 235223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6760 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 237671 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10910 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10900 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 576 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 174715 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.360335 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.308190 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 604346 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 69245 39.63% 39.63% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 23718 13.58% 53.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 38151 21.84% 75.04% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 38808 22.21% 97.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3275 1.87% 99.13% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1152 0.66% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 254 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 174715 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 17 5.94% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 59 20.63% 26.57% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 73.43% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 115348 48.53% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 85085 35.80% 84.33% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 37238 15.67% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 237671 # Type of FU issued -system.cpu3.iq.rate 1.349169 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 286 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001203 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 650461 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 252939 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 235820 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued +system.cpu3.iq.rate 1.478471 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 237957 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 32638 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2448 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2386 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 609 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 281506 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 80352 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 37945 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 925 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 236476 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 79331 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 39523 # number of nop insts executed -system.cpu3.iew.exec_refs 116486 # number of memory reference insts executed -system.cpu3.iew.exec_branches 48746 # Number of branches executed -system.cpu3.iew.exec_stores 37155 # Number of stores executed -system.cpu3.iew.exec_rate 1.342386 # Inst execution rate -system.cpu3.iew.wb_sent 236114 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 235820 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 133214 # num instructions producing a value -system.cpu3.iew.wb_consumers 137877 # num instructions consuming a value +system.cpu3.iew.exec_nop 43769 # number of nop insts executed +system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed +system.cpu3.iew.exec_branches 53091 # Number of branches executed +system.cpu3.iew.exec_stores 42613 # Number of stores executed +system.cpu3.iew.exec_rate 1.471764 # Inst execution rate +system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 148532 # num instructions producing a value +system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.338662 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.966180 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12531 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6184 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1283 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 165002 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.630011 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.014402 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 67849 41.12% 41.12% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 46915 28.43% 69.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6084 3.69% 73.24% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7112 4.31% 77.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1576 0.96% 78.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 33196 20.12% 98.62% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 454 0.28% 98.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1000 0.61% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 165002 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 268955 # Number of instructions committed -system.cpu3.commit.committedOps 268955 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 297438 # Number of instructions committed +system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 114381 # Number of memory references committed -system.cpu3.commit.loads 77904 # Number of loads committed -system.cpu3.commit.membars 5468 # Number of memory barriers committed -system.cpu3.commit.branches 47910 # Number of branches committed +system.cpu3.commit.refs 129728 # Number of memory references committed +system.cpu3.commit.loads 87775 # Number of loads committed +system.cpu3.commit.membars 4366 # Number of memory barriers committed +system.cpu3.commit.branches 52284 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 184410 # Number of committed integer instructions. +system.cpu3.commit.int_insts 204138 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 816 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 445085 # The number of ROB reads -system.cpu3.rob.rob_writes 565364 # The number of ROB writes -system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1446 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 224789 # Number of Instructions Simulated -system.cpu3.committedOps 224789 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 224789 # Number of Instructions Simulated -system.cpu3.cpi 0.783673 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.783673 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.276043 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.276043 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 408025 # number of integer regfile reads -system.cpu3.int_regfile_writes 190344 # number of integer regfile writes +system.cpu3.rob.rob_reads 473500 # The number of ROB reads +system.cpu3.rob.rob_writes 621006 # The number of ROB writes +system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 249993 # Number of Instructions Simulated +system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated +system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 453881 # number of integer regfile reads +system.cpu3.int_regfile_writes 211087 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 118055 # number of misc regfile reads +system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.replacements 319 # number of replacements -system.cpu3.icache.tagsinuse 80.505037 # Cycle average of tags in use -system.cpu3.icache.total_refs 20059 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 46.648837 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 80.505037 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.157236 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.157236 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 20059 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 20059 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 20059 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 20059 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 20059 # number of overall hits -system.cpu3.icache.overall_hits::total 20059 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses -system.cpu3.icache.overall_misses::total 477 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6428500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6428500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6428500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6428500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6428500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6428500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 20536 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 20536 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 20536 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 20536 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 20536 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 20536 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023228 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.023228 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023228 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.023228 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023228 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.023228 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13476.939203 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13476.939203 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13476.939203 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13476.939203 # average overall miss latency +system.cpu3.icache.tags.replacements 319 # number of replacements +system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits +system.cpu3.icache.overall_hits::total 17724 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses +system.cpu3.icache.overall_misses::total 475 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2027,106 +2028,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 47 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 47 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 47 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 47 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5181004 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5181004 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5181004 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5181004 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5181004 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5181004 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020939 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.020939 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.020939 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12048.846512 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 24.780818 # Cycle average of tags in use -system.cpu3.dcache.total_refs 42491 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1517.535714 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 24.780818 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.048400 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.048400 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 46335 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 46335 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 36269 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 36269 # number of WriteReq hits +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 82604 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 82604 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 82604 # number of overall hits -system.cpu3.dcache.overall_hits::total 82604 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 340 # 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miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2135,87 +2136,87 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 182 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 215 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 215 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # 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number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 432500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 432500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2349521 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2349521 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2349521 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2349521 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003385 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003385 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002884 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002884 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.828571 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.828571 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003166 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003166 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.632911 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.632911 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12233.342857 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12233.342857 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7456.896552 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7456.896552 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # 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number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # 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Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 3.476542 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.732205 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004346 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000919 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000083 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000053 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006361 # 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miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.192941 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.025701 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.018605 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.037383 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.020930 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.273414 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses @@ -2527,7 +2528,7 @@ system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -2535,59 +2536,59 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 56749.527410 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10563.437500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.986667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66630.319149 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65711.538462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62937.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58604.166667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 65465.648855 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 3469c3943..42fbfc6a4 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -86,15 +86,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 175415 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 222.772698 # Cycle average of tags in use -system.cpu0.icache.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits @@ -128,15 +128,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 150.745494 # Cycle average of tags in use -system.cpu0.dcache.total_refs 81883 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 490.317365 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -210,15 +210,15 @@ system.cpu1.num_idle_cycles 7873.724337 # Nu system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles -system.cpu1.icache.replacements 278 # number of replacements -system.cpu1.icache.tagsinuse 76.751702 # Cycle average of tags in use -system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 278 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits @@ -252,15 +252,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 30.316999 # Cycle average of tags in use -system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits @@ -332,15 +332,15 @@ system.cpu2.num_idle_cycles 7936.951217 # Nu system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.icache.replacements 278 # number of replacements -system.cpu2.icache.tagsinuse 74.781015 # Cycle average of tags in use -system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.replacements 278 # number of replacements +system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits @@ -374,15 +374,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 29.605505 # Cycle average of tags in use -system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.057823 # Average percentage of cache occupancy +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits @@ -454,15 +454,15 @@ system.cpu3.num_idle_cycles 8001.119846 # Nu system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles -system.cpu3.icache.replacements 279 # number of replacements -system.cpu3.icache.tagsinuse 72.874497 # Cycle average of tags in use -system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.replacements 279 # number of replacements +system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits @@ -496,15 +496,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 28.795404 # Cycle average of tags in use -system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.056241 # Average percentage of cache occupancy +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits @@ -554,31 +554,31 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets nan system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 366.582542 # Cycle average of tags in use -system.l2c.total_refs 1220 # Total number of references to valid blocks. -system.l2c.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.897862 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005594 # Average percentage of cache occupancy +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use +system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index a78d037d9..4a2827ac8 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 262793500 # Number of ticks simulated -final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 262794500 # Number of ticks simulated +final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1490059 # Simulator instruction rate (inst/s) -host_op_rate 1490014 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 590046557 # Simulator tick rate (ticks/s) -host_mem_usage 244196 # Number of bytes of host memory used -host_seconds 0.45 # Real time elapsed on the host -sim_insts 663601 # Number of instructions simulated -sim_ops 663601 # Number of ops (including micro ops) simulated +host_inst_rate 146225 # Simulator instruction rate (inst/s) +host_op_rate 146224 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57909206 # Simulator tick rate (ticks/s) +host_mem_usage 244388 # Number of bytes of host memory used +host_seconds 4.54 # Real time elapsed on the host +sim_insts 663567 # Number of instructions simulated +sim_ops 663567 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory @@ -34,30 +34,30 @@ system.physmem.num_reads::cpu2.data 15 # Nu system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 139303293 # Throughput (bytes/s) +system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 139302763 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 430 # Transaction distribution system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 272 # Transaction distribution @@ -70,11 +70,11 @@ system.membus.tot_pkt_size_system.l2c.mem_side 36608 system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 36608 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 855296 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 5423500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 2.1 # Layer utilization (%) -system.toL2Bus.throughput 646591335 # Throughput (bytes/s) +system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.toL2Bus.throughput 646588875 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution @@ -85,11 +85,11 @@ system.toL2Bus.trans_dist::ReadExResp 429 # Tr system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 388 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 355 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 359 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 352 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 401 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes) @@ -102,26 +102,26 @@ system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 116032 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1474488 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1650489 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1281961 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1651987 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1173486 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1177490 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 525587 # number of cpu cycles simulated +system.cpu0.numCycles 525589 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 158574 # Number of instructions committed @@ -140,18 +140,18 @@ system.cpu0.num_mem_refs 74021 # nu system.cpu0.num_load_insts 49007 # Number of load instructions system.cpu0.num_store_insts 25014 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 525587 # Number of busy cycles +system.cpu0.num_busy_cycles 525589 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.401760 # Cycle average of tags in use -system.cpu0.icache.total_refs 158170 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 338.693790 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.401760 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits @@ -164,12 +164,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 467 # system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18147500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18147500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18147500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18147500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18147500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18147500 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses @@ -182,12 +182,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38859.743041 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38859.743041 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38859.743041 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38859.743041 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -202,34 +202,34 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17213500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17213500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17213500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17213500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17213500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17213500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36859.743041 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.572033 # Cycle average of tags in use -system.cpu0.dcache.total_refs 73489 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 440.053892 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.572033 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits @@ -250,16 +250,16 @@ system.cpu0.dcache.demand_misses::cpu0.data 353 # system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4582500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4582500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6978000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6978000 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6974000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6974000 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11560500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11560500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11560500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11560500 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11560981 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11560981 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11560981 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11560981 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) @@ -280,16 +280,16 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26955.882353 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26955.882353 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38131.147541 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38131.147541 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32749.291785 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32749.291785 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -310,16 +310,16 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237519 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237519 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6612000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6612000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6608000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6608000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10849519 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10849519 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10849519 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10849519 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10845019 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10845019 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10845019 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10845019 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses @@ -330,84 +330,84 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24926.582353 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24926.582353 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36131.147541 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36131.147541 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 525587 # number of cpu cycles simulated +system.cpu1.numCycles 525588 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 173389 # 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Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits +system.cpu1.icache.overall_hits::total 163138 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # 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number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 173422 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 173422 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002110 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002110 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002110 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002110 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002110 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002110 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20606.557377 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20606.557377 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20606.557377 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20606.557377 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7546988 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7546988 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7546988 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7546988 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7546988 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7546988 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20620.185792 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20620.185792 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,94 +422,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # 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Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 579.333333 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.692937 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054088 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054088 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 39322 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39322 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7334 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7334 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 19 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 46656 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 46656 # 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Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits +system.cpu1.dcache.overall_hits::total 57685 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses +system.cpu1.dcache.overall_misses::total 263 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2495483 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2495483 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1980000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1980000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4475483 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4475483 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4475483 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4475483 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,114 +518,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 278 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 278 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2972539 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2972539 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 152000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4934539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4934539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4934539 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4934539 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004355 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004355 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014247 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014247 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.773810 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.773810 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005923 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005923 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17282.203488 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17282.203488 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18509.433962 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18509.433962 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2338.461538 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2338.461538 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1762000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1762000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3932517 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3932517 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3932517 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3932517 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 525587 # number of cpu cycles simulated +system.cpu2.numCycles 525588 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 164870 # Number of instructions committed -system.cpu2.committedOps 164870 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112982 # Number of integer alu accesses +system.cpu2.committedInsts 164866 # Number of instructions committed +system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 29953 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112982 # number of integer instructions +system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls +system.cpu2.num_int_insts 112988 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 294323 # number of times the integer registers were read -system.cpu2.num_int_register_writes 112883 # number of times the integer registers were written +system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read +system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59198 # number of memory refs -system.cpu2.num_load_insts 42166 # Number of load instructions -system.cpu2.num_store_insts 17032 # Number of store instructions -system.cpu2.num_idle_cycles 69603.001735 # Number of idle cycles -system.cpu2.num_busy_cycles 455983.998265 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867571 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132429 # Percentage of idle cycles -system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 67.624903 # Cycle average of tags in use -system.cpu2.icache.total_refs 164537 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 449.554645 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 67.624903 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 164537 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 164537 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 164537 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 164537 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 164537 # number of overall hits -system.cpu2.icache.overall_hits::total 164537 # number of overall hits +system.cpu2.num_mem_refs 59208 # number of memory refs +system.cpu2.num_load_insts 42171 # Number of load instructions +system.cpu2.num_store_insts 17037 # Number of store instructions +system.cpu2.num_idle_cycles 69604.869303 # Number of idle cycles +system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles +system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles +system.cpu2.icache.tags.replacements 280 # number of replacements +system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits +system.cpu2.icache.overall_hits::total 164533 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5251500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5251500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5251500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5251500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5251500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 164903 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 164903 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 164903 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 164903 # 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average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14348.360656 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14348.360656 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14348.360656 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5255488 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5255488 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5255488 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5255488 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5255488 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5255488 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 164899 # 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average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809519 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809519 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1710500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1710500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520019 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3520019 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520019 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3520019 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11904.730263 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11904.730263 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15550 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15550 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13435.187023 # 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number of instructions that are conditional controls -system.cpu3.num_int_insts 112266 # number of integer instructions +system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls +system.cpu3.num_int_insts 108218 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 286233 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109194 # number of times the integer registers were written +system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read +system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 57176 # number of memory refs -system.cpu3.num_load_insts 41805 # Number of load instructions -system.cpu3.num_store_insts 15371 # Number of store instructions -system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles -system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles -system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 65.598360 # Cycle average of tags in use -system.cpu3.icache.total_refs 166434 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 453.498638 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 65.598360 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 166434 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 166434 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 166434 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 166434 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 166434 # number of overall hits -system.cpu3.icache.overall_hits::total 166434 # number of overall hits +system.cpu3.num_mem_refs 46164 # number of memory refs +system.cpu3.num_load_insts 39753 # Number of load instructions +system.cpu3.num_store_insts 6411 # Number of store instructions +system.cpu3.num_idle_cycles 69869.868798 # Number of idle cycles +system.cpu3.num_busy_cycles 455718.131202 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles +system.cpu3.icache.tags.replacements 281 # number of replacements +system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 176322 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 176322 # number of overall hits +system.cpu3.icache.overall_hits::total 176322 # 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number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 166801 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 166801 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 166801 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 166801 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 166801 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 166801 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002200 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002200 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002200 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002200 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002200 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002200 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14029.972752 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14029.972752 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14029.972752 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14029.972752 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5147499 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5147499 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5147499 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5147499 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5147499 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 176689 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 176689 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 176689 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 176689 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 176689 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 176689 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002077 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002077 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002077 # 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number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -858,94 +858,94 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4414501 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4414501 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4414501 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4414501 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4414501 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4414501 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002200 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002200 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002200 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12028.613079 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12028.613079 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12028.613079 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4412501 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4412501 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4412501 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4412501 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4412501 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4412501 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002077 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # 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average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 14135.220126 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17509.174312 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 17509.174312 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4103.773585 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4103.773585 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15507.462687 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 15507.462687 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15507.462687 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 15507.462687 # average overall miss latency +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # 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miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -954,72 +954,72 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 159 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1924510 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1924510 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1690500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1690500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 111500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 111500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3615010 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3615010 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3615010 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3615010 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003804 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003804 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.007122 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.007122 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.828125 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.828125 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004693 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004693 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004693 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004693 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 12103.836478 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 12103.836478 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15509.174312 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15509.174312 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2103.773585 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2103.773585 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13488.843284 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13488.843284 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13488.843284 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13488.843284 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # 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number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1888500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661027 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4661027 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661027 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 349.045938 # Cycle average of tags in use -system.l2c.total_refs 1220 # Total number of references to valid blocks. -system.l2c.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.843823 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 231.790377 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 51.556644 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.123911 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.843759 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 1.030265 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.831019 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005326 # Average percentage of cache occupancy +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use +system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 429 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits @@ -1061,9 +1061,9 @@ system.l2c.ReadReq_misses::cpu3.inst 9 # nu system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 450 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses @@ -1088,38 +1088,38 @@ system.l2c.overall_misses::cpu2.data 16 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 16 # 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number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 834499 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30956999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) @@ -1132,9 +1132,9 @@ system.l2c.ReadReq_accesses::total 1670 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) @@ -1196,38 +1196,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.640000 # mi system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52373.684211 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52083.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49833.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # 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average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 52156.187500 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52292.228041 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52290.540541 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1264,9 +1264,9 @@ system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # n system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses @@ -1301,15 +1301,15 @@ system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 764491 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560499 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5719499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5719000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles @@ -1317,8 +1317,8 @@ system.l2c.demand_mshr_miss_latency::cpu1.data 897500 system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # 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average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40278.161972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency @@ -1391,8 +1391,8 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency @@ -1400,8 +1400,8 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index e56d497e2..0a30250cf 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,656 +1,654 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000650 # Number of seconds simulated -sim_ticks 649827000 # Number of ticks simulated -final_tick 649827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000653 # Number of seconds simulated +sim_ticks 652606500 # Number of ticks simulated +final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 87337651 # Simulator tick rate (ticks/s) -host_mem_usage 355516 # Number of bytes of host memory used -host_seconds 7.44 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 81682 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82403 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 82634 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 80397 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 83903 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 81493 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 81053 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 80348 # Number of bytes read from this memory -system.physmem.bytes_read::total 653913 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 411392 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5392 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5164 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5249 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5478 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5343 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5429 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5380 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5399 # Number of bytes written to this memory -system.physmem.bytes_written::total 454226 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10933 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11024 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11066 # Number of read requests responded to by this memory +host_tick_rate 176079756 # Simulator tick rate (ticks/s) +host_mem_usage 355636 # Number of bytes of host memory used +host_seconds 3.71 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 79011 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 80501 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 83900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 78451 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 80299 # Number of bytes read from this memory +system.physmem.bytes_read::total 645272 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 398848 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5221 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5261 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5379 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5376 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5284 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5253 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5355 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5238 # Number of bytes written to this memory +system.physmem.bytes_written::total 441215 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10991 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3 11034 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11012 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10870 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10997 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10859 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87795 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6428 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5392 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5164 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5249 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5478 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5343 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5429 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5380 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5399 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49262 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 125698070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 126807596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 127163076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 123720621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 129115903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 125407224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 124730120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 123645216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1006287827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 633079266 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 8297593 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 7946730 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 8077534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 8429936 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 8222188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 8354531 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 8279127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 8308365 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 698995271 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 633079266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 133995663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 134754327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 135240610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 132150557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 137338092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 133761755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 133009247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 131953581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1705283098 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 1705280021 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 84626 # Transaction distribution -system.membus.trans_dist::ReadResp 84624 # Transaction distribution -system.membus.trans_dist::WriteReq 42834 # Transaction distribution -system.membus.trans_dist::WriteResp 42832 # Transaction distribution -system.membus.trans_dist::Writeback 6428 # Transaction distribution -system.membus.trans_dist::UpgradeReq 56782 # Transaction distribution -system.membus.trans_dist::UpgradeResp 46322 # Transaction distribution -system.membus.trans_dist::ReadExReq 48493 # Transaction distribution -system.membus.trans_dist::ReadExResp 3169 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 416110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 416110 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side 1108137 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1108137 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1108137 # Total data (bytes) +system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11072 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88226 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6232 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5221 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5261 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5376 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5284 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5253 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5355 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5238 # Number of write requests responded to by this memory +system.physmem.num_writes::total 48599 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 122606808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 125725073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 124189692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 121069894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 123353047 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 128561392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 120211797 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 123043519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 988761221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 611161550 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 8000227 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 8061519 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 8242333 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 8237736 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 8096763 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 8049261 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 8205557 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 8026276 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 676081222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 611161550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 130607035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 133786593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 132432025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 129307630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 131449809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 136610653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 128417354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 131069795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1664842443 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1664833249 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 85134 # Transaction distribution +system.membus.trans_dist::ReadResp 85128 # Transaction distribution +system.membus.trans_dist::WriteReq 42367 # Transaction distribution +system.membus.trans_dist::WriteResp 42365 # Transaction distribution +system.membus.trans_dist::Writeback 6232 # Transaction distribution +system.membus.trans_dist::UpgradeReq 57414 # Transaction distribution +system.membus.trans_dist::UpgradeResp 46744 # Transaction distribution +system.membus.trans_dist::ReadExReq 48586 # Transaction distribution +system.membus.trans_dist::ReadExResp 3092 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side 417062 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 417062 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side 1086481 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1086481 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1086481 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 287607668 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 44.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 310731500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 47.8 # Layer utilization (%) -system.l2c.replacements 13443 # number of replacements -system.l2c.tagsinuse 785.847638 # Cycle average of tags in use -system.l2c.total_refs 148477 # Total number of references to valid blocks. -system.l2c.sampled_refs 14254 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.416515 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 727.764026 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.053915 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.581472 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.416719 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.244884 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.857651 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.082573 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 6.903381 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 6.943017 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.710707 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.006889 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007404 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007243 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007075 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007673 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.006917 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.006742 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.006780 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.767429 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10664 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10479 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10841 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10758 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10614 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10530 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10691 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10867 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85444 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 73993 # number of Writeback hits -system.l2c.Writeback_hits::total 73993 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 363 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 337 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 327 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 310 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 313 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 326 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 344 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 344 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2664 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1821 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1874 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1837 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1846 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1886 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1867 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1842 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14873 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12485 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12353 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12678 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12604 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12416 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12558 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12709 # number of demand (read+write) hits -system.l2c.demand_hits::total 100317 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12485 # number of overall hits -system.l2c.overall_hits::cpu1 12353 # number of overall hits -system.l2c.overall_hits::cpu2 12678 # number of overall hits -system.l2c.overall_hits::cpu3 12604 # number of overall hits -system.l2c.overall_hits::cpu4 12514 # number of overall hits -system.l2c.overall_hits::cpu5 12416 # number of overall hits -system.l2c.overall_hits::cpu6 12558 # number of overall hits -system.l2c.overall_hits::cpu7 12709 # number of overall hits -system.l2c.overall_hits::total 100317 # number of overall hits -system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 740 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 751 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 714 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 782 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 720 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 737 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 688 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5877 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1987 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1883 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1865 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1791 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1907 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1910 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1895 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1890 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15128 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4230 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4311 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4330 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4249 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4286 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4380 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4201 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4403 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34390 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 4975 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5051 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5081 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 4963 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5068 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5100 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 4938 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5091 # number of demand (read+write) misses -system.l2c.demand_misses::total 40267 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 4975 # number of overall misses -system.l2c.overall_misses::cpu1 5051 # number of overall misses -system.l2c.overall_misses::cpu2 5081 # number of overall misses -system.l2c.overall_misses::cpu3 4963 # number of overall misses -system.l2c.overall_misses::cpu4 5068 # number of overall misses -system.l2c.overall_misses::cpu5 5100 # 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number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 236797000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 226713000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 237470499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1854977497 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 273835999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 278001500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 280185500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 273714998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 279602000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 280728000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 271732000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 280124999 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11472 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11396 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11250 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11428 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11555 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 91321 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 73993 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 73993 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2350 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2220 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2192 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2101 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2220 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2236 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2239 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2234 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17792 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6051 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6185 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6167 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6095 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6186 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6266 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6068 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6245 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 49263 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17460 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17404 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17567 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17582 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17516 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17496 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17800 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 140584 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17460 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17404 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17567 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17582 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17516 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17496 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17800 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 140584 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.065299 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.065960 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.064786 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.062238 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.068621 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.064000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.064491 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.059541 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.064355 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.845532 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.848198 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.850821 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.852451 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.859009 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.854204 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.846360 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.846016 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.850270 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.699058 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.697009 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.702124 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.697129 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.692855 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.699011 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.692320 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.705044 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.698090 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.284937 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.290221 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.286108 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.282518 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.288249 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.291162 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.282236 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.286011 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.286427 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.284937 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.290221 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.286108 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.282518 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.288249 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.291162 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.282236 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.286011 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.286427 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 62204.697987 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61800 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 62104.527297 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61950.278711 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 61886.828645 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 61015.277778 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61084.124830 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 61997.819767 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 61757.273949 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29049.068948 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28979.553903 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 30054.155496 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 28684.254606 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 29557.420031 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28797.905759 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29426.912929 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28887.830688 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29180.691433 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53780.969031 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53878.334493 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53936.489607 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54008.590021 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53944.587028 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54063.242009 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53966.436563 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53933.794913 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53939.444519 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55042.411859 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55038.903187 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55143.770911 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55151.117872 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55170.086819 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55044.705882 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55028.756582 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55023.570811 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55080.462811 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55042.411859 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55038.903187 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55143.770911 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55151.117872 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55170.086819 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55044.705882 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55028.756582 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55023.570811 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55080.462811 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 13397 # number of cycles access was blocked +system.membus.reqLayer0.occupancy 286485584 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 43.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 311361500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 47.7 # Layer utilization (%) +system.l2c.tags.replacements 13254 # number of replacements +system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use +system.l2c.tags.total_refs 149317 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10635 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10552 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10744 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10808 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10723 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10748 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10838 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85773 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 74336 # number of Writeback hits +system.l2c.Writeback_hits::total 74336 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 332 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 322 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 337 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 354 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 332 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 349 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 378 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2757 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1930 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1860 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1868 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1850 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1871 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1809 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1953 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1858 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14999 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12565 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12412 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12612 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12658 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12594 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12557 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12678 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12696 # number of demand (read+write) hits +system.l2c.demand_hits::total 100772 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12565 # number of overall hits +system.l2c.overall_hits::cpu1 12412 # number of overall hits +system.l2c.overall_hits::cpu2 12612 # number of overall hits +system.l2c.overall_hits::cpu3 12658 # number of overall hits +system.l2c.overall_hits::cpu4 12594 # number of overall hits +system.l2c.overall_hits::cpu5 12557 # number of overall hits +system.l2c.overall_hits::cpu6 12678 # number of overall hits +system.l2c.overall_hits::cpu7 12696 # number of overall hits +system.l2c.overall_hits::total 100772 # number of overall hits +system.l2c.ReadReq_misses::cpu0 751 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 742 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 744 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 696 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 727 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 735 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 708 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 698 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5801 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1964 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1929 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1920 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1880 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1830 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1887 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1921 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1963 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15294 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4321 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4353 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4358 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4233 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4361 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4404 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4224 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4317 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34571 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5072 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5095 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5102 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 4929 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5088 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5139 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 4932 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5015 # number of demand (read+write) misses +system.l2c.demand_misses::total 40372 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5072 # number of overall misses +system.l2c.overall_misses::cpu1 5095 # number of overall misses +system.l2c.overall_misses::cpu2 5102 # number of overall misses +system.l2c.overall_misses::cpu3 4929 # number of overall misses +system.l2c.overall_misses::cpu4 5088 # number of overall misses +system.l2c.overall_misses::cpu5 5139 # number of overall misses +system.l2c.overall_misses::cpu6 4932 # number of overall misses +system.l2c.overall_misses::cpu7 5015 # number of overall misses +system.l2c.overall_misses::total 40372 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 46656500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 45888000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 46214500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 43225999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 45481000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 44732500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 43604500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 43142000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 358944999 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 54482000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 56107500 # 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number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 237965000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 227719000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 232651999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1863605497 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 279010999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 280419000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 281173500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 271778498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 280353500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 282697500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 271323500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 275793999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2222550496 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 279010999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 280419000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 281173500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 271778498 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 280353500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 282697500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 271323500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 275793999 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2222550496 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11386 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11294 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11488 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11504 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11450 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11483 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11433 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11536 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91574 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 74336 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 74336 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2296 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2251 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2257 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2234 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2162 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2240 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2270 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2341 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18051 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6251 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6213 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6226 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6083 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6232 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6213 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6177 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6175 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 49570 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17637 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17507 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17714 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17587 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17682 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17610 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17711 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 141144 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17637 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17507 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17714 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17587 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17682 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17610 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17711 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 141144 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.065958 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.065699 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.064763 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.060501 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.063493 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.064008 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.061926 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.060506 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.063348 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.855401 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.856952 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.850687 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.841540 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.846438 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.842411 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.846256 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.838531 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.847266 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.691249 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.700628 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.699968 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.695874 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.699775 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.708836 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.683827 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.699109 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.697418 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.287577 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.291026 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.288021 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.280264 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.287750 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.290405 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.280068 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.283157 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.286034 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.287577 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.291026 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.288021 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.280264 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.287750 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.290405 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.280068 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.283157 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.286034 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 62125.832224 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61843.665768 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 62116.263441 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 62106.320402 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 62559.834938 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 60860.544218 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61588.276836 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 61808.022923 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61876.400448 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 27740.325866 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29086.314152 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 28488.541667 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29653.723404 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28261.475410 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29585.585586 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28866.475794 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29855.068772 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28942.134170 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53773.316131 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53878.015162 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53914.410280 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53993.030711 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53857.486815 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54033.832879 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53910.748106 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53892.054436 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53906.612392 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55010.055008 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55038.076546 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55110.446884 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55138.668695 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55100.923742 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55010.215995 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55012.875101 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54993.818345 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55051.780838 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55010.055008 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55038.076546 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55110.446884 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55138.668695 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55100.923742 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55010.215995 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55012.875101 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54993.818345 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55051.780838 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 13487 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1907 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1906 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.025170 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.076076 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6428 # number of writebacks -system.l2c.writebacks::total 6428 # number of writebacks +system.l2c.writebacks::writebacks 6233 # number of writebacks +system.l2c.writebacks::total 6233 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu0 1 # 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number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1910 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1894 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1889 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15124 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4226 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4305 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4324 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4247 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4284 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4378 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4198 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4400 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34362 # 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number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 176232999 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 179835500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 181021500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 177936499 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 179280500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 183709500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 175748500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 184108999 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1437873997 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 213448999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 216489000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 218323000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 213447998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 218017000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 218634500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 211504500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 218219499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1728084496 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 213448999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 216489000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 218323000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 213447998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 218017000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 218634500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 211504500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 218219499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1728084496 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 406261500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 408851000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 410764500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 410830500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407460500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 403658000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 409230500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 404004500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3261061000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 227401000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 218592500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 221548500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 231869500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 226934000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230334000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226902000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 228628000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1812209500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 633662500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 627443500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 632313000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 642700000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 634394500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 633992000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 636132500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 632632500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5073270500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064773 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.065425 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064268 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061890 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.068006 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.063378 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063616 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.059109 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.063797 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.845106 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.847748 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.850821 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.852451 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.859009 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.854204 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.845913 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.845568 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.850045 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.698397 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.696039 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.701151 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.696801 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.692532 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698691 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.691826 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.704564 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.697521 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.284364 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.289531 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.285433 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.282177 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287737 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.290649 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.281493 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.285562 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.285865 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.284364 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.289531 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.285433 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.282177 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287737 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.290649 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.281493 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.285562 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.285865 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50359.945873 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49936.648501 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50069.127517 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 50016.195775 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49982.580645 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48983.169705 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49182.943604 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49942.166911 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49812.993306 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41052.870091 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41030.286929 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41033.512064 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41078.447795 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41054.798112 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41092.931937 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41129.619852 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41088.141874 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41070.021158 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41702.082111 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41773.635308 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41864.361702 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41896.985872 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41848.856209 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41961.968936 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41864.816579 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41842.954318 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41844.886706 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42990.734945 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42962.691010 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43070.230815 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43059.914868 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 43094.880411 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42945.295620 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42945.076142 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42931.241196 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 43000.012342 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42990.734945 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42962.691010 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43070.230815 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43059.914868 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 43094.880411 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42945.295620 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42945.076142 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42931.241196 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 43000.012342 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu2 736 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 693 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 721 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 731 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 703 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 693 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5756 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1963 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1929 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1920 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1879 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1830 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1887 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1921 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1963 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15292 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4318 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4350 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4355 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4230 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4356 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4398 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4220 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4314 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34541 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5063 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5084 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5091 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 4923 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5077 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5129 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 4923 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5007 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40297 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5063 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5084 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5091 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 4923 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5077 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5129 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 4923 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5007 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40297 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 37430000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 36700000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 36861500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 34765499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 36517000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 35579500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 34789500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 34507000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 287149999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 80503500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 79250000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78828500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 77220000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 75116000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77478500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78872500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80473500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 627742500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 179980999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 181689000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 182122000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 177202499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 181963000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 184511000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 176480500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 180371999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1444320997 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 217410999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 218389000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 218983500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 211967998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 218480000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 220090500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 211270000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 214878999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1731470996 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 217410999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 218389000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 218983500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 211967998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 218480000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 220090500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 211270000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 214878999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1731470996 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 408599000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 409928000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 408199000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 411446500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 412339500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 409840000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 407063000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 414602500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3282017500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 219448000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222166000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 226500000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 227574000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 224253000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 222853000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 225951500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 221581000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1790326500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 628047000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 632094000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 634699000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 639020500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 636592500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 632693000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 633014500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 636183500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5072344000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.065431 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064990 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064067 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.060240 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.062969 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.063659 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.061489 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060073 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.062856 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.854965 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.856952 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.850687 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.841092 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.846438 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.842411 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.846256 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.838531 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.847155 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690769 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.700145 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.699486 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.695381 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.698973 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.707871 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.683180 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.698623 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.696813 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.287067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.290398 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.287400 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.279923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.287128 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.289840 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.279557 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.282706 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285503 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.287067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.290398 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.287400 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.279923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.287128 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.289840 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.279557 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.282706 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285503 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50241.610738 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50083.559783 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 50166.665224 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50647.711512 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48672.366621 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49487.197724 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49793.650794 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49887.074183 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41010.443199 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41083.462934 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41056.510417 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41096.327834 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41046.994536 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41059.088500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41058.042686 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40995.160469 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41050.385823 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41681.565308 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41767.586207 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41819.058553 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41891.843735 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41772.956841 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41953.387904 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41820.023697 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41810.848169 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41814.683912 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42941.141418 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42956.136900 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43013.847967 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43056.672354 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43033.287374 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.996296 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42914.889295 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42915.717795 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42967.739435 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42941.141418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42956.136900 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43013.847967 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43056.672354 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43033.287374 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.996296 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42914.889295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42915.717795 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42967.739435 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -681,163 +679,163 @@ system.l2c.overall_avg_mshr_uncacheable_latency::total inf system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) -system.toL2Bus.throughput 51050793519 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 365486 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 365476 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 42834 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 42830 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 73993 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 28250 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28248 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 155786 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 155781 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118183 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 117760 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118671 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 118343 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 117990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118322 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118461 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 118625 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 946355 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1725217 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1723022 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1747851 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1725043 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1729886 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1731401 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1727521 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1744371 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 13854312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 13854312 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 19319872 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 649780490 # Layer occupancy (ticks) +system.toL2Bus.throughput 51078499831 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 368070 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 368059 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 42367 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 42365 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 74336 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 28719 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28718 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 155928 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 155926 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 118639 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118896 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 119078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 118813 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 119137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 950354 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1731443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1726092 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1741657 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1748194 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1742487 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1735937 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1741406 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1745057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 13912273 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 13912273 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 19421888 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 652560490 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 156586979 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 157373515 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 156968437 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 158243013 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 157751073 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 24.3 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 157263428 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 157858027 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 24.2 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 157862988 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 156564098 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 157250041 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 158148657 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 24.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 157838676 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 157464901 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 158178516 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 157629539 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 24.3 # Layer utilization (%) -system.cpu0.num_reads 98049 # number of read accesses completed -system.cpu0.num_writes 53278 # number of write accesses completed +system.toL2Bus.respLayer7.occupancy 157763244 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 24.2 # Layer utilization (%) +system.cpu0.num_reads 98977 # number of read accesses completed +system.cpu0.num_writes 53590 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 21910 # number of replacements -system.cpu0.l1c.tagsinuse 394.044184 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13156 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22301 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.589929 # Average number of references to valid blocks. -system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 394.044184 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.769618 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.769618 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8471 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8471 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1074 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1074 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9545 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9545 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9545 # number of overall hits -system.cpu0.l1c.overall_hits::total 9545 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35640 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35640 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23074 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23074 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58714 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58714 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58714 # number of overall misses -system.cpu0.l1c.overall_misses::total 58714 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 933901812 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 933901812 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 856280361 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 856280361 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1790182173 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1790182173 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1790182173 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1790182173 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44111 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44111 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24148 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24148 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68259 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68259 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68259 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68259 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807962 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807962 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955524 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.955524 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860165 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860165 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860165 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860165 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26203.754545 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 26203.754545 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37110.182933 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 37110.182933 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 30489.869077 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 30489.869077 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 30489.869077 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 30489.869077 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1011011 # number of cycles access was blocked +system.cpu0.l1c.tags.replacements 21970 # number of replacements +system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks. +system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1118 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1118 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9803 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9803 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9803 # number of overall hits +system.cpu0.l1c.overall_hits::total 9803 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35704 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35704 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23289 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23289 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 58993 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 58993 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 58993 # number of overall misses +system.cpu0.l1c.overall_misses::total 58993 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 937059642 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 937059642 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 866806760 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 866806760 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1803866402 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1803866402 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1803866402 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1803866402 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44389 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44389 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24407 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24407 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68796 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68796 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68796 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68796 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804343 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.804343 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954193 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954193 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.857506 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.857506 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.857506 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.857506 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26245.228602 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 26245.228602 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37219.578342 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 37219.578342 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 30577.634669 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 30577.634669 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 30577.634669 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 30577.634669 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1018391 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61585 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 62068 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.416514 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.407666 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9569 # number of writebacks -system.cpu0.l1c.writebacks::total 9569 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35640 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35640 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23074 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23074 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58714 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58714 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58714 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58714 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 860177811 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 860177811 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 808764395 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 808764395 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1668942206 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1668942206 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1668942206 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1668942206 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 696207485 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 696207485 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1651009618 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1651009618 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2347217103 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2347217103 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807962 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807962 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955524 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955524 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860165 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860165 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860165 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860165 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24135.179882 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24135.179882 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35050.896897 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35050.896897 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28424.944749 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28424.944749 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28424.944749 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28424.944749 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9494 # number of writebacks +system.cpu0.l1c.writebacks::total 9494 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35704 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35704 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23289 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23289 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 58993 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 58993 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 58993 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 58993 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 860700776 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 860700776 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 817560778 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 817560778 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1678261554 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1678261554 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1678261554 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1678261554 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 703193894 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 703193894 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1636775658 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1636775658 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2339969552 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2339969552 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804343 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804343 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954193 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954193 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857506 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.857506 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857506 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.857506 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24106.564419 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24106.564419 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35105.018592 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35105.018592 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28448.486329 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28448.486329 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28448.486329 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28448.486329 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -845,114 +843,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98391 # number of read accesses completed -system.cpu1.num_writes 53060 # number of write accesses completed +system.cpu1.num_reads 99824 # number of read accesses completed +system.cpu1.num_writes 53636 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21908 # number of replacements -system.cpu1.l1c.tagsinuse 394.826417 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13138 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22318 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.588673 # Average number of references to valid blocks. -system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 394.826417 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.771145 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.771145 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8563 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8563 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1113 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1113 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9676 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9676 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9676 # number of overall hits -system.cpu1.l1c.overall_hits::total 9676 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35632 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35632 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23114 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23114 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 58746 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 58746 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 58746 # number of overall misses -system.cpu1.l1c.overall_misses::total 58746 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 934157803 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 934157803 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 854823705 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 854823705 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1788981508 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1788981508 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1788981508 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1788981508 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44195 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44195 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24227 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24227 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68422 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68422 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68422 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68422 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806245 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.806245 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954060 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954060 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.858583 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.858583 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.858583 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.858583 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26216.822042 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 26216.822042 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 36982.941291 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 36982.941291 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 30452.822456 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 30452.822456 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 30452.822456 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 30452.822456 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1014678 # number of cycles access was blocked +system.cpu1.l1c.tags.replacements 22223 # number of replacements +system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks. +system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8757 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8757 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1135 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1135 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9892 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9892 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9892 # number of overall hits +system.cpu1.l1c.overall_hits::total 9892 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36260 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36260 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23033 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23033 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 59293 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 59293 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 59293 # number of overall misses +system.cpu1.l1c.overall_misses::total 59293 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 947629716 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 947629716 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 858813201 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 858813201 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1806442917 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1806442917 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1806442917 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1806442917 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45017 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45017 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24168 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24168 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 69185 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 69185 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 69185 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 69185 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805473 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805473 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953037 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953037 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857021 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857021 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857021 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857021 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26134.299945 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 26134.299945 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 37286.206790 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 37286.206790 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 30466.377431 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 30466.377431 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 30466.377431 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 30466.377431 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1020302 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 61858 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 62395 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.403343 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.352304 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9599 # number of writebacks -system.cpu1.l1c.writebacks::total 9599 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35632 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35632 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23114 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23114 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 58746 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 58746 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 58746 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 58746 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 860390916 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 860390916 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 807278180 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 807278180 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1667669096 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1667669096 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1667669096 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1667669096 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 703500956 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 703500956 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1594898180 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1594898180 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2298399136 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2298399136 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806245 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806245 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954060 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954060 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858583 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.858583 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858583 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.858583 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24146.579367 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24146.579367 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34925.940123 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34925.940123 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28387.789739 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28387.789739 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28387.789739 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28387.789739 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9512 # number of writebacks +system.cpu1.l1c.writebacks::total 9512 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36260 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36260 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23033 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 59293 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 59293 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 59293 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 59293 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 870111848 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 870111848 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 810087173 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 810087173 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1680199021 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1680199021 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1680199021 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1680199021 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 702431869 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 702431869 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1631991143 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1631991143 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2334423012 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2334423012 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805473 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805473 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953037 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953037 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857021 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857021 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857021 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857021 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23996.465747 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23996.465747 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 35170.719099 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 35170.719099 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.223972 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.223972 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.223972 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.223972 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -960,114 +958,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 53426 # number of write accesses completed +system.cpu2.num_reads 99336 # number of read accesses completed +system.cpu2.num_writes 53403 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22360 # number of replacements -system.cpu2.l1c.tagsinuse 394.888678 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13327 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22756 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.585648 # Average number of references to valid blocks. -system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 394.888678 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.771267 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.771267 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8771 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8771 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1101 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1101 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9872 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9872 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9872 # number of overall hits -system.cpu2.l1c.overall_hits::total 9872 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36112 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36112 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22938 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22938 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59050 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59050 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59050 # number of overall misses -system.cpu2.l1c.overall_misses::total 59050 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 945591370 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 945591370 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 849320343 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 849320343 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1794911713 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1794911713 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1794911713 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1794911713 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44883 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44883 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24039 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24039 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68922 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68922 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68922 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68922 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804581 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.804581 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954199 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954199 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.856766 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.856766 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.856766 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.856766 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26184.962616 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 26184.962616 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37026.782762 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 37026.782762 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 30396.472701 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 30396.472701 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 30396.472701 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 30396.472701 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1018235 # number of cycles access was blocked +system.cpu2.l1c.tags.replacements 22214 # number of replacements +system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks. +system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8708 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8708 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1070 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1070 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9778 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9778 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9778 # number of overall hits +system.cpu2.l1c.overall_hits::total 9778 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36160 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36160 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22990 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22990 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59150 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59150 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59150 # number of overall misses +system.cpu2.l1c.overall_misses::total 59150 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 947354858 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 947354858 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 856510547 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 856510547 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1803865405 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1803865405 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1803865405 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1803865405 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44868 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44868 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24060 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24060 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68928 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68928 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68928 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68928 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805920 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805920 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955528 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955528 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858142 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858142 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858142 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858142 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26198.972843 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 26198.972843 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37255.787168 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 37255.787168 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 30496.456551 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 30496.456551 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 30496.456551 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 30496.456551 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1016435 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 62319 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 62092 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.339078 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.369822 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9616 # number of writebacks -system.cpu2.l1c.writebacks::total 9616 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36112 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36112 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22938 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22938 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59050 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59050 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59050 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59050 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 870903925 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 870903925 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 802151745 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 802151745 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1673055670 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1673055670 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1673055670 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1673055670 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 702585995 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 702585995 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1602698265 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1602698265 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2305284260 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2305284260 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804581 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804581 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954199 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954199 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856766 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.856766 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856766 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.856766 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24116.745819 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24116.745819 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34970.430944 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34970.430944 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28332.864860 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28332.864860 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28332.864860 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28332.864860 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9582 # number of writebacks +system.cpu2.l1c.writebacks::total 9582 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36160 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36160 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22990 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22990 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59150 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59150 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59150 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59150 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 870067956 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 870067956 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 807866531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 807866531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1677934487 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1677934487 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1677934487 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1677934487 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 699720514 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 699720514 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1649553128 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1649553128 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2349273642 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2349273642 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805920 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805920 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955528 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955528 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858142 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858142 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858142 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858142 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24061.613827 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24061.613827 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35139.910004 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35139.910004 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28367.446948 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28367.446948 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28367.446948 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28367.446948 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1075,114 +1073,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98539 # number of read accesses completed -system.cpu3.num_writes 53510 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 53536 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 21926 # number of replacements -system.cpu3.l1c.tagsinuse 394.806744 # Cycle average of tags in use -system.cpu3.l1c.total_refs 12847 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22328 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.575376 # Average number of references to valid blocks. -system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 394.806744 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.771107 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.771107 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8426 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8426 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1071 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1071 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9497 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9497 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9497 # number of overall hits -system.cpu3.l1c.overall_hits::total 9497 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35942 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35942 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22767 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22767 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 58709 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 58709 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 58709 # number of overall misses -system.cpu3.l1c.overall_misses::total 58709 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 940164359 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 940164359 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 841530610 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 841530610 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1781694969 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1781694969 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1781694969 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1781694969 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44368 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44368 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 23838 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 23838 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68206 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68206 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68206 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68206 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.810088 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.810088 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955072 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955072 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860760 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860760 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860760 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860760 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26157.819793 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 26157.819793 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 36962.735978 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 36962.735978 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 30347.901838 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 30347.901838 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 30347.901838 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 30347.901838 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1011201 # number of cycles access was blocked +system.cpu3.l1c.tags.replacements 22464 # number of replacements +system.cpu3.l1c.tags.tagsinuse 397.838914 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13424 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.587175 # Average number of references to valid blocks. +system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8781 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8781 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1109 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1109 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9890 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9890 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9890 # number of overall hits +system.cpu3.l1c.overall_hits::total 9890 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36107 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36107 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23001 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23001 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 59108 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 59108 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 59108 # number of overall misses +system.cpu3.l1c.overall_misses::total 59108 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 940989779 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 940989779 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 850325185 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 850325185 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1791314964 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1791314964 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1791314964 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1791314964 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44888 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44888 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24110 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24110 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68998 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68998 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68998 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68998 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804380 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.804380 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954002 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954002 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.856663 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.856663 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.856663 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.856663 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26061.145457 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 26061.145457 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 36969.052867 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 36969.052867 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 30305.795561 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 30305.795561 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 30305.795561 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 30305.795561 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1013074 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61773 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 62000 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.369628 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.339903 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9447 # number of writebacks -system.cpu3.l1c.writebacks::total 9447 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35942 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35942 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22767 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22767 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 58709 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 58709 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 58709 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 58709 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 865819865 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 865819865 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 794633661 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 794633661 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1660453526 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1660453526 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1660453526 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1660453526 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 705869404 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 705869404 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1670668640 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1670668640 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2376538044 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2376538044 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.810088 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.810088 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955072 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955072 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860760 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860760 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860760 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860760 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24089.362445 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24089.362445 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34902.870866 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34902.870866 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28282.776508 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28282.776508 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28282.776508 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28282.776508 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9786 # number of writebacks +system.cpu3.l1c.writebacks::total 9786 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36107 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36107 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23001 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23001 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 59108 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 59108 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 59108 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 59108 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 863727177 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 863727177 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 801703041 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 801703041 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1665430218 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1665430218 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1665430218 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1665430218 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 709371346 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 709371346 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1619504156 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1619504156 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2328875502 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2328875502 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804380 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804380 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954002 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954002 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856663 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.856663 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856663 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.856663 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23921.322098 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23921.322098 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34855.138516 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34855.138516 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28176.054307 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28176.054307 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28176.054307 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28176.054307 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1190,114 +1188,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 98567 # number of read accesses completed -system.cpu4.num_writes 53142 # number of write accesses completed +system.cpu4.num_reads 99830 # number of read accesses completed +system.cpu4.num_writes 54064 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 21884 # number of replacements -system.cpu4.l1c.tagsinuse 394.848687 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13028 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22289 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.584504 # Average number of references to valid blocks. -system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 394.848687 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.771189 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.771189 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8503 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8503 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1105 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1105 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9608 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9608 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9608 # number of overall hits -system.cpu4.l1c.overall_hits::total 9608 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 35561 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 35561 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23022 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23022 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 58583 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 58583 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 58583 # number of overall misses -system.cpu4.l1c.overall_misses::total 58583 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 936314772 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 936314772 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 859386922 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 859386922 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1795701694 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1795701694 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1795701694 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1795701694 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44064 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44064 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24127 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24127 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68191 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68191 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68191 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68191 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807031 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807031 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954201 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954201 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859102 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859102 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859102 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859102 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26329.821209 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 26329.821209 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37328.942837 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 37328.942837 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 30652.265913 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 30652.265913 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 30652.265913 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 30652.265913 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1016374 # number of cycles access was blocked +system.cpu4.l1c.tags.replacements 22082 # number of replacements +system.cpu4.l1c.tags.tagsinuse 393.544066 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13201 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22486 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587076 # Average number of references to valid blocks. +system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8712 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8712 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1102 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1102 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9814 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9814 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9814 # number of overall hits +system.cpu4.l1c.overall_hits::total 9814 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 35977 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 35977 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23176 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23176 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59153 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59153 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59153 # number of overall misses +system.cpu4.l1c.overall_misses::total 59153 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 943945635 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 943945635 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 856485364 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 856485364 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1800430999 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1800430999 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1800430999 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1800430999 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44689 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44689 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24278 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24278 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68967 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68967 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68967 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68967 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805053 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805053 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954609 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.954609 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857700 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857700 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857700 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857700 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26237.474915 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 26237.474915 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 36955.702623 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 36955.702623 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 30436.850185 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 30436.850185 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 30436.850185 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 30436.850185 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1017670 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61728 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 62294 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.465364 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.336565 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9520 # number of writebacks -system.cpu4.l1c.writebacks::total 9520 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35561 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 35561 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23022 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23022 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 58583 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 58583 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 58583 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 58583 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 862769237 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 862769237 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 812030378 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 812030378 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1674799615 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1674799615 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1674799615 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1674799615 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 700729623 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 700729623 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1644067080 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1644067080 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2344796703 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2344796703 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807031 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807031 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954201 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954201 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859102 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859102 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859102 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859102 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24261.669722 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24261.669722 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35271.930241 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35271.930241 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28588.491798 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28588.491798 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28588.491798 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28588.491798 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9622 # number of writebacks +system.cpu4.l1c.writebacks::total 9622 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35977 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 35977 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23176 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23176 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59153 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59153 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59153 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59153 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 867154515 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 867154515 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 807437346 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 807437346 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1674591861 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1674591861 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1674591861 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1674591861 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 707224870 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 707224870 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1620907679 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1620907679 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2328132549 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2328132549 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805053 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805053 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954609 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954609 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857700 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857700 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857700 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857700 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24103.024571 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24103.024571 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34839.374612 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34839.374612 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28309.500127 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28309.500127 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28309.500127 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28309.500127 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1305,114 +1303,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98869 # number of read accesses completed -system.cpu5.num_writes 53477 # number of write accesses completed +system.cpu5.num_reads 99630 # number of read accesses completed +system.cpu5.num_writes 53500 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22131 # number of replacements -system.cpu5.l1c.tagsinuse 394.954130 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13197 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22529 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.585778 # Average number of references to valid blocks. -system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 394.954130 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.771395 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.771395 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8594 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8594 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1100 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1100 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9694 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9694 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9694 # number of overall hits -system.cpu5.l1c.overall_hits::total 9694 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 35827 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 35827 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23090 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23090 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 58917 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 58917 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 58917 # number of overall misses -system.cpu5.l1c.overall_misses::total 58917 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 936035832 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 936035832 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 858178388 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 858178388 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1794214220 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1794214220 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1794214220 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1794214220 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44421 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44421 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24190 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24190 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68611 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68611 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68611 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68611 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806533 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806533 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954527 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954527 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858711 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858711 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858711 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858711 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26126.547911 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 26126.547911 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37166.669034 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 37166.669034 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 30453.251523 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 30453.251523 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 30453.251523 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 30453.251523 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1010232 # number of cycles access was blocked +system.cpu5.l1c.tags.replacements 22051 # number of replacements +system.cpu5.l1c.tags.tagsinuse 395.592742 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13484 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22450 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.600624 # Average number of references to valid blocks. +system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8824 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8824 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1160 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1160 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9984 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9984 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9984 # number of overall hits +system.cpu5.l1c.overall_hits::total 9984 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36108 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36108 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23031 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23031 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59139 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59139 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59139 # number of overall misses +system.cpu5.l1c.overall_misses::total 59139 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 948980493 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 948980493 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 861190152 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 861190152 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1810170645 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1810170645 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1810170645 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1810170645 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44932 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44932 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24191 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24191 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69123 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69123 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69123 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69123 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.803614 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.803614 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952048 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952048 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.855562 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.855562 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.855562 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.855562 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26281.724078 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 26281.724078 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37392.651296 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 37392.651296 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 30608.746259 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 30608.746259 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 30608.746259 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 30608.746259 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1024769 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61688 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 62427 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.376475 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.415477 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9611 # number of writebacks -system.cpu5.l1c.writebacks::total 9611 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35827 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 35827 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23090 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23090 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 58917 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 58917 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 58917 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 58917 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 861924856 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 861924856 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 810652413 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 810652413 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1672577269 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1672577269 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1672577269 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1672577269 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 694440055 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 694440055 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1653385505 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1653385505 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2347825560 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2347825560 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806533 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806533 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954527 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954527 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858711 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858711 # 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average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24145.633904 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35278.884981 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35278.884981 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28481.349854 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28481.349854 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28481.349854 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28481.349854 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1420,114 +1418,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99583 # number of read accesses completed -system.cpu6.num_writes 53438 # number of write accesses completed +system.cpu6.num_reads 99897 # number of read accesses completed +system.cpu6.num_writes 53584 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21939 # number of replacements -system.cpu6.l1c.tagsinuse 394.903585 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13339 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22346 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.596930 # Average number of references to valid blocks. -system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 394.903585 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.771296 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.771296 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8764 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8764 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1067 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1067 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9831 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9831 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9831 # number of overall hits -system.cpu6.l1c.overall_hits::total 9831 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36046 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36046 # 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number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1784076243 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44810 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44810 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23962 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23962 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68772 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68772 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68772 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68772 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804419 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.804419 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955471 # 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average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 30268.849239 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1009249 # number of cycles access was blocked +system.cpu6.l1c.tags.replacements 22385 # number of replacements +system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks. +system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8715 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8715 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1094 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1094 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9809 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9809 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9809 # number of overall hits +system.cpu6.l1c.overall_hits::total 9809 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36235 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36235 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23035 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23035 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 59270 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 59270 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 59270 # number of overall misses +system.cpu6.l1c.overall_misses::total 59270 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 950668375 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 950668375 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 850880053 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 850880053 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1801548428 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1801548428 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1801548428 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1801548428 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44950 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44950 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24129 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24129 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 69079 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 69079 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 69079 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 69079 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806118 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806118 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954660 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954660 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858003 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858003 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858003 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858003 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26236.190838 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 26236.190838 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 36938.574040 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 36938.574040 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 30395.620516 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 30395.620516 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 30395.620516 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 30395.620516 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1011987 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61784 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61933 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.335119 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.340029 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9560 # number of writebacks -system.cpu6.l1c.writebacks::total 9560 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36046 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36046 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22895 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22895 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 58941 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 58941 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 58941 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 58941 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 863686811 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 863686811 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 798668072 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 798668072 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1662354883 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1662354883 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1662354883 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1662354883 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702782954 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702782954 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1637437633 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1637437633 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2340220587 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2340220587 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804419 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804419 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955471 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955471 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857049 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.857049 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857049 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.857049 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 23960.683876 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 23960.683876 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34883.951605 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34883.951605 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28203.710202 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28203.710202 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28203.710202 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28203.710202 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9690 # number of writebacks +system.cpu6.l1c.writebacks::total 9690 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36235 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36235 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23035 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23035 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 59270 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 59270 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 59270 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 59270 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 873220563 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 873220563 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 802141037 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 802141037 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1675361600 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1675361600 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1675361600 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1675361600 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 697661939 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 697661939 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1639994129 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1639994129 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2337656068 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2337656068 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806118 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806118 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954660 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954660 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858003 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858003 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858003 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858003 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24098.815041 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24098.815041 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34822.706186 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34822.706186 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28266.603678 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28266.603678 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28266.603678 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28266.603678 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1535,114 +1533,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99199 # number of read accesses completed -system.cpu7.num_writes 53517 # number of write accesses completed +system.cpu7.num_reads 99207 # number of read accesses completed +system.cpu7.num_writes 53401 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22063 # number of replacements -system.cpu7.l1c.tagsinuse 393.496696 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13289 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22472 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.591358 # Average number of references to valid blocks. -system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 393.496696 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.768548 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.768548 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8670 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8670 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1128 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1128 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9798 # 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number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 860844547 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1794181629 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1794181629 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1794181629 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1794181629 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44596 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44596 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24267 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24267 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68863 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68863 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68863 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68863 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805588 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805588 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953517 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953517 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857717 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857717 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857717 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857717 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25979.432222 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 25979.432222 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37203.187130 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 37203.187130 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 30376.392601 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 30376.392601 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 30376.392601 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 30376.392601 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1011426 # number of cycles access was blocked +system.cpu7.l1c.tags.replacements 22143 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks. +system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8635 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8635 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1078 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1078 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9713 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9713 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9713 # number of overall hits +system.cpu7.l1c.overall_hits::total 9713 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36141 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36141 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23098 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23098 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59239 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59239 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59239 # number of overall misses +system.cpu7.l1c.overall_misses::total 59239 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 942615817 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 942615817 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 859348059 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 859348059 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1801963876 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1801963876 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1801963876 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1801963876 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44776 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44776 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24176 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24176 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68952 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68952 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68952 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68952 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807151 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807151 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955410 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955410 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859134 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859134 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859134 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859134 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26081.619684 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 26081.619684 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37204.435839 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 37204.435839 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 30418.539746 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 30418.539746 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 30418.539746 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 30418.539746 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1024987 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 62031 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 62690 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.305170 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.350088 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9494 # number of writebacks -system.cpu7.l1c.writebacks::total 9494 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35926 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35926 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23139 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23139 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59065 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59065 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59065 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59065 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 859043599 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 859043599 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 813252475 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 813252475 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1672296074 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1672296074 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1672296074 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1672296074 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 693959592 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 693959592 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1654672592 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1654672592 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2348632184 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2348632184 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805588 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805588 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953517 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953517 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857717 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857717 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857717 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857717 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23911.473557 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23911.473557 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35146.396776 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35146.396776 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28312.809176 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28312.809176 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28312.809176 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28312.809176 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9629 # number of writebacks +system.cpu7.l1c.writebacks::total 9629 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36141 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36141 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23098 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23098 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59239 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59239 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59239 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59239 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 865505701 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 865505701 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 810567819 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 810567819 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1676073520 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1676073520 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1676073520 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1676073520 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 711693302 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 711693302 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1603062205 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1603062205 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2314755507 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2314755507 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807151 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807151 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955410 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955410 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859134 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859134 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859134 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859134 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23948.028582 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23948.028582 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35092.554290 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35092.554290 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28293.413461 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28293.413461 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28293.413461 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28293.413461 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index 39565381c..ff9167bb3 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 12296459257 # Simulator tick rate (ticks/s) -host_mem_usage 231220 # Number of bytes of host memory used -host_seconds 8.13 # Real time elapsed on the host +host_tick_rate 29067628326 # Simulator tick rate (ticks/s) +host_mem_usage 231288 # Number of bytes of host memory used +host_seconds 3.44 # Real time elapsed on the host system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory @@ -519,7 +519,5 @@ system.monitor.writeTransHist::17 0 0.00% 100.00% # Hi system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period -system.monitor.readAddrDist::total 16 # Read address distribution -system.monitor.writeAddrDist::total 16 # Write address distribution ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt index d0c130b6b..4db87dea6 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 7576487056 # Simulator tick rate (ticks/s) -host_mem_usage 230980 # Number of bytes of host memory used -host_seconds 13.20 # Real time elapsed on the host +host_tick_rate 14083896029 # Simulator tick rate (ticks/s) +host_mem_usage 231304 # Number of bytes of host memory used +host_seconds 7.10 # Real time elapsed on the host system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory system.physmem.bytes_read::total 64 # Number of bytes read from this memory system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory @@ -376,7 +376,5 @@ system.monitor.writeTransHist::34816-36863 0 0.00% 100.00% # system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period -system.monitor.readAddrDist::total 16 # Read address distribution -system.monitor.writeAddrDist::total 16 # Write address distribution ---------- End Simulation Statistics ---------- |