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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-07 13:05:36 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-07 13:05:36 -0500 |
| commit | 721668156130ffeb9f724ce9efc8f1f0d8c7f6f2 (patch) | |
| tree | ce38f7a2465c13d29e0b5e54ed5b7919b2d3e7ad /tests | |
| parent | f22d3bb9c3a010bfe9681cf7b02e0fc39a694e49 (diff) | |
| download | gem5-721668156130ffeb9f724ce9efc8f1f0d8c7f6f2.tar.xz | |
config: Reduce DRAM controller regression traffic rate
This patch changes the traffic generator period such that it does not
completely saturate the DRAM controller and create an ever-growing
backlog in the queued port.
A separate patch updates the stats.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/quick/se/70.tgen/tgen-simple-dram.cfg | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/quick/se/70.tgen/tgen-simple-dram.cfg b/tests/quick/se/70.tgen/tgen-simple-dram.cfg index a10369bab..7ac7510a2 100644 --- a/tests/quick/se/70.tgen/tgen-simple-dram.cfg +++ b/tests/quick/se/70.tgen/tgen-simple-dram.cfg @@ -21,9 +21,7 @@ # interval. If a specific value is desired, then the min and max can # be set to the same value. STATE 0 100 IDLE -#STATE 1 10000000000 TRACE tests/quick/se/70.tgen/tgen-simple-dram.trc 0 -#STATE 1 1000000000 RANDOM 101 0 134217728 64 2000 2000 0 -STATE 1 1000000000 LINEAR 100 0 134217728 64 2000 2000 0 +STATE 1 1000000000 LINEAR 100 0 134217728 64 30000 30000 0 INIT 0 TRANSITION 0 1 1 TRANSITION 1 1 1 |