diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-30 09:37:06 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-30 09:37:06 -0500 |
| commit | ade53def9252a36a39b2c4bd61196355906f0505 (patch) | |
| tree | b1249ddb339746a2cb9fdc48efa11d1c7c6a0dbe /tests | |
| parent | cfc268ad9e5b83cac551cae118811e5c86382d9e (diff) | |
| download | gem5-ade53def9252a36a39b2c4bd61196355906f0505.tar.xz | |
Ruby: Connect system port in Ruby network test
This patch moves the connection of the system port to create_system in
Ruby.py. Thereby it allows the failing Ruby test (and other Ruby
systems) to run again.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/configs/memtest-ruby.py | 4 | ||||
| -rw-r--r-- | tests/configs/o3-timing-mp-ruby.py | 2 | ||||
| -rw-r--r-- | tests/configs/o3-timing-ruby.py | 3 | ||||
| -rw-r--r-- | tests/configs/rubytest-ruby.py | 3 | ||||
| -rw-r--r-- | tests/configs/simple-atomic-mp-ruby.py | 2 | ||||
| -rw-r--r-- | tests/configs/simple-timing-mp-ruby.py | 3 | ||||
| -rw-r--r-- | tests/configs/simple-timing-ruby.py | 3 |
7 files changed, 7 insertions, 13 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index 2517e7670..49f152017 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -109,10 +109,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): # ruby_port.access_phys_mem = False - -# Connect the system port for loading of binaries etc -system.system_port = system.ruby._sys_port_proxy.port - # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py index b14f0e5b1..6f01167d3 100644 --- a/tests/configs/o3-timing-mp-ruby.py +++ b/tests/configs/o3-timing-mp-ruby.py @@ -46,6 +46,8 @@ for cpu in cpus: # connect memory to membus system.physmem.port = system.membus.port +# Connect the system port for loading of binaries etc +system.system_port = system.membus.port # ----------------------- # run simulation diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py index 07851ae9f..3b6d58b3b 100644 --- a/tests/configs/o3-timing-ruby.py +++ b/tests/configs/o3-timing-ruby.py @@ -43,4 +43,7 @@ system = System(cpu = cpu, system.physmem.port = system.membus.port cpu.connectAllPorts(system.membus) +# Connect the system port for loading of binaries etc +system.system_port = system.membus.port + root = Root(system = system) diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py index a7e598b0a..b63833ccf 100644 --- a/tests/configs/rubytest-ruby.py +++ b/tests/configs/rubytest-ruby.py @@ -105,9 +105,6 @@ for ruby_port in system.ruby._cpu_ruby_ports: # ruby_port.access_phys_mem = False -# Connect the system port for loading of binaries etc -system.system_port = system.ruby._sys_port_proxy.port - # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py index 705f13ef3..f8a7b1d17 100644 --- a/tests/configs/simple-atomic-mp-ruby.py +++ b/tests/configs/simple-atomic-mp-ruby.py @@ -47,6 +47,8 @@ for cpu in cpus: # connect memory to membus system.physmem.port = system.membus.port +# Connect the system port for loading of binaries etc +system.system_port = system.membus.port # ----------------------- # run simulation diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py index 58ca862e1..d57ccea15 100644 --- a/tests/configs/simple-timing-mp-ruby.py +++ b/tests/configs/simple-timing-mp-ruby.py @@ -88,9 +88,6 @@ for (i, cpu) in enumerate(system.cpu): cpu.icache_port = system.ruby._cpu_ruby_ports[i].port cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port -# Connect the system port for loading of binaries etc -system.system_port = system.ruby._sys_port_proxy.port - # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index 359421a49..1d67f6f97 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -85,9 +85,6 @@ assert(len(system.ruby._cpu_ruby_ports) == 1) cpu.icache_port = system.ruby._cpu_ruby_ports[0].port cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port -# Connect the system port for loading of binaries etc -system.system_port = system.ruby._sys_port_proxy.port - # ----------------------- # run simulation # ----------------------- |