diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
| commit | d2b57a7473768e8aff3707916b40b264cab6821c (patch) | |
| tree | f4e64db0a8bb23dd26a1c8f1ec5b887be346f625 /tests | |
| parent | 7c55464aac2bcab15699e563f18a7d3d565d949a (diff) | |
| download | gem5-d2b57a7473768e8aff3707916b40b264cab6821c.tar.xz | |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
Diffstat (limited to 'tests')
27 files changed, 14963 insertions, 14953 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index c7b42033d..0876dc614 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903503 # Number of seconds simulated -sim_ticks 1903503020500 # Number of ticks simulated -final_tick 1903503020500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903548 # Number of seconds simulated +sim_ticks 1903548166500 # Number of ticks simulated +final_tick 1903548166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196271 # Simulator instruction rate (inst/s) -host_op_rate 196271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6657053225 # Simulator tick rate (ticks/s) -host_mem_usage 303260 # Number of bytes of host memory used -host_seconds 285.94 # Real time elapsed on the host -sim_insts 56121257 # Number of instructions simulated -sim_ops 56121257 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 882432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24721216 # Number of bytes read from this memory +host_inst_rate 123505 # Simulator instruction rate (inst/s) +host_op_rate 123505 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4187441182 # Simulator tick rate (ticks/s) +host_mem_usage 303204 # Number of bytes of host memory used +host_seconds 454.59 # Real time elapsed on the host +sim_insts 56143492 # Number of instructions simulated +sim_ops 56143492 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 879488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24796480 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 100416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 648960 # Number of bytes read from this memory -system.physmem.bytes_read::total 29002688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 882432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 100416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982848 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7936064 # Number of bytes written to this memory -system.physmem.bytes_written::total 7936064 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13788 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386269 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 101696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 559552 # Number of bytes read from this memory +system.physmem.bytes_read::total 28986880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 879488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 101696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7925376 # Number of bytes written to this memory +system.physmem.bytes_written::total 7925376 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387445 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1569 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10140 # Number of read requests responded to by this memory -system.physmem.num_reads::total 453167 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124001 # Number of write requests responded to by this memory -system.physmem.num_writes::total 124001 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 463583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12987222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1391994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 340929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15236481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 463583 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4169189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4169189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4169189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 463583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12987222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1391994 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 340929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19405670 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 346253 # number of replacements -system.l2c.tagsinuse 65331.229324 # Cycle average of tags in use -system.l2c.total_refs 2603754 # Total number of references to valid blocks. -system.l2c.sampled_refs 411399 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.329024 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6380524000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53709.821247 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5286.136461 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6105.466815 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 198.491400 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 31.313401 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.819547 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080660 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093162 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003029 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000478 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996875 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 965065 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 779439 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 111820 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 39391 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1895715 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 831921 # number of Writeback hits -system.l2c.Writeback_hits::total 831921 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 73 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 245 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 28 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits +system.physmem.num_reads::cpu1.inst 1589 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8743 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452920 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123834 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123834 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 462026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13026453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1391961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 293952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15227815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 462026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53424 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4163475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4163475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4163475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 462026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13026453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1391961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 293952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19391291 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 346033 # number of replacements +system.l2c.tagsinuse 65330.743124 # Cycle average of tags in use +system.l2c.total_refs 2608063 # Total number of references to valid blocks. +system.l2c.sampled_refs 411178 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.342905 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6380526000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53708.225390 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5276.213951 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 6113.589929 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 198.792297 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 33.921558 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.819522 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.080509 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.093286 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.003033 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000518 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996868 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 970913 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 780748 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 107670 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 39067 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1898398 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 832636 # number of Writeback hits +system.l2c.Writeback_hits::total 832636 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 238 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 165704 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 16093 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 181797 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 965065 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 945143 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 111820 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 55484 # number of demand (read+write) hits -system.l2c.demand_hits::total 2077512 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 965065 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1387261000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1941911500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 514448500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2456360000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3305512500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538108500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3843621000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259011 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014541 # 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mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165312 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165312 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41024.594193 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41433.078394 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42600.703262 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40591.650344 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41764.543151 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43467.944563 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41874.779301 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -348,14 +348,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.468001 # Cycle average of tags in use +system.iocache.tagsinuse 0.468369 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1712293423000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.468001 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.029250 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.029250 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1712293009000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.468369 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.029273 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.029273 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -366,12 +366,12 @@ system.iocache.overall_misses::tsunami.ide 41728 # system.iocache.overall_misses::total 41728 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21012998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21012998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7634627806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7634627806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7655640804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7655640804 # 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number of WriteReq accesses(hits+misses) @@ -390,17 +390,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119392.034091 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183736.710772 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183736.710772 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183465.318347 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183465.318347 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183465.318347 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183465.318347 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7744000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276451.550010 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 276451.550010 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 275789.105732 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 275789.105732 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 201643000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7100 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24752 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1090.704225 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8146.533613 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -416,12 +416,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41728 system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11860000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11860000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5473770000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5473770000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5485630000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5485630000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5485630000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5485630000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9326257976 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9326257976 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9338117976 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9338117976 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9338117976 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9338117976 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -432,12 +432,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131733.009241 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131733.009241 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131461.608512 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131461.608512 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131461.608512 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131461.608512 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224447.871968 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 224447.871968 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9362822 # DTB read hits -system.cpu0.dtb.read_misses 32776 # DTB read misses -system.cpu0.dtb.read_acv 407 # DTB read access violations -system.cpu0.dtb.read_accesses 655429 # DTB read accesses -system.cpu0.dtb.write_hits 6177998 # DTB write hits -system.cpu0.dtb.write_misses 6927 # DTB write misses -system.cpu0.dtb.write_acv 263 # DTB write access violations -system.cpu0.dtb.write_accesses 211643 # DTB write accesses -system.cpu0.dtb.data_hits 15540820 # DTB hits -system.cpu0.dtb.data_misses 39703 # DTB misses -system.cpu0.dtb.data_acv 670 # DTB access violations -system.cpu0.dtb.data_accesses 867072 # DTB accesses -system.cpu0.itb.fetch_hits 1071612 # ITB hits -system.cpu0.itb.fetch_misses 26818 # ITB misses -system.cpu0.itb.fetch_acv 827 # ITB acv -system.cpu0.itb.fetch_accesses 1098430 # ITB accesses +system.cpu0.dtb.read_hits 9377828 # DTB read hits +system.cpu0.dtb.read_misses 33360 # DTB read misses +system.cpu0.dtb.read_acv 521 # DTB read access violations +system.cpu0.dtb.read_accesses 633373 # DTB read accesses +system.cpu0.dtb.write_hits 6221809 # DTB write hits +system.cpu0.dtb.write_misses 7167 # DTB write misses +system.cpu0.dtb.write_acv 341 # DTB write access violations +system.cpu0.dtb.write_accesses 216042 # DTB write accesses +system.cpu0.dtb.data_hits 15599637 # DTB hits +system.cpu0.dtb.data_misses 40527 # DTB misses +system.cpu0.dtb.data_acv 862 # DTB access violations +system.cpu0.dtb.data_accesses 849415 # DTB accesses +system.cpu0.itb.fetch_hits 1073423 # ITB hits +system.cpu0.itb.fetch_misses 26403 # ITB misses +system.cpu0.itb.fetch_acv 1051 # ITB acv +system.cpu0.itb.fetch_accesses 1099826 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,277 +483,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 120285579 # number of cpu cycles simulated +system.cpu0.numCycles 120667689 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13328375 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11156715 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 403301 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 9703007 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5627426 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13362893 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11185412 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 402804 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 9622475 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5627170 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 881916 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 36485 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 30082863 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 67323144 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13328375 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6509342 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12704270 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1925792 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 41150259 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29396 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 190626 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 307717 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 171 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8274450 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 278264 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 85724819 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.785340 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.113356 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 884758 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 37477 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 30221705 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 67571030 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13362893 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6511928 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12734942 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1928304 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 41309111 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 28714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 205220 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 305503 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8304621 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 277902 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 86063714 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.785128 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.113854 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 73020549 85.18% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 838460 0.98% 86.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1676934 1.96% 88.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 765061 0.89% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2646040 3.09% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 584012 0.68% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 626464 0.73% 93.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 965763 1.13% 94.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4601536 5.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 73328772 85.20% 85.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 837915 0.97% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1666262 1.94% 88.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 768356 0.89% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2658731 3.09% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 585060 0.68% 92.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 622966 0.72% 93.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 967713 1.12% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4627939 5.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 85724819 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.110806 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.559694 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 31004655 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 40959879 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11547285 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 992195 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1220804 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 569651 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 39042 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 66162079 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 119714 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1220804 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 32084617 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 16798713 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 20265121 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10859034 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4496528 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 62667463 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6952 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 714166 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1644224 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 41889226 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 75909055 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 75455060 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 453995 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36387256 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5501970 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1564601 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238699 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11969460 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9870474 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6474014 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1213478 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 815744 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55487857 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1996787 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54121133 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 111429 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6732221 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3352698 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1361171 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 85724819 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.631336 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.279357 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 86063714 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.110741 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.559976 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 31149327 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 41124977 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11584676 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 985581 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1219152 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 571369 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 39493 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 66407813 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 120728 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1219152 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 32233219 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 16872016 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 20344281 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10880828 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4514216 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 62880643 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6942 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 700700 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1661735 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 42005938 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 76144064 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 75702119 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 441945 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36517182 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5488748 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1574453 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 239002 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12018911 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9888186 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6523659 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1201517 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 824194 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 55665948 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1995313 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54317533 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 112244 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6696159 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3338542 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1358752 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 86063714 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.631132 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.280124 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 61209229 71.40% 71.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 11417613 13.32% 84.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5048858 5.89% 90.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3283375 3.83% 94.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2508461 2.93% 97.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1248570 1.46% 98.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 634570 0.74% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 321579 0.38% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52564 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 61486843 71.44% 71.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 11432526 13.28% 84.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 5063556 5.88% 90.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3287093 3.82% 94.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2517985 2.93% 97.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1255115 1.46% 98.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 648079 0.75% 99.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 319509 0.37% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53008 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 85724819 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 86063714 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 72995 10.68% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 324242 47.46% 58.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 285988 41.86% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 73354 10.53% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 330176 47.38% 57.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 293358 42.10% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 4465 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37158612 68.66% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60272 0.11% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 18564 0.03% 68.81% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.81% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.81% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.81% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 2231 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9761868 18.04% 86.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6247803 11.54% 98.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 867318 1.60% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3296 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37287239 68.65% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60152 0.11% 68.76% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.76% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15662 0.03% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1646 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9781142 18.01% 86.80% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6293081 11.59% 98.39% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 875315 1.61% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54121133 # Type of FU issued -system.cpu0.iq.rate 0.449939 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 683225 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012624 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 194116788 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 63916247 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 52959668 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 644951 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 312925 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 303605 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 54462198 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 337695 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 568272 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54317533 # Type of FU issued +system.cpu0.iq.rate 0.450141 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 696889 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012830 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 194880881 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 64065914 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53156794 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 627031 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 303977 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 294706 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 54682626 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 328500 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 571695 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1280116 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2462 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12570 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 515440 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1271953 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2828 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12731 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 517788 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18537 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 100807 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18545 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 107284 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1220804 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 12124657 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 860720 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 60917526 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 643294 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9870474 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6474014 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1758330 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 617908 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 8871 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12570 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 212626 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 388253 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 600879 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 53642657 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9419598 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 478476 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1219152 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 12163042 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 861940 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 61112544 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 659342 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9888186 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6523659 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1757966 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 617572 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 9941 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12731 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 210191 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 389993 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 600184 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 53834482 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9436308 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 483050 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3432882 # number of nop insts executed -system.cpu0.iew.exec_refs 15618436 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8560068 # Number of branches executed -system.cpu0.iew.exec_stores 6198838 # Number of stores executed -system.cpu0.iew.exec_rate 0.445961 # Inst execution rate -system.cpu0.iew.wb_sent 53356597 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53263273 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26352404 # num instructions producing a value -system.cpu0.iew.wb_consumers 35613133 # num instructions consuming a value +system.cpu0.iew.exec_nop 3451283 # number of nop insts executed +system.cpu0.iew.exec_refs 15679571 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8587439 # Number of branches executed +system.cpu0.iew.exec_stores 6243263 # Number of stores executed +system.cpu0.iew.exec_rate 0.446138 # Inst execution rate +system.cpu0.iew.wb_sent 53546468 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53451500 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26356174 # num instructions producing a value +system.cpu0.iew.wb_consumers 35593959 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.442807 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.739963 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.442964 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.740468 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7330810 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 635616 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 562628 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 84504015 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.633112 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.546448 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7303960 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 636561 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 562819 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 84844562 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.633202 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.547709 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 64274948 76.06% 76.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8494337 10.05% 86.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4620943 5.47% 91.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2493253 2.95% 94.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1382716 1.64% 96.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 578306 0.68% 96.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 482831 0.57% 97.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 448312 0.53% 97.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1728369 2.05% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 64556270 76.09% 76.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8510919 10.03% 86.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4635841 5.46% 91.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2494817 2.94% 94.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1390539 1.64% 96.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 576056 0.68% 96.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 484846 0.57% 97.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 456978 0.54% 97.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1738296 2.05% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 84504015 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53500498 # Number of instructions committed -system.cpu0.commit.committedOps 53500498 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 84844562 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 53723778 # Number of instructions committed +system.cpu0.commit.committedOps 53723778 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14548932 # Number of memory references committed -system.cpu0.commit.loads 8590358 # Number of loads committed -system.cpu0.commit.membars 216685 # Number of memory barriers committed -system.cpu0.commit.branches 8083038 # Number of branches committed -system.cpu0.commit.fp_insts 301061 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49495422 # Number of committed integer instructions. -system.cpu0.commit.function_calls 700509 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1728369 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14622104 # Number of memory references committed +system.cpu0.commit.loads 8616233 # Number of loads committed +system.cpu0.commit.membars 216543 # Number of memory barriers committed +system.cpu0.commit.branches 8113778 # Number of branches committed +system.cpu0.commit.fp_insts 292474 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49705714 # Number of committed integer instructions. +system.cpu0.commit.function_calls 703203 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1738296 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 143428116 # The number of ROB reads -system.cpu0.rob.rob_writes 122883641 # The number of ROB writes -system.cpu0.timesIdled 1359099 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 34560760 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3686357913 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50400239 # Number of Instructions Simulated -system.cpu0.committedOps 50400239 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 50400239 # Number of Instructions Simulated -system.cpu0.cpi 2.386607 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.386607 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.419005 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.419005 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 70355564 # number of integer regfile reads -system.cpu0.int_regfile_writes 38486142 # number of integer regfile writes -system.cpu0.fp_regfile_reads 150309 # number of floating regfile reads -system.cpu0.fp_regfile_writes 151918 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1870359 # number of misc regfile reads -system.cpu0.misc_regfile_writes 881938 # number of misc regfile writes +system.cpu0.rob.rob_reads 143945633 # The number of ROB reads +system.cpu0.rob.rob_writes 123274808 # The number of ROB writes +system.cpu0.timesIdled 1363780 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 34603975 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3686422279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 50608732 # Number of Instructions Simulated +system.cpu0.committedOps 50608732 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 50608732 # Number of Instructions Simulated +system.cpu0.cpi 2.384325 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.384325 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.419406 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.419406 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 70600527 # number of integer regfile reads +system.cpu0.int_regfile_writes 38607300 # number of integer regfile writes +system.cpu0.fp_regfile_reads 144193 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146198 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1863622 # number of misc regfile reads +system.cpu0.misc_regfile_writes 886886 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -785,245 +785,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 978272 # number of replacements -system.cpu0.icache.tagsinuse 509.990128 # Cycle average of tags in use -system.cpu0.icache.total_refs 7239988 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 978784 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.396921 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23947377000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.990128 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996074 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996074 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 7239988 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7239988 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7239988 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7239988 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7239988 # number of overall hits -system.cpu0.icache.overall_hits::total 7239988 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1034461 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1034461 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1034461 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1034461 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1034461 # number of overall misses -system.cpu0.icache.overall_misses::total 1034461 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16768248492 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 16768248492 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 16768248492 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 16768248492 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 16768248492 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 16768248492 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8274449 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8274449 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8274449 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8274449 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8274449 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8274449 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125019 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125019 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125019 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125019 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125019 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125019 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16209.647819 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16209.647819 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16209.647819 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16209.647819 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16209.647819 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16209.647819 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1517995 # number of cycles access was blocked +system.cpu0.icache.replacements 984085 # number of replacements +system.cpu0.icache.tagsinuse 509.993322 # Cycle average of tags in use +system.cpu0.icache.total_refs 7264923 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984594 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.378598 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23948219000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.993322 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996081 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996081 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 7264923 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7264923 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7264923 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7264923 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7264923 # number of overall hits +system.cpu0.icache.overall_hits::total 7264923 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1039697 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1039697 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1039697 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1039697 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1039697 # number of overall misses +system.cpu0.icache.overall_misses::total 1039697 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16868456488 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 16868456488 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 16868456488 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 16868456488 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 16868456488 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 16868456488 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8304620 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8304620 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8304620 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8304620 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8304620 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8304620 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125195 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125195 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125195 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125195 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125195 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125195 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16224.396616 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16224.396616 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16224.396616 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16224.396616 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1612994 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 159 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 9547.138365 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 9432.713450 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 55484 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 55484 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 55484 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 55484 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 55484 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 55484 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 978977 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 978977 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 978977 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 978977 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 978977 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 978977 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12951368495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12951368495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12951368495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12951368495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12951368495 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12951368495 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.118313 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.118313 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.118313 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.118313 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.118313 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.118313 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13229.492108 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13229.492108 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13229.492108 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13229.492108 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13229.492108 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13229.492108 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54925 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54925 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54925 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54925 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54925 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54925 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 984772 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984772 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 984772 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984772 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 984772 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13041683494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13041683494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13041683494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13041683494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13041683494 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13041683494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.118581 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.118581 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.118581 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13243.353278 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1336500 # number of replacements -system.cpu0.dcache.tagsinuse 506.465908 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11143271 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1336941 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.334901 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 23748000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.465908 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989191 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989191 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6824660 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6824660 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3928020 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3928020 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181318 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 181318 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208014 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208014 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10752680 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10752680 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10752680 # number of overall hits -system.cpu0.dcache.overall_hits::total 10752680 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1708787 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1708787 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1807599 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1807599 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22179 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22179 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 632 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 632 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3516386 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3516386 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3516386 # 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average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9794.303797 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33013.982666 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33013.982666 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33013.982666 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33013.982666 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 743236979 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 140000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 67742 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10971.583050 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 28000 # 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number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3942957 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181355 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 181355 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208341 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208341 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10765525 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10765525 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10765525 # number of overall hits +system.cpu0.dcache.overall_hits::total 10765525 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1719034 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1719034 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1839372 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1839372 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22429 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22429 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 711 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 711 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3558406 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3558406 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3558406 # number of overall misses +system.cpu0.dcache.overall_misses::total 3558406 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46470872000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 46470872000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71479264510 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71479264510 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 406558000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 406558000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6746500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 6746500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117950136510 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117950136510 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117950136510 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117950136510 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8541602 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8541602 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5782329 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5782329 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203784 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203784 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209052 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 209052 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14323931 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14323931 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14323931 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14323931 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.201254 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.201254 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318102 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.318102 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110063 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110063 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003401 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003401 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248424 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248424 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248424 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248424 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27033.131398 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27033.131398 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38860.689686 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38860.689686 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18126.443444 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18126.443444 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9488.748242 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9488.748242 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33146.902436 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33146.902436 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 754476476 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 245500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 70452 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10709.085278 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 27277.777778 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 787469 # number of writebacks -system.cpu0.dcache.writebacks::total 787469 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 665447 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 665447 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1525035 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1525035 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4877 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4877 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2190482 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2190482 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2190482 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2190482 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1043340 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1043340 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 282564 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 282564 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 632 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 632 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1325904 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1325904 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1325904 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1325904 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27425552538 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27425552538 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9314976366 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9314976366 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 247730500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 247730500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4222000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4222000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36740528904 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 36740528904 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36740528904 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 36740528904 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2057449498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2057449498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3512263498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3512263498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122265 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122265 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049265 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049265 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085023 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085023 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003029 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003029 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092922 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092922 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092922 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092922 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26286.304118 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26286.304118 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32965.899287 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32965.899287 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14318.026818 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14318.026818 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6680.379747 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6680.379747 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27709.795659 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27709.795659 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27709.795659 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27709.795659 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 796119 # number of writebacks +system.cpu0.dcache.writebacks::total 796119 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 675047 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 675047 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1552745 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1552745 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5057 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5057 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2227792 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2227792 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2227792 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2227792 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1043987 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1043987 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 286627 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 286627 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17372 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17372 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 711 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 711 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330614 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1330614 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330614 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1330614 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27461612037 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27461612037 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9493856805 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9493856805 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 250184001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 250184001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4525001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4525001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36955468842 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 36955468842 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36955468842 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 36955468842 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1456541500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1456541500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2062903998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2062903998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3519445498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3519445498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049569 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049569 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085247 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085247 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003401 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003401 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092894 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092894 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26304.553636 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26304.553636 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33122.688389 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33122.688389 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14401.565796 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14401.565796 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6364.277075 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6364.277075 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1035,22 +1035,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1316259 # DTB read hits -system.cpu1.dtb.read_misses 12259 # DTB read misses -system.cpu1.dtb.read_acv 114 # DTB read access violations -system.cpu1.dtb.read_accesses 313045 # DTB read accesses -system.cpu1.dtb.write_hits 810694 # DTB write hits -system.cpu1.dtb.write_misses 3210 # DTB write misses -system.cpu1.dtb.write_acv 140 # DTB write access violations -system.cpu1.dtb.write_accesses 130863 # DTB write accesses -system.cpu1.dtb.data_hits 2126953 # DTB hits -system.cpu1.dtb.data_misses 15469 # DTB misses -system.cpu1.dtb.data_acv 254 # DTB access violations -system.cpu1.dtb.data_accesses 443908 # DTB accesses -system.cpu1.itb.fetch_hits 378821 # ITB hits -system.cpu1.itb.fetch_misses 8734 # ITB misses -system.cpu1.itb.fetch_acv 397 # ITB acv -system.cpu1.itb.fetch_accesses 387555 # ITB accesses +system.cpu1.dtb.read_hits 1298594 # DTB read hits +system.cpu1.dtb.read_misses 11503 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 332098 # DTB read accesses +system.cpu1.dtb.write_hits 765153 # DTB write hits +system.cpu1.dtb.write_misses 2957 # DTB write misses +system.cpu1.dtb.write_acv 47 # DTB write access violations +system.cpu1.dtb.write_accesses 125840 # DTB write accesses +system.cpu1.dtb.data_hits 2063747 # DTB hits +system.cpu1.dtb.data_misses 14460 # DTB misses +system.cpu1.dtb.data_acv 53 # DTB access violations +system.cpu1.dtb.data_accesses 457938 # DTB accesses +system.cpu1.itb.fetch_hits 372513 # ITB hits +system.cpu1.itb.fetch_misses 8563 # ITB misses +system.cpu1.itb.fetch_acv 155 # ITB acv +system.cpu1.itb.fetch_accesses 381076 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1063,516 +1063,516 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 10995031 # number of cpu cycles simulated +system.cpu1.numCycles 10640951 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1761936 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1452774 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 65512 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 889011 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 565473 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1701905 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1402674 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 62577 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 862370 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 552113 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 118681 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 6179 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3538328 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8413663 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1761936 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 684154 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1515563 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 337074 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 4688566 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24381 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 85396 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48035 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1081640 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 43091 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 10121394 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.831275 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.201855 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 115027 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5500 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3435420 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 8139615 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1701905 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 667140 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1472350 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 326710 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 4537469 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24627 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 73138 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 47601 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1039363 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 39149 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9806707 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.830005 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.196976 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 8605831 85.03% 85.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 83210 0.82% 85.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 170185 1.68% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 136768 1.35% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 220692 2.18% 91.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 89992 0.89% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 103416 1.02% 92.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 63845 0.63% 93.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 647455 6.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 8334357 84.99% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 78230 0.80% 85.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 173812 1.77% 87.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 130927 1.34% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 215769 2.20% 91.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 90418 0.92% 92.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 98526 1.00% 93.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 62686 0.64% 93.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 621982 6.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 10121394 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.160248 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.765224 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3636179 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4783124 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1407347 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 79113 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 215630 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 78857 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5594 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8201368 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 16988 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 215630 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3774532 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 581193 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3715501 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1338240 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 496296 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7575516 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 44770 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 149873 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 5044245 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9199948 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9159980 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 39968 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 4092104 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 952133 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 317142 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 23346 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1397635 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1414528 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 877825 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 136527 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 116556 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6675821 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 314231 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6372058 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 25577 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1212482 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 668533 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 238569 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 10121394 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.629563 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.309947 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9806707 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.159939 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.764933 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3510066 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 4639401 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1367694 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 78184 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 211361 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 75357 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4832 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 7943726 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 14591 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 211361 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3646380 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 524692 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3638231 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1300485 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 485556 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7343826 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 139 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 57550 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 136110 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 4921664 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 8958013 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 8905584 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52429 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 3978815 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 942849 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 306458 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22346 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1365387 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1395502 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 827989 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 138090 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 96967 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6484639 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 311488 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6173957 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 24546 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1207593 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 679802 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236614 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9806707 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.629565 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.304884 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 7322432 72.35% 72.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1274873 12.60% 84.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 565463 5.59% 90.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 381432 3.77% 94.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 276297 2.73% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 150290 1.48% 98.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 93014 0.92% 99.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 53503 0.53% 99.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4090 0.04% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 7075152 72.15% 72.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1257607 12.82% 84.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 548751 5.60% 90.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 366543 3.74% 94.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 274418 2.80% 97.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 146525 1.49% 98.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 78833 0.80% 99.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 55100 0.56% 99.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 3778 0.04% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 10121394 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9806707 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2751 1.84% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 83898 56.09% 57.93% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 62938 42.07% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2937 2.09% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 77829 55.26% 57.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 60078 42.66% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2823 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3945332 61.92% 61.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 9935 0.16% 62.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 7188 0.11% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1411 0.02% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1374762 21.57% 83.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 831632 13.05% 96.88% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 198975 3.12% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3992 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3816770 61.82% 61.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10118 0.16% 62.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.05% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10095 0.16% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1996 0.03% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1354962 21.95% 84.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 784960 12.71% 96.91% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 191064 3.09% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6372058 # Type of FU issued -system.cpu1.iq.rate 0.579540 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 149587 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023475 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 22982123 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8175044 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6195827 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 58550 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 29266 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 28229 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6488697 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 30125 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 71376 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6173957 # Type of FU issued +system.cpu1.iq.rate 0.580207 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 140844 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.022813 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 22242262 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 7966601 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 5994284 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 77749 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 38725 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 37333 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6270612 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 40197 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 68178 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 250758 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 518 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1865 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 114138 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 253497 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 450 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1694 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 109535 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 364 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 10621 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 346 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8387 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 215630 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 327250 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 19053 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7270048 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 103390 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1414528 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 877825 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 292634 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6157 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4769 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1865 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 31136 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 75519 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 106655 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6299419 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1333225 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 72638 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 211361 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 294243 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 17071 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7057887 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 102198 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1395502 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 827989 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 289869 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6102 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1694 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 30581 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 71547 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 102128 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6103512 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1313696 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 70445 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 279996 # number of nop insts executed -system.cpu1.iew.exec_refs 2150860 # number of memory reference insts executed -system.cpu1.iew.exec_branches 922163 # Number of branches executed -system.cpu1.iew.exec_stores 817635 # Number of stores executed -system.cpu1.iew.exec_rate 0.572933 # Inst execution rate -system.cpu1.iew.wb_sent 6254968 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6224056 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2925555 # num instructions producing a value -system.cpu1.iew.wb_consumers 4065237 # num instructions consuming a value +system.cpu1.iew.exec_nop 261760 # number of nop insts executed +system.cpu1.iew.exec_refs 2085126 # number of memory reference insts executed +system.cpu1.iew.exec_branches 894247 # Number of branches executed +system.cpu1.iew.exec_stores 771430 # Number of stores executed +system.cpu1.iew.exec_rate 0.573587 # Inst execution rate +system.cpu1.iew.wb_sent 6061366 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6031617 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2917806 # num instructions producing a value +system.cpu1.iew.wb_consumers 4086073 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.566079 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.719652 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.566831 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.714086 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1244518 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 75662 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 99560 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9905764 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.601159 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.526173 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1232464 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 74874 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 96289 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9595346 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.599743 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.518608 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 7610675 76.83% 76.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1117297 11.28% 88.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 392466 3.96% 92.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 237967 2.40% 94.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 150669 1.52% 96.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 70627 0.71% 96.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 80896 0.82% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 63718 0.64% 98.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 181449 1.83% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 7360615 76.71% 76.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1091727 11.38% 88.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 382276 3.98% 92.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 236221 2.46% 94.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 149500 1.56% 96.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 68368 0.71% 96.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 77096 0.80% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 48958 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 180585 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9905764 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5954935 # Number of instructions committed -system.cpu1.commit.committedOps 5954935 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 9595346 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 5754744 # Number of instructions committed +system.cpu1.commit.committedOps 5754744 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1927457 # Number of memory references committed -system.cpu1.commit.loads 1163770 # Number of loads committed -system.cpu1.commit.membars 20047 # Number of memory barriers committed -system.cpu1.commit.branches 840841 # Number of branches committed -system.cpu1.commit.fp_insts 27263 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5573216 # Number of committed integer instructions. -system.cpu1.commit.function_calls 89926 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 181449 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1860459 # Number of memory references committed +system.cpu1.commit.loads 1142005 # Number of loads committed +system.cpu1.commit.membars 20259 # Number of memory barriers committed +system.cpu1.commit.branches 814036 # Number of branches committed +system.cpu1.commit.fp_insts 36051 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5384897 # Number of committed integer instructions. +system.cpu1.commit.function_calls 87726 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 180585 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 16822912 # The number of ROB reads -system.cpu1.rob.rob_writes 14613272 # The number of ROB writes -system.cpu1.timesIdled 86532 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 873637 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3796008743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5721018 # Number of Instructions Simulated -system.cpu1.committedOps 5721018 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 5721018 # Number of Instructions Simulated -system.cpu1.cpi 1.921866 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.921866 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.520328 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.520328 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8196384 # number of integer regfile reads -system.cpu1.int_regfile_writes 4468767 # number of integer regfile writes -system.cpu1.fp_regfile_reads 18086 # number of floating regfile reads -system.cpu1.fp_regfile_writes 17123 # number of floating regfile writes -system.cpu1.misc_regfile_reads 275818 # number of misc regfile reads -system.cpu1.misc_regfile_writes 138963 # number of misc regfile writes -system.cpu1.icache.replacements 112877 # number of replacements -system.cpu1.icache.tagsinuse 455.325853 # Cycle average of tags in use -system.cpu1.icache.total_refs 961616 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 113389 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.480682 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1880828738000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 455.325853 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.889308 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.889308 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 961616 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 961616 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 961616 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 961616 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 961616 # number of overall hits -system.cpu1.icache.overall_hits::total 961616 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 120024 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 120024 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 120024 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 120024 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 120024 # number of overall misses -system.cpu1.icache.overall_misses::total 120024 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1993076499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1993076499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1993076499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1993076499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1993076499 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1993076499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1081640 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1081640 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1081640 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1081640 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1081640 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1081640 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110965 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.110965 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110965 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.110965 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110965 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.110965 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16605.649695 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 16605.649695 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16605.649695 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 16605.649695 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16605.649695 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 16605.649695 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 288999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 16310969 # The number of ROB reads +system.cpu1.rob.rob_writes 14184459 # The number of ROB writes +system.cpu1.timesIdled 82580 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 834244 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3796004491 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5534760 # Number of Instructions Simulated +system.cpu1.committedOps 5534760 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 5534760 # Number of Instructions Simulated +system.cpu1.cpi 1.922568 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.922568 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.520138 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.520138 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 7951221 # number of integer regfile reads +system.cpu1.int_regfile_writes 4345022 # number of integer regfile writes +system.cpu1.fp_regfile_reads 24272 # number of floating regfile reads +system.cpu1.fp_regfile_writes 22982 # number of floating regfile writes +system.cpu1.misc_regfile_reads 283160 # number of misc regfile reads +system.cpu1.misc_regfile_writes 134137 # number of misc regfile writes +system.cpu1.icache.replacements 108736 # number of replacements +system.cpu1.icache.tagsinuse 452.848051 # Cycle average of tags in use +system.cpu1.icache.total_refs 924017 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 109246 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.458131 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1880838222000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 452.848051 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.884469 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.884469 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 924017 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 924017 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 924017 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 924017 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 924017 # number of overall hits +system.cpu1.icache.overall_hits::total 924017 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 115346 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 115346 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 115346 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 115346 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 115346 # number of overall misses +system.cpu1.icache.overall_misses::total 115346 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1915256999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1915256999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1915256999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1915256999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1915256999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1915256999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1039363 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1039363 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1039363 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1039363 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1039363 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1039363 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110978 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.110978 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110978 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.110978 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110978 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.110978 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16604.450948 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 16604.450948 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 16604.450948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 16604.450948 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 222999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 50 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 5779.980000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7433.300000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6586 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6586 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6586 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6586 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6586 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6586 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 113438 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 113438 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 113438 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 113438 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 113438 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 113438 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1550619499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1550619499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1550619499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1550619499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1550619499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1550619499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.104876 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.104876 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.104876 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.104876 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.104876 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.104876 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13669.312744 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13669.312744 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13669.312744 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13669.312744 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13669.312744 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13669.312744 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6038 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6038 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6038 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6038 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6038 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6038 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 109308 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 109308 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 109308 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 109308 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 109308 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 109308 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1491398999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1491398999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1491398999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1491398999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1491398999 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1491398999 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105168 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.105168 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.105168 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13644.005919 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 66353 # number of replacements -system.cpu1.dcache.tagsinuse 422.855509 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1693567 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 66865 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 25.328154 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1880297916000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 422.855509 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.825890 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.825890 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1103263 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1103263 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 554602 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 554602 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16904 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16904 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15090 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15090 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1657865 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1657865 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1657865 # number of overall hits -system.cpu1.dcache.overall_hits::total 1657865 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 120863 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 120863 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 188065 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 188065 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1871 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1871 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 714 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 308928 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 308928 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 308928 # number of overall misses -system.cpu1.dcache.overall_misses::total 308928 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2422870500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2422870500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7680920661 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7680920661 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 31721000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 31721000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8263500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 8263500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10103791161 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10103791161 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10103791161 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10103791161 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1224126 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1224126 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 742667 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 742667 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18775 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18775 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15804 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15804 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1966793 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1966793 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1966793 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1966793 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.098734 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.098734 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.253229 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.253229 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099654 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.099654 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.045178 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.045178 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.157072 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.157072 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.157072 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.157072 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20046.420327 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20046.420327 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40841.840114 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 40841.840114 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16954.035275 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16954.035275 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11573.529412 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11573.529412 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32705.974081 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 32705.974081 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32705.974081 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 32705.974081 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 54269989 # number of cycles access was blocked +system.cpu1.dcache.replacements 61811 # number of replacements +system.cpu1.dcache.tagsinuse 423.387508 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1665798 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62157 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 26.799846 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1880297158000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 423.387508 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.826929 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.826929 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1100458 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1100458 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 541491 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 541491 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16674 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 16674 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14757 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 14757 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1641949 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1641949 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1641949 # number of overall hits +system.cpu1.dcache.overall_hits::total 1641949 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 110209 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 110209 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 156496 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 156496 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1520 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1520 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 666 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 666 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 266705 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 266705 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 266705 # number of overall misses +system.cpu1.dcache.overall_misses::total 266705 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2207117500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2207117500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6428377585 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6428377585 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 25057000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 25057000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8004500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 8004500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8635495085 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8635495085 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8635495085 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8635495085 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1210667 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1210667 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 697987 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 697987 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18194 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 18194 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15423 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15423 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1908654 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1908654 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1908654 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1908654 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.091032 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.091032 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224210 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.224210 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083544 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083544 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.043182 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.043182 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.139735 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.139735 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.139735 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.139735 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20026.653903 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20026.653903 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41076.945002 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41076.945002 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16484.868421 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16484.868421 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12018.768769 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12018.768769 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 32378.452166 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 32378.452166 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 48117991 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6147 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4997 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8828.695136 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9629.375825 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 44452 # number of writebacks -system.cpu1.dcache.writebacks::total 44452 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 76735 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 76735 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 160629 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 160629 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 625 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 625 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 237364 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 237364 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 237364 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 237364 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 44128 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 44128 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 27436 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 27436 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1246 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1246 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 712 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 712 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 71564 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 71564 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 71564 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 71564 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 680335003 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 680335003 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 908440847 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 908440847 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 14899501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 14899501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6048501 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6048501 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1588775850 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1588775850 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1588775850 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1588775850 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26654500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26654500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 549434000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 549434000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 576088500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 576088500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036049 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036049 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066365 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066365 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.045052 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.045052 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.036386 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.036386 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036386 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036386 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15417.308806 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15417.308806 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33111.271577 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33111.271577 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11957.865971 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.865971 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8495.085674 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8495.085674 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22200.769242 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22200.769242 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22200.769242 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22200.769242 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 36517 # number of writebacks +system.cpu1.dcache.writebacks::total 36517 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66699 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 66699 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 133155 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 133155 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 347 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 347 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 199854 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 199854 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 199854 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 199854 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43510 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 43510 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23341 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 23341 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1173 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1173 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 665 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 665 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 66851 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 66851 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 66851 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 66851 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 664874003 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 664874003 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 774412476 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 774412476 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13964500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13964500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5940500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5940500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1439286479 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1439286479 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1439286479 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1439286479 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25429000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25429000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 545455000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 545455000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 570884000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 570884000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035939 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035939 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033440 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033440 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064472 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064472 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043117 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043117 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.035025 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035025 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15280.946978 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15280.946978 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33178.204704 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33178.204704 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11904.944587 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.944587 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8933.082707 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8933.082707 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1581,171 +1581,162 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6363 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 198040 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71346 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 130 0.07% 40.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.10% 41.77% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.77% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102331 58.23% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 175740 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69979 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 130 0.09% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.36% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69973 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142015 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862552849000 97.86% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 68272000 0.00% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 582924500 0.03% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4256000 0.00% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40116611000 2.11% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903324912500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980840 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 199157 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71465 40.61% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.10% 41.78% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 9 0.01% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 102444 58.21% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 175976 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70100 49.28% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.35% 50.72% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 9 0.01% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 70091 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 142258 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1862744375000 97.86% 97.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 69542000 0.00% 97.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 583001500 0.03% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5982500 0.00% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 40144359500 2.11% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903547260500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980900 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.683791 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808097 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 5 2.35% 2.35% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.45% 10.80% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.41% 12.21% # number of syscalls executed -system.cpu0.kern.syscall::6 28 13.15% 25.35% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 25.82% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.47% 26.29% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.23% 30.52% # number of syscalls executed -system.cpu0.kern.syscall::19 5 2.35% 32.86% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.88% 34.74% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.94% 35.68% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.88% 37.56% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.29% 40.85% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.94% 41.78% # number of syscalls executed -system.cpu0.kern.syscall::45 38 17.84% 59.62% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.88% 61.50% # number of syscalls executed -system.cpu0.kern.syscall::48 6 2.82% 64.32% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.23% 68.54% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 69.01% # number of syscalls executed -system.cpu0.kern.syscall::59 4 1.88% 70.89% # number of syscalls executed -system.cpu0.kern.syscall::71 32 15.02% 85.92% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.41% 87.32% # number of syscalls executed -system.cpu0.kern.syscall::74 9 4.23% 91.55% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 92.02% # number of syscalls executed -system.cpu0.kern.syscall::90 1 0.47% 92.49% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.29% 95.77% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.94% 96.71% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.94% 97.65% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.94% 98.59% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.06% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.94% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 213 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684188 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808394 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.65% 3.65% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.68% 12.33% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.37% 13.70% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.61% 28.31% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.46% 28.77% # number of syscalls executed +system.cpu0.kern.syscall::17 8 3.65% 32.42% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.57% 36.99% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.74% 39.73% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.46% 40.18% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.37% 41.55% # number of syscalls executed +system.cpu0.kern.syscall::33 6 2.74% 44.29% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.91% 45.21% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.44% 61.64% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.37% 63.01% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.57% 67.58% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.57% 72.15% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.46% 72.60% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.74% 75.34% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.50% 85.84% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.37% 87.21% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.74% 89.95% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.46% 90.41% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.37% 91.78% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.11% 95.89% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.91% 96.80% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.91% 97.72% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.46% 98.17% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.91% 99.09% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.91% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 219 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 103 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 101 0.05% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3753 2.03% 2.09% # number of callpals executed -system.cpu0.kern.callpal::tbi 37 0.02% 2.11% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.12% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169151 91.71% 93.83% # number of callpals executed -system.cpu0.kern.callpal::rdps 6371 3.45% 97.28% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.28% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.28% # number of callpals executed -system.cpu0.kern.callpal::rdusp 6 0.00% 97.29% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.29% # number of callpals executed -system.cpu0.kern.callpal::rti 4525 2.45% 99.74% # number of callpals executed -system.cpu0.kern.callpal::callsys 331 0.18% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 146 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184440 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6935 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1104 # number of protection mode switches +system.cpu0.kern.callpal::swpctx 3850 2.08% 2.14% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 169235 91.57% 93.74% # number of callpals executed +system.cpu0.kern.callpal::rdps 6384 3.45% 97.19% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::rti 4673 2.53% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 133 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 184824 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7179 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1251 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1104 -system.cpu0.kern.mode_good::user 1104 +system.cpu0.kern.mode_good::kernel 1250 +system.cpu0.kern.mode_good::user 1251 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.159193 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.174119 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.274661 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1900909928000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1870692000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.296679 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901642531000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1904721500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3754 # number of times the context was actually changed +system.cpu0.kern.swap_context 3851 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2268 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39512 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10294 33.41% 33.41% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1926 6.25% 39.66% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 103 0.33% 40.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18486 60.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30809 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10284 45.72% 45.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1926 8.56% 54.28% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 103 0.46% 54.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10181 45.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22494 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876458068500 98.58% 98.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533952000 0.03% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 54130500 0.00% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 26455983000 1.39% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903502134000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999029 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2262 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 38430 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10197 33.29% 33.29% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1926 6.29% 39.58% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 101 0.33% 39.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18406 60.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30630 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10185 45.68% 45.68% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1926 8.64% 54.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 101 0.45% 54.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10084 45.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22296 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1876291886000 98.58% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533607500 0.03% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 52904000 0.00% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 26445439500 1.39% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903323837000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998823 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.550741 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.730111 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 3 2.65% 2.65% # number of syscalls executed -system.cpu1.kern.syscall::3 12 10.62% 13.27% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.88% 14.16% # number of syscalls executed -system.cpu1.kern.syscall::6 14 12.39% 26.55% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.31% 31.86% # number of syscalls executed -system.cpu1.kern.syscall::19 5 4.42% 36.28% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.77% 38.05% # number of syscalls executed -system.cpu1.kern.syscall::23 2 1.77% 39.82% # number of syscalls executed -system.cpu1.kern.syscall::24 2 1.77% 41.59% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.54% 45.13% # number of syscalls executed -system.cpu1.kern.syscall::45 16 14.16% 59.29% # number of syscalls executed -system.cpu1.kern.syscall::47 2 1.77% 61.06% # number of syscalls executed -system.cpu1.kern.syscall::48 4 3.54% 64.60% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.88% 65.49% # number of syscalls executed -system.cpu1.kern.syscall::59 3 2.65% 68.14% # number of syscalls executed -system.cpu1.kern.syscall::71 22 19.47% 87.61% # number of syscalls executed -system.cpu1.kern.syscall::74 7 6.19% 93.81% # number of syscalls executed -system.cpu1.kern.syscall::90 2 1.77% 95.58% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.77% 97.35% # number of syscalls executed -system.cpu1.kern.syscall::132 2 1.77% 99.12% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 113 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.547865 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.727914 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.28% 10.28% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.93% 11.21% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.35% 20.56% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.93% 21.50% # number of syscalls executed +system.cpu1.kern.syscall::17 7 6.54% 28.04% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.80% 30.84% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.80% 33.64% # number of syscalls executed +system.cpu1.kern.syscall::33 5 4.67% 38.32% # number of syscalls executed +system.cpu1.kern.syscall::45 18 16.82% 55.14% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.80% 57.94% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.93% 58.88% # number of syscalls executed +system.cpu1.kern.syscall::71 31 28.97% 87.85% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.35% 97.20% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.80% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 107 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wripir 9 0.03% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 478 1.50% 1.53% # number of callpals executed -system.cpu1.kern.callpal::tbi 16 0.05% 1.58% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.60% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26108 81.82% 83.42% # number of callpals executed -system.cpu1.kern.callpal::rdps 2389 7.49% 90.91% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.91% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 90.92% # number of callpals executed -system.cpu1.kern.callpal::rdusp 3 0.01% 90.93% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.94% # number of callpals executed -system.cpu1.kern.callpal::rti 2671 8.37% 99.31% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.58% 99.89% # number of callpals executed -system.cpu1.kern.callpal::imb 34 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.04% # number of callpals executed +system.cpu1.kern.callpal::swpctx 385 1.22% 1.26% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.27% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.29% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26077 82.56% 83.85% # number of callpals executed +system.cpu1.kern.callpal::rdps 2376 7.52% 91.38% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.38% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.02% 91.39% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.40% # number of callpals executed +system.cpu1.kern.callpal::rti 2525 7.99% 99.40% # number of callpals executed +system.cpu1.kern.callpal::callsys 142 0.45% 99.85% # number of callpals executed +system.cpu1.kern.callpal::imb 47 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31908 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1099 # number of protection mode switches -system.cpu1.kern.mode_switch::user 634 # number of protection mode switches +system.cpu1.kern.callpal::total 31584 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 861 # number of protection mode switches +system.cpu1.kern.mode_switch::user 488 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 660 -system.cpu1.kern.mode_good::user 634 +system.cpu1.kern.mode_good::kernel 514 +system.cpu1.kern.mode_good::user 488 system.cpu1.kern.mode_good::idle 26 -system.cpu1.kern.mode_switch_good::kernel 0.600546 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.596980 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.012677 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.348837 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2247097500 0.12% 0.12% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 912883500 0.05% 0.17% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1900342145000 99.83% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 479 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::total 0.302353 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2103355500 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 871184500 0.05% 0.16% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1899849485000 99.84% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 386 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index b2dcfbe50..ab9c5cd0a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,146 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.864443 # Number of seconds simulated -sim_ticks 1864443445500 # Number of ticks simulated -final_tick 1864443445500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.867374 # Number of seconds simulated +sim_ticks 1867373908500 # Number of ticks simulated +final_tick 1867373908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198323 # Simulator instruction rate (inst/s) -host_op_rate 198323 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6987525181 # Simulator tick rate (ticks/s) -host_mem_usage 299164 # Number of bytes of host memory used -host_seconds 266.82 # Real time elapsed on the host -sim_insts 52917560 # Number of instructions simulated -sim_ops 52917560 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 968960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory +host_inst_rate 123272 # Simulator instruction rate (inst/s) +host_op_rate 123272 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4349339718 # Simulator tick rate (ticks/s) +host_mem_usage 299108 # Number of bytes of host memory used +host_seconds 429.35 # Real time elapsed on the host +sim_insts 52926469 # Number of instructions simulated +sim_ops 52926469 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 969792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28501248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7519232 # Number of bytes written to this memory -system.physmem.bytes_written::total 7519232 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15140 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28501568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 969792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7518720 # Number of bytes written to this memory +system.physmem.bytes_written::total 7518720 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15153 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388742 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445332 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117488 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117488 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 519705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13344465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1422563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15286732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 519705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 519705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4032963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4032963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4032963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 519705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13344465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1422563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19319696 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 338394 # number of replacements -system.l2c.tagsinuse 65347.941058 # Cycle average of tags in use -system.l2c.total_refs 2558628 # Total number of references to valid blocks. -system.l2c.sampled_refs 403561 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.340127 # Average number of references to valid blocks. -system.l2c.warmup_cycle 4870004000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53835.098828 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5353.738970 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6159.103260 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.821458 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.081692 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.093980 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.997130 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 1006554 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 827784 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1834338 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 840935 # number of Writeback hits -system.l2c.Writeback_hits::total 840935 # number of Writeback hits +system.physmem.num_reads::total 445337 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117480 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117480 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 519335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13323249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1420330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15262914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 519335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 519335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4026360 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4026360 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4026360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 519335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13323249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1420330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19289275 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 338398 # number of replacements +system.l2c.tagsinuse 65348.140689 # Cycle average of tags in use +system.l2c.total_refs 2559915 # Total number of references to valid blocks. +system.l2c.sampled_refs 403567 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.343222 # Average number of references to valid blocks. +system.l2c.warmup_cycle 4870006000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53844.889123 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5363.726417 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6139.525149 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.821608 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.081844 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.093682 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997133 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 1007783 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 827771 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1835554 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 841020 # number of Writeback hits +system.l2c.Writeback_hits::total 841020 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185458 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185458 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 1006554 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1013242 # number of demand (read+write) hits -system.l2c.demand_hits::total 2019796 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 1006554 # number of overall hits -system.l2c.overall_hits::cpu.data 1013242 # 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1333882500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1333882500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1884635500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1884635500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 3218518000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3218518000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.136032 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.635294 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.635294 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383479 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383479 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014819 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.277541 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.166814 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014819 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.277541 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.166814 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41050.690047 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.939962 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40156.378331 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42200 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42200 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383447 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383447 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166729 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166729 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40155.211960 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41574.074074 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41606.778113 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41606.778113 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41050.690047 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40551.426073 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40570.119350 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41050.690047 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40551.426073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40570.119350 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41867.797539 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -231,14 +231,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.286638 # Cycle average of tags in use +system.iocache.tagsinuse 1.309507 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1711308746000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.286638 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.080415 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.080415 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1711308479000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.309507 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.081844 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.081844 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -249,12 +249,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7639193806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7639193806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7659866804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7659866804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7659866804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7659866804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11464497806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11464497806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11485170804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11485170804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11485170804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11485170804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -273,17 +273,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183846.597179 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183846.597179 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183579.791588 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183579.791588 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183579.791588 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183579.791588 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7379000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275907.244080 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275907.244080 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 275258.737064 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 275258.737064 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 275258.737064 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 275258.737064 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199587000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7110 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24660 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1037.834037 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8093.552311 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -299,12 +299,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5478339000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5478339000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5490015000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5490015000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5490015000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5490015000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9303643992 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9303643992 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9315319992 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9315319992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9315319992 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9315319992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -315,12 +315,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131842.967848 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131842.967848 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131576.153385 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131576.153385 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131576.153385 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131576.153385 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223903.638621 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223903.638621 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223255.122636 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223255.122636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223255.122636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223255.122636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -338,22 +338,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9936242 # DTB read hits -system.cpu.dtb.read_misses 43490 # DTB read misses -system.cpu.dtb.read_acv 516 # DTB read access violations -system.cpu.dtb.read_accesses 957786 # DTB read accesses -system.cpu.dtb.write_hits 6625146 # DTB write hits -system.cpu.dtb.write_misses 10048 # DTB write misses -system.cpu.dtb.write_acv 376 # DTB write access violations -system.cpu.dtb.write_accesses 340602 # DTB write accesses -system.cpu.dtb.data_hits 16561388 # DTB hits -system.cpu.dtb.data_misses 53538 # DTB misses -system.cpu.dtb.data_acv 892 # DTB access violations -system.cpu.dtb.data_accesses 1298388 # DTB accesses -system.cpu.itb.fetch_hits 1339050 # ITB hits -system.cpu.itb.fetch_misses 40176 # ITB misses -system.cpu.itb.fetch_acv 1137 # ITB acv -system.cpu.itb.fetch_accesses 1379226 # ITB accesses +system.cpu.dtb.read_hits 9950205 # DTB read hits +system.cpu.dtb.read_misses 43861 # DTB read misses +system.cpu.dtb.read_acv 493 # DTB read access violations +system.cpu.dtb.read_accesses 957335 # DTB read accesses +system.cpu.dtb.write_hits 6626699 # DTB write hits +system.cpu.dtb.write_misses 9966 # DTB write misses +system.cpu.dtb.write_acv 395 # DTB write access violations +system.cpu.dtb.write_accesses 340478 # DTB write accesses +system.cpu.dtb.data_hits 16576904 # DTB hits +system.cpu.dtb.data_misses 53827 # DTB misses +system.cpu.dtb.data_acv 888 # DTB access violations +system.cpu.dtb.data_accesses 1297813 # DTB accesses +system.cpu.itb.fetch_hits 1339762 # ITB hits +system.cpu.itb.fetch_misses 37185 # ITB misses +system.cpu.itb.fetch_acv 1122 # ITB acv +system.cpu.itb.fetch_accesses 1376947 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -366,277 +366,277 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 124718167 # number of cpu cycles simulated +system.cpu.numCycles 124800831 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14016362 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11699457 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 447467 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10098689 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5905629 # Number of BTB hits +system.cpu.BPredUnit.lookups 14048431 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11726244 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 450741 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10120037 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5916610 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 935083 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44772 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31431497 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71249565 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14016362 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6840712 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13427140 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2133623 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43145521 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33490 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 277896 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 300852 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 229 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8810652 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 301668 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 90022350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.791465 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.121682 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 938783 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45408 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31451408 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71430724 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14048431 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6855393 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13459712 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2155244 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43163669 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 276321 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 306226 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 194 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8835796 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 303984 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 90109445 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.792711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.123252 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 76595210 85.08% 85.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 880275 0.98% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1754034 1.95% 88.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 853758 0.95% 88.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2767447 3.07% 92.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 598798 0.67% 92.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 668363 0.74% 93.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009728 1.12% 94.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4894737 5.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 76649733 85.06% 85.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 882120 0.98% 86.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1758761 1.95% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 855148 0.95% 88.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2774809 3.08% 92.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 597111 0.66% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 671452 0.75% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1010353 1.12% 94.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4909958 5.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 90022350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.112384 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.571285 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32462663 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 42944944 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12200929 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1050932 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1362881 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 612569 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43257 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69997551 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 131864 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1362881 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33604793 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17288612 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21444377 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11497846 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4823839 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66302391 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7264 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 752324 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1793006 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44298032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80385832 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79896368 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 489464 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38124388 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6173636 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1698063 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251025 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12720780 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10525150 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6958577 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1307223 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 920725 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58755274 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2090184 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57106230 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 126003 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7528195 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3871424 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1424917 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 90022350 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.634356 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.284426 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 90109445 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.112567 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.572358 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32486072 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 42966960 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12232972 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1046401 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1377039 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 612715 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43176 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70146735 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 131924 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1377039 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33631618 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17301504 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21458473 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11517889 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4822920 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66414787 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7289 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 750703 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1791896 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44375645 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80516952 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80027527 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 489425 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38131021 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6244616 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1698641 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251106 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12735763 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10548926 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6961519 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1298320 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 905557 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58829539 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2094293 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57137234 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 128634 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7593303 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3942261 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1428853 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 90109445 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.634087 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.284474 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64211383 71.33% 71.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11984837 13.31% 84.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5359973 5.95% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3439210 3.82% 94.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2607784 2.90% 97.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1324300 1.47% 98.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 687470 0.76% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 352783 0.39% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 54610 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64286768 71.34% 71.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11995743 13.31% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5355125 5.94% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3438365 3.82% 94.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2611846 2.90% 97.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1326020 1.47% 98.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 685055 0.76% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 355852 0.39% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 54671 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 90022350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 90109445 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 75162 9.94% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 361865 47.84% 57.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 319378 42.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 75508 9.96% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 363265 47.93% 57.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 319103 42.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38979239 68.26% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61855 0.11% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10375615 18.17% 86.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6703515 11.74% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949472 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38991069 68.24% 68.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61859 0.11% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25608 0.04% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10392240 18.19% 86.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6705676 11.74% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949855 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57106230 # Type of FU issued -system.cpu.iq.rate 0.457882 # Inst issue rate -system.cpu.iq.fu_busy_cnt 756405 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013246 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 204420366 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68047675 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55829438 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 696851 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 339603 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327742 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57490896 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 364448 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598206 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57137234 # Type of FU issued +system.cpu.iq.rate 0.457827 # Inst issue rate +system.cpu.iq.fu_busy_cnt 757876 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013264 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 204573341 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68190814 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55847999 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 697081 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 339930 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327759 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57523312 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 364507 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 597966 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1442254 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2799 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13958 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 583775 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1464590 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2710 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13959 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 585881 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17984 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 104066 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18028 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 111488 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1362881 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12351222 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 868923 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64407898 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 684720 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10525150 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6958577 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1840963 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 621108 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12330 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13958 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 238471 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 421447 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 659918 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56579740 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10008035 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 526489 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1377039 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12355921 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 868580 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64490760 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 689025 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10548926 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6961519 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1842879 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 620807 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12564 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13959 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 241262 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 422502 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 663764 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56606739 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10022317 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 530494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3562440 # number of nop insts executed -system.cpu.iew.exec_refs 16658473 # number of memory reference insts executed -system.cpu.iew.exec_branches 8978804 # Number of branches executed -system.cpu.iew.exec_stores 6650438 # Number of stores executed -system.cpu.iew.exec_rate 0.453661 # Inst execution rate -system.cpu.iew.wb_sent 56268334 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56157180 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27683314 # num instructions producing a value -system.cpu.iew.wb_consumers 37519561 # num instructions consuming a value +system.cpu.iew.exec_nop 3566928 # number of nop insts executed +system.cpu.iew.exec_refs 16674247 # number of memory reference insts executed +system.cpu.iew.exec_branches 8979744 # Number of branches executed +system.cpu.iew.exec_stores 6651930 # Number of stores executed +system.cpu.iew.exec_rate 0.453577 # Inst execution rate +system.cpu.iew.wb_sent 56287349 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56175758 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27690548 # num instructions producing a value +system.cpu.iew.wb_consumers 37534692 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.450273 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737837 # average fanout of values written-back +system.cpu.iew.wb_rate 0.450123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737732 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8193317 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 665267 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 615735 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 88659469 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.632811 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.547834 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8267625 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 665440 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 619184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 88732406 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.632394 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.547937 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67465140 76.09% 76.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8924230 10.07% 86.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4814714 5.43% 91.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2600553 2.93% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1445109 1.63% 96.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 596766 0.67% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 516883 0.58% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 484830 0.55% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1811244 2.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67542246 76.12% 76.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8923750 10.06% 86.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4811841 5.42% 91.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2594320 2.92% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1447946 1.63% 96.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 597901 0.67% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 519027 0.58% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 475014 0.54% 97.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1820361 2.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 88659469 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56104643 # Number of instructions committed -system.cpu.commit.committedOps 56104643 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 88732406 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56113829 # Number of instructions committed +system.cpu.commit.committedOps 56113829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15457698 # Number of memory references committed -system.cpu.commit.loads 9082896 # Number of loads committed -system.cpu.commit.membars 226441 # Number of memory barriers committed -system.cpu.commit.branches 8439531 # Number of branches committed +system.cpu.commit.refs 15459974 # Number of memory references committed +system.cpu.commit.loads 9084336 # Number of loads committed +system.cpu.commit.membars 226495 # Number of memory barriers committed +system.cpu.commit.branches 8440914 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51953528 # Number of committed integer instructions. -system.cpu.commit.function_calls 739583 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1811244 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 51962143 # Number of committed integer instructions. +system.cpu.commit.function_calls 739769 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1820361 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150896568 # The number of ROB reads -system.cpu.rob.rob_writes 129959625 # The number of ROB writes -system.cpu.timesIdled 1384663 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34695817 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3604162300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52917560 # Number of Instructions Simulated -system.cpu.committedOps 52917560 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52917560 # Number of Instructions Simulated -system.cpu.cpi 2.356839 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.356839 # CPI: Total CPI of All Threads -system.cpu.ipc 0.424297 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.424297 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74164887 # number of integer regfile reads -system.cpu.int_regfile_writes 40500361 # number of integer regfile writes -system.cpu.fp_regfile_reads 166351 # number of floating regfile reads -system.cpu.fp_regfile_writes 166958 # number of floating regfile writes -system.cpu.misc_regfile_reads 1995249 # number of misc regfile reads -system.cpu.misc_regfile_writes 947406 # number of misc regfile writes +system.cpu.rob.rob_reads 151043798 # The number of ROB reads +system.cpu.rob.rob_writes 130140767 # The number of ROB writes +system.cpu.timesIdled 1385278 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34691386 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3609940555 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52926469 # Number of Instructions Simulated +system.cpu.committedOps 52926469 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52926469 # Number of Instructions Simulated +system.cpu.cpi 2.358004 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.358004 # CPI: Total CPI of All Threads +system.cpu.ipc 0.424087 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.424087 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74197467 # number of integer regfile reads +system.cpu.int_regfile_writes 40518410 # number of integer regfile writes +system.cpu.fp_regfile_reads 166390 # number of floating regfile reads +system.cpu.fp_regfile_writes 166940 # number of floating regfile writes +system.cpu.misc_regfile_reads 1995246 # number of misc regfile reads +system.cpu.misc_regfile_writes 947641 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -668,245 +668,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1021086 # number of replacements -system.cpu.icache.tagsinuse 509.954176 # Cycle average of tags in use -system.cpu.icache.total_refs 7728678 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1021597 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.565290 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23896761000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.954176 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996004 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996004 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7728679 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7728679 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7728679 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7728679 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7728679 # number of overall hits -system.cpu.icache.overall_hits::total 7728679 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1081971 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1081971 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1081971 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1081971 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1081971 # number of overall misses -system.cpu.icache.overall_misses::total 1081971 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17450602485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17450602485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17450602485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17450602485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17450602485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17450602485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8810650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8810650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8810650 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8810650 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8810650 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8810650 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122803 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122803 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122803 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122803 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122803 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122803 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16128.530695 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16128.530695 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16128.530695 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16128.530695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16128.530695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16128.530695 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1774492 # number of cycles access was blocked +system.cpu.icache.replacements 1022327 # number of replacements +system.cpu.icache.tagsinuse 509.956829 # Cycle average of tags in use +system.cpu.icache.total_refs 7752117 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1022838 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.579027 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23896694000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.956829 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996009 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996009 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7752118 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7752118 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7752118 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7752118 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7752118 # number of overall hits +system.cpu.icache.overall_hits::total 7752118 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1083676 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1083676 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1083676 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1083676 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16124.307901 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16124.307901 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16124.307901 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16124.307901 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1701496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 205 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8656.058537 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9098.909091 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1021838 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1021838 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13459032492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13459032492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13459032492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13459032492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13459032492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13459032492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115978 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115978 # 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number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1826719 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1826719 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1967450 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1967450 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23276 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23276 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7252868 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7252868 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4173229 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4173229 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 190095 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 190095 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 219635 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 213497 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 219640 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219640 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15223668 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15223668 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15223668 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15223668 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.201437 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.201437 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320461 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.320461 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109613 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109613 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000023 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000023 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.249368 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.249368 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.249368 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.249368 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26730.086291 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26730.086291 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38131.155537 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38131.155537 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18388.447328 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18388.447328 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30800 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30800 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32642.061664 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32642.061664 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32642.061664 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32642.061664 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 733938028 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72096 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10180.010375 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.249452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.249452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.249452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.249452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26710.048023 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26710.048023 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38282.475826 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38282.475826 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18401.311854 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18401.311854 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30700 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30700 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32707.293656 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32707.293656 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32707.293656 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32707.293656 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 749837529 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 205000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72763 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10305.203592 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25625 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840935 # number of writebacks -system.cpu.dcache.writebacks::total 840935 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 742319 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 742319 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667295 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1667295 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5261 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5261 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2409614 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2409614 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2409614 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2409614 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084400 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084400 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300155 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300155 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18015 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18015 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 841020 # number of writebacks +system.cpu.dcache.writebacks::total 841020 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 745266 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 745266 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667773 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1667773 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5284 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5284 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2413039 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2413039 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2413039 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2413039 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084268 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084268 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300264 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300264 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18118 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18118 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384555 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384555 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384555 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384555 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28231864000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28231864000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9653593940 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9653593940 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 269637000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 269637000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1384532 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384532 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28231218500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28231218500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9703849435 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9703849435 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 271481500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 271481500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 138000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 138000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37885457940 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37885457940 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37885457940 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37885457940 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423534500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423534500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2001030998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2001030998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3424565498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3424565498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119498 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119498 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048882 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048882 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084413 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084413 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37935067935 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37935067935 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37935067935 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37935067935 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1425162500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1425162500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2002731998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002731998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3427894498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3427894498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119381 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119381 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048893 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048893 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084863 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084863 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000023 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090999 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090999 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090999 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090999 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26034.548137 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26034.548137 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32162.029418 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32162.029418 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14967.360533 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14967.360533 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090946 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090946 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090946 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090946 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26037.122280 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26037.122280 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32317.725185 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32317.725185 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14984.076609 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.076609 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27600 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27600 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27362.912950 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27362.912950 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27362.912950 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27362.912950 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27399.199105 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27399.199105 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27399.199105 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27399.199105 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -915,28 +915,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6425 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211112 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74681 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 133 0.07% 41.03% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1886 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105636 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182336 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73314 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1886 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73315 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148648 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1823792488500 97.82% 97.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 71545000 0.00% 97.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 571672500 0.03% 97.85% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 40006830500 2.15% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1864442536500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981695 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6432 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211195 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74695 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 137 0.08% 41.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1890 1.04% 42.06% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105693 57.94% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182415 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73328 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 137 0.09% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1890 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73331 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148686 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1826702082500 97.82% 97.82% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 72077500 0.00% 97.83% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 572984500 0.03% 97.86% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 40025844000 2.14% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1867372988500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981699 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694034 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815242 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693811 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815097 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -975,29 +975,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175205 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6791 3.54% 96.97% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175272 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6795 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5112 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rti 5118 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192064 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches -system.cpu.kern.mode_switch::user 1735 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2104 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1905 -system.cpu.kern.mode_good::user 1735 +system.cpu.kern.callpal::total 192141 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2108 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.325641 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080798 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393229 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29922134000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2785239500 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1831735155000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080645 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393483 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29935560000 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2782423500 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1834654997000 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 07942a1c8..e2d527772 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538055 # Number of seconds simulated -sim_ticks 2538055224500 # Number of ticks simulated -final_tick 2538055224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.538087 # Number of seconds simulated +sim_ticks 2538087368500 # Number of ticks simulated +final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74782 # Simulator instruction rate (inst/s) -host_op_rate 96192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3131579061 # Simulator tick rate (ticks/s) -host_mem_usage 390232 # Number of bytes of host memory used -host_seconds 810.47 # Real time elapsed on the host -sim_insts 60608338 # Number of instructions simulated -sim_ops 77960937 # Number of ops (including micro ops) simulated +host_inst_rate 75387 # Simulator instruction rate (inst/s) +host_op_rate 96971 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3156986836 # Simulator tick rate (ticks/s) +host_mem_usage 390016 # Number of bytes of host memory used +host_seconds 803.96 # Real time elapsed on the host +sim_insts 60608307 # Number of instructions simulated +sim_ops 77960925 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090192 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797960 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59092 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813110 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717846 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2678413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4769898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54294380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64349 # number of replacements -system.l2c.tagsinuse 51370.291201 # Cycle average of tags in use -system.l2c.total_refs 1966684 # Total number of references to valid blocks. -system.l2c.sampled_refs 129742 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.158422 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2527049892000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36909.964338 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.537302 # Average occupied blocks per requestor +system.l2c.replacements 64372 # number of replacements +system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use +system.l2c.total_refs 1967256 # Total number of references to valid blocks. +system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8186.541319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6225.247998 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563201 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000741 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124917 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094990 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783848 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11547 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 978702 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 387818 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1500728 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits -system.l2c.Writeback_hits::total 608398 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112928 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112928 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 978702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 500746 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613656 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122661 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11547 # number of overall hits -system.l2c.overall_hits::cpu.inst 978702 # number of overall hits -system.l2c.overall_hits::cpu.data 500746 # number of overall hits -system.l2c.overall_hits::total 1613656 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.124757 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094926 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783730 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 123430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 978266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 387692 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1501094 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits +system.l2c.Writeback_hits::total 608347 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits +system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits +system.l2c.overall_hits::cpu.inst 978266 # number of overall hits +system.l2c.overall_hits::cpu.data 500583 # number of overall hits +system.l2c.overall_hits::total 1613985 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2903 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10685 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23113 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133164 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133164 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 133199 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133199 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12372 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143855 # number of demand (read+write) misses -system.l2c.demand_misses::total 156289 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143884 # number of demand (read+write) misses +system.l2c.demand_misses::total 156312 # number of demand (read+write) misses system.l2c.overall_misses::cpu.dtb.walker 61 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu.inst 12372 # number of overall misses -system.l2c.overall_misses::cpu.data 143855 # number of overall misses -system.l2c.overall_misses::total 156289 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3190500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu.inst 12366 # number of overall misses +system.l2c.overall_misses::cpu.data 143884 # number of overall misses +system.l2c.overall_misses::total 156312 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3194000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 658900997 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 562244999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1224396496 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7068682495 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7068682495 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 3190500 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 658485498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 561949499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1223688997 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1101000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1101000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7073691498 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7073691498 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3194000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 658900997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7630927494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8293078991 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 3190500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu.inst 658485498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7635640997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8297380495 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3194000 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32081918388 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5320000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 198827716888 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198833036888 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026679 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015132 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.987079 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.987079 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541115 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541115 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026671 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015120 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088264 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088259 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088259 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.964560 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40466.541176 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40775.015144 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.247849 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.247849 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,9 +332,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15052335 # DTB read hits +system.cpu.checker.dtb.read_hits 15052368 # DTB read hits system.cpu.checker.dtb.read_misses 7317 # DTB read misses -system.cpu.checker.dtb.write_hits 11295995 # DTB write hits +system.cpu.checker.dtb.write_hits 11296020 # DTB write hits system.cpu.checker.dtb.write_misses 2195 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -345,13 +345,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15059652 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11298190 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15059685 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11298215 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26348330 # DTB hits +system.cpu.checker.dtb.hits 26348388 # DTB hits system.cpu.checker.dtb.misses 9512 # DTB misses -system.cpu.checker.dtb.accesses 26357842 # DTB accesses -system.cpu.checker.itb.inst_hits 61787107 # ITB inst hits +system.cpu.checker.dtb.accesses 26357900 # DTB accesses +system.cpu.checker.itb.inst_hits 61787075 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -368,36 +368,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61791578 # ITB inst accesses -system.cpu.checker.itb.hits 61787107 # DTB hits +system.cpu.checker.itb.inst_accesses 61791546 # ITB inst accesses +system.cpu.checker.itb.hits 61787075 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61791578 # DTB accesses -system.cpu.checker.numCycles 78251513 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61791546 # DTB accesses +system.cpu.checker.numCycles 78251500 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51779226 # DTB read hits -system.cpu.dtb.read_misses 81574 # DTB read misses -system.cpu.dtb.write_hits 11882622 # DTB write hits -system.cpu.dtb.write_misses 18093 # DTB write misses +system.cpu.dtb.read_hits 51778790 # DTB read hits +system.cpu.dtb.read_misses 81353 # DTB read misses +system.cpu.dtb.write_hits 11881898 # DTB write hits +system.cpu.dtb.write_misses 18166 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8066 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3293 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 606 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 8033 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1237 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860800 # DTB read accesses -system.cpu.dtb.write_accesses 11900715 # DTB write accesses +system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51860143 # DTB read accesses +system.cpu.dtb.write_accesses 11900064 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63661848 # DTB hits -system.cpu.dtb.misses 99667 # DTB misses -system.cpu.dtb.accesses 63761515 # DTB accesses -system.cpu.itb.inst_hits 13144692 # ITB inst hits -system.cpu.itb.inst_misses 11967 # ITB inst misses +system.cpu.dtb.hits 63660688 # DTB hits +system.cpu.dtb.misses 99519 # DTB misses +system.cpu.dtb.accesses 63760207 # DTB accesses +system.cpu.itb.inst_hits 13142674 # ITB inst hits +system.cpu.itb.inst_misses 12012 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -406,122 +406,122 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5259 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5318 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13156659 # ITB inst accesses -system.cpu.itb.hits 13144692 # DTB hits -system.cpu.itb.misses 11967 # DTB misses -system.cpu.itb.accesses 13156659 # DTB accesses -system.cpu.numCycles 487285069 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154686 # ITB inst accesses +system.cpu.itb.hits 13142674 # DTB hits +system.cpu.itb.misses 12012 # DTB misses +system.cpu.itb.accesses 13154686 # DTB accesses +system.cpu.numCycles 487300785 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15533008 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12472748 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753945 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10621013 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369898 # Number of BTB hits +system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450891 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 81082 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33390116 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101781554 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15533008 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9820789 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22319812 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6080499 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158808 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102222011 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133571 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 207903 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13140422 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021772 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6316 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134680 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140314971 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367844 0.84% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761669 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2653320 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2361626 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142802 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2916048 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808288 0.50% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9291255 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031877 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208875 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35567426 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101892214 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20037549 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109983 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010651 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100654 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174914 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316762 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572114 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010651 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37681511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40491658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54797467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18895098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6741438 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110776004 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22866 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1160313 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487001 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30716 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115615239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507028919 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506935731 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93188 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747197 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36868041 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898954 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797959 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13563069 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21067127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13877132 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956196 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2590406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101357427 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126494913 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 198538 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24680718 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65543860 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514575 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162617823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777866 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488052 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116473756 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14895850 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7383355 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6325930 3.89% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12628751 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810327 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536412 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438084 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125358 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162617823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53829 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available @@ -549,13 +549,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366722 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411335 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100692 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95407 0.08% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued @@ -568,10 +568,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued @@ -583,361 +583,361 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53419362 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12513627 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126494913 # Type of FU issued -system.cpu.iq.rate 0.259591 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8831890 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069820 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424714403 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128119104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467949 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12866 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10326 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134951003 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 645792 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued +system.cpu.iq.rate 0.259577 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5347388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11096 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2076739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107215 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052024 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010651 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30083339 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540488 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103672693 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219471 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21067127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13877132 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126042 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41068 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376458 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332668 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709126 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123289616 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469824 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3205297 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255493 # number of nop insts executed -system.cpu.iew.exec_refs 64863659 # number of memory reference insts executed -system.cpu.iew.exec_branches 11931891 # Number of branches executed -system.cpu.iew.exec_stores 12393835 # Number of stores executed -system.cpu.iew.exec_rate 0.253013 # Inst execution rate -system.cpu.iew.wb_sent 121912605 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87478275 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47524907 # num instructions producing a value -system.cpu.iew.wb_consumers 86445005 # num instructions consuming a value +system.cpu.iew.exec_nop 255111 # number of nop insts executed +system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed +system.cpu.iew.exec_branches 11930392 # Number of branches executed +system.cpu.iew.exec_stores 12393079 # Number of stores executed +system.cpu.iew.exec_rate 0.253002 # Inst execution rate +system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47523827 # num instructions producing a value +system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179522 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549770 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24740610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545198 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625619 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158689613 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492227 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459221 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130476861 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14004142 8.82% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942589 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238161 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2017118 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1061710 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402075 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657613 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889344 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158689613 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758719 # Number of instructions committed -system.cpu.commit.committedOps 78111318 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60758688 # Number of instructions committed +system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520132 # Number of memory references committed -system.cpu.commit.loads 15719739 # Number of loads committed -system.cpu.commit.membars 413350 # Number of memory barriers committed -system.cpu.commit.branches 10163894 # Number of branches committed +system.cpu.commit.refs 27520186 # Number of memory references committed +system.cpu.commit.loads 15719769 # Number of loads committed +system.cpu.commit.membars 413359 # Number of memory barriers committed +system.cpu.commit.branches 10163898 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148099 # Number of committed integer instructions. -system.cpu.commit.function_calls 996264 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889344 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. +system.cpu.commit.function_calls 996262 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256736769 # The number of ROB reads -system.cpu.rob.rob_writes 209812510 # The number of ROB writes -system.cpu.timesIdled 1906775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324667246 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588737338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608338 # Number of Instructions Simulated -system.cpu.committedOps 77960937 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608338 # Number of Instructions Simulated -system.cpu.cpi 8.039902 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.039902 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124380 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124380 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558055788 # number of integer regfile reads -system.cpu.int_regfile_writes 90157821 # number of integer regfile writes -system.cpu.fp_regfile_reads 8288 # number of floating regfile reads -system.cpu.fp_regfile_writes 2908 # number of floating regfile writes -system.cpu.misc_regfile_reads 134082325 # number of misc regfile reads -system.cpu.misc_regfile_writes 913357 # number of misc regfile writes -system.cpu.icache.replacements 991945 # number of replacements -system.cpu.icache.tagsinuse 511.576100 # Cycle average of tags in use -system.cpu.icache.total_refs 12062971 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992457 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.154654 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225347000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.576100 # Average occupied blocks per requestor +system.cpu.rob.rob_reads 256700614 # The number of ROB reads +system.cpu.rob.rob_writes 209796185 # The number of ROB writes +system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60608307 # Number of Instructions Simulated +system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated +system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 558050325 # number of integer regfile reads +system.cpu.int_regfile_writes 90161621 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads +system.cpu.misc_regfile_writes 913390 # number of misc regfile writes +system.cpu.icache.replacements 991554 # number of replacements +system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use +system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12062971 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12062971 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12062971 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12062971 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12062971 # number of overall hits -system.cpu.icache.overall_hits::total 12062971 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1077319 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1077319 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1077319 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1077319 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1077319 # number of overall misses -system.cpu.icache.overall_misses::total 1077319 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16672871489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16672871489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16672871489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16672871489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16672871489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16672871489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13140290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13140290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13140290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13140290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081986 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081986 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081986 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081986 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2904990 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits +system.cpu.icache.overall_hits::total 12061582 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1076715 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1076715 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1076715 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1076715 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1076715 # number of overall misses +system.cpu.icache.overall_misses::total 1076715 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16664677991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16664677991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16664677991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16664677991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 436 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 446 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6662.821101 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84824 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84824 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84824 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84824 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84824 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84824 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992495 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 992495 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 992495 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 992495 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 992495 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 992495 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12649346990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12649346990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12649346990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12649346990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84611 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992104 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 992104 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 992104 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 992104 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 992104 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 992104 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12645073993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12645073993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12645073993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12645073993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644089 # number of replacements -system.cpu.dcache.tagsinuse 511.991456 # Cycle average of tags in use -system.cpu.dcache.total_refs 21738846 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644601 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724499 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991456 # Average occupied blocks per requestor +system.cpu.dcache.replacements 643955 # number of replacements +system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use +system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908205 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13908205 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258424 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258424 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283313 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283313 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285772 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285772 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21166629 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21166629 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21166629 # number of overall hits -system.cpu.dcache.overall_hits::total 21166629 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 766922 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 766922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2994004 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2994004 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13808 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13808 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3759495 # number of overall misses +system.cpu.dcache.overall_misses::total 3759495 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14876538000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14876538000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129441839072 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129441839072 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224157500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224157500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 359000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 359000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144318377072 # 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number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24926244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24926244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24926244 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24926244 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052182 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052182 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292007 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292007 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046437 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046437 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150825 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150825 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150825 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150825 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19428.423293 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19428.423293 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43236.852036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43236.852036 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16228.009846 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16228.009846 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22437.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 22437.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38387.702889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38387.702889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33577415 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7376000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7440 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4513.093414 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26063.604240 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608398 # number of writebacks -system.cpu.dcache.writebacks::total 608398 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 380638 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 380638 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2745107 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2745107 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1447 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3125745 # 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number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744878 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1442 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1442 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3124452 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3124452 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3124452 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3124452 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386136 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386136 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248907 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248907 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12371 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12371 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635043 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -959,16 +959,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323890643510 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index b2358caab..37534da99 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,71 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.617033 # Number of seconds simulated -sim_ticks 2617033170500 # Number of ticks simulated -final_tick 2617033170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.617165 # Number of seconds simulated +sim_ticks 2617165375500 # Number of ticks simulated +final_tick 2617165375500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88113 # Simulator instruction rate (inst/s) -host_op_rate 113402 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3655705591 # Simulator tick rate (ticks/s) -host_mem_usage 391256 # Number of bytes of host memory used -host_seconds 715.88 # Real time elapsed on the host -sim_insts 63077791 # Number of instructions simulated -sim_ops 81181923 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4357428 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5244336 # Number of bytes read from this memory -system.physmem.bytes_read::total 131535204 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 820992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4255104 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7284240 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81969 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301800 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66486 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823770 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46277796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1665026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 162456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2003924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50261191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 162456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1625927 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1150974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2783396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1625927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46277796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1671522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 162456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3154898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53044587 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 89131 # Simulator instruction rate (inst/s) +host_op_rate 114699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3698456604 # Simulator tick rate (ticks/s) +host_mem_usage 391036 # Number of bytes of host memory used +host_seconds 707.64 # Real time elapsed on the host +sim_insts 63072219 # Number of instructions simulated +sim_ops 81165616 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -84,237 +29,310 @@ system.realview.nvmem.bw_inst_read::total 171 # I system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72594 # number of replacements -system.l2c.tagsinuse 53100.305923 # Cycle average of tags in use -system.l2c.total_refs 1970249 # Total number of references to valid blocks. -system.l2c.sampled_refs 137794 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.298511 # Average number of references to valid blocks. +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 388160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4317812 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 434112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5305072 # Number of bytes read from this memory +system.physmem.bytes_read::total 131557540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 388160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 434112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4272576 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7301712 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6783 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82918 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302149 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66759 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824043 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46275459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 148313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1649805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 165871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2027030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50267186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 148313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 165871 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1632520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1150915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2789931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1632520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46275459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 148313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1656300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 165871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3177945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53057118 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72943 # number of replacements +system.l2c.tagsinuse 53116.867697 # Cycle average of tags in use +system.l2c.total_refs 1971460 # Total number of references to valid blocks. +system.l2c.sampled_refs 138142 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.271257 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37791.704596 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 4.504480 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.004560 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4202.741800 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2939.105076 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 13.484693 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4025.080355 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4123.680364 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.576656 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37786.311031 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 4.267723 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000236 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4199.901742 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2938.535340 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 12.943065 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.004375 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4043.458423 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4131.445760 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.576573 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000065 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064129 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.044847 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061418 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062922 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.810246 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 54561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5750 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 401038 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165879 # 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mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.840125 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.849717 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.845295 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783515 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.813278 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.795954 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618358 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.533183 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567818 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000203 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.217465 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091859 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40411.328872 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40388.960103 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40404.341603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40734.530859 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.288451 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.098817 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.500000 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40019.795658 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.245675 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40016.164585 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41094.922774 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40730.693596 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40895.030032 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40423.935251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40727.858238 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.058335 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40026.889669 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40027.883460 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.546261 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.054422 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40017.066086 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41076.199160 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40760.780552 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40900.455825 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -507,27 +537,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9087709 # DTB read hits -system.cpu0.dtb.read_misses 37707 # DTB read misses -system.cpu0.dtb.write_hits 5292852 # DTB write hits -system.cpu0.dtb.write_misses 6797 # DTB write misses +system.cpu0.dtb.read_hits 7439931 # DTB read hits +system.cpu0.dtb.read_misses 24509 # DTB read misses +system.cpu0.dtb.write_hits 4439969 # DTB write hits +system.cpu0.dtb.write_misses 3332 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2252 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1465 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1349 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9125416 # DTB read accesses -system.cpu0.dtb.write_accesses 5299649 # DTB write accesses +system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7464440 # DTB read accesses +system.cpu0.dtb.write_accesses 4443301 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14380561 # DTB hits -system.cpu0.dtb.misses 44504 # DTB misses -system.cpu0.dtb.accesses 14425065 # DTB accesses -system.cpu0.itb.inst_hits 4426363 # ITB inst hits -system.cpu0.itb.inst_misses 5791 # ITB inst misses +system.cpu0.dtb.hits 11879900 # DTB hits +system.cpu0.dtb.misses 27841 # DTB misses +system.cpu0.dtb.accesses 11907741 # DTB accesses +system.cpu0.itb.inst_hits 3552097 # ITB inst hits +system.cpu0.itb.inst_misses 3937 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -536,542 +566,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1409 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1661 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 929 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4432154 # ITB inst accesses -system.cpu0.itb.hits 4426363 # DTB hits -system.cpu0.itb.misses 5791 # DTB misses -system.cpu0.itb.accesses 4432154 # DTB accesses -system.cpu0.numCycles 73540541 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 3556034 # ITB inst accesses +system.cpu0.itb.hits 3552097 # DTB hits +system.cpu0.itb.misses 3937 # DTB misses +system.cpu0.itb.accesses 3556034 # DTB accesses +system.cpu0.numCycles 63548405 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6354280 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4863798 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 316535 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 4079773 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3047693 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5090505 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 3902323 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 231356 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3310708 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2517095 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 700511 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 30883 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12981968 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33339853 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6354280 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3748204 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7827899 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1608255 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 88516 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 23525864 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 77679 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 91798 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4424514 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 175463 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2818 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 45755598 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.940589 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.320885 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 576022 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 23707 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 10651881 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 26843573 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5090505 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3093117 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 6356133 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1209317 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66372 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20477375 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 36616 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 72183 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 3550824 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 136175 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2156 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 38533087 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.905766 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.281431 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 37936221 82.91% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 625086 1.37% 84.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 819758 1.79% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 695394 1.52% 87.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 800497 1.75% 89.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 578636 1.26% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 719119 1.57% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 370554 0.81% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3210333 7.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 32183362 83.52% 83.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 497864 1.29% 84.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 649099 1.68% 86.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 569855 1.48% 87.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 713173 1.85% 89.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 461238 1.20% 91.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 562037 1.46% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 306432 0.80% 93.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2590027 6.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 45755598 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086405 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.453353 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13479181 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 23559009 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7020718 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 606128 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1090562 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 996028 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66487 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41577642 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 218603 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1090562 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14092626 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6784553 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14469405 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6963849 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2354603 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40318960 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2633 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 472928 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1334672 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 351 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40667832 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 182121697 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 182086780 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34917 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31702592 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8965239 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 463825 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 419023 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5696158 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7936117 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5894118 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139492 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1233570 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 38069002 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 950684 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38295497 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6802670 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14391567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 261548 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 45755598 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.836958 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.462966 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 38533087 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.080104 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.422411 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 11016691 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20495843 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 5693231 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512184 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 815138 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 784502 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 52422 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 33794983 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 170156 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 815138 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 11512212 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6110309 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12456624 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 5662288 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1976516 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 32836773 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1958 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 434728 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1081609 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 147 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 32827027 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 148293172 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 148253410 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 39762 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 25938752 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6888275 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 379434 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 344458 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4684493 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6313022 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4948082 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 931233 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 932024 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 31038582 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 848484 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 31613010 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 68951 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5311616 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10469723 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 281141 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 38533087 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.820412 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.447904 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 29855724 65.25% 65.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6336412 13.85% 79.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3245721 7.09% 86.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2523061 5.51% 91.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2111675 4.62% 96.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 936021 2.05% 98.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 511535 1.12% 99.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 181147 0.40% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54302 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 25332313 65.74% 65.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5318332 13.80% 79.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2653261 6.89% 86.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2120070 5.50% 91.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1758280 4.56% 96.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 743996 1.93% 98.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 416585 1.08% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 146664 0.38% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 43586 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 45755598 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 38533087 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27761 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 835942 77.99% 80.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207752 19.38% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 17185 1.90% 1.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.05% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 711308 78.54% 80.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 176706 19.51% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 23003680 60.07% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50163 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9567598 24.98% 85.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5620993 14.68% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 39793 0.13% 0.13% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 18975009 60.02% 60.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 42063 0.13% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 2 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 2 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 627 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7818427 24.73% 85.02% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4737084 14.98% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38295497 # Type of FU issued -system.cpu0.iq.rate 0.520740 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1071919 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.027991 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 123548516 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45830842 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35351164 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8368 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39310727 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4345 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 327037 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 31613010 # Type of FU issued +system.cpu0.iq.rate 0.497463 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 905651 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028648 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 102751361 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 37203152 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 29110459 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 9929 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5392 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4352 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 32473546 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5322 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 253493 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1508258 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3980 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13847 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 614652 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1084760 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3550 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10332 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 476904 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149655 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5288 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1893731 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4858 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1090562 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4675196 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 127491 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39158193 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 88903 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7936117 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5894118 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 617815 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 49276 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17780 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13847 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 160769 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144529 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 305298 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37872918 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9405503 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 422579 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 815138 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4299477 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 104449 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 31945570 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 72737 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 6313022 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 4948082 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 576088 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 33936 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17434 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10332 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 115531 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 108245 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 223776 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 31278568 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7699224 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 334442 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 138507 # number of nop insts executed -system.cpu0.iew.exec_refs 14971538 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5077620 # Number of branches executed -system.cpu0.iew.exec_stores 5566035 # Number of stores executed -system.cpu0.iew.exec_rate 0.514994 # Inst execution rate -system.cpu0.iew.wb_sent 37653849 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35355057 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18700837 # num instructions producing a value -system.cpu0.iew.wb_consumers 35658328 # num instructions consuming a value +system.cpu0.iew.exec_nop 58504 # number of nop insts executed +system.cpu0.iew.exec_refs 12394115 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4158454 # Number of branches executed +system.cpu0.iew.exec_stores 4694891 # Number of stores executed +system.cpu0.iew.exec_rate 0.492201 # Inst execution rate +system.cpu0.iew.wb_sent 31120630 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 29114811 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 15418480 # num instructions producing a value +system.cpu0.iew.wb_consumers 29202336 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.480756 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.524445 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.458152 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.527988 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6703968 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 689136 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 267907 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 44701440 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.716325 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.672707 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5043051 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 567343 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 195875 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 37746791 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.699150 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.656907 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32554343 72.83% 72.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6077315 13.60% 86.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1947893 4.36% 90.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1038743 2.32% 93.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 803562 1.80% 94.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 505193 1.13% 96.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 401469 0.90% 96.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 200976 0.45% 97.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1171946 2.62% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 27673007 73.31% 73.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5099673 13.51% 86.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1632700 4.33% 91.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 816219 2.16% 93.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 659263 1.75% 95.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 376754 1.00% 96.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 343613 0.91% 96.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 170043 0.45% 97.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 975519 2.58% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 44701440 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24280608 # Number of instructions committed -system.cpu0.commit.committedOps 32020757 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 37746791 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 19900047 # Number of instructions committed +system.cpu0.commit.committedOps 26390683 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11707325 # Number of memory references committed -system.cpu0.commit.loads 6427859 # Number of loads committed -system.cpu0.commit.membars 234599 # Number of memory barriers committed -system.cpu0.commit.branches 4418672 # Number of branches committed -system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28286546 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500309 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1171946 # number cycles where commit BW limit reached +system.cpu0.commit.refs 9699440 # Number of memory references committed +system.cpu0.commit.loads 5228262 # Number of loads committed +system.cpu0.commit.membars 194354 # Number of memory barriers committed +system.cpu0.commit.branches 3620828 # Number of branches committed +system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 23422561 # Number of committed integer instructions. +system.cpu0.commit.function_calls 422942 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 975519 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 81369547 # The number of ROB reads -system.cpu0.rob.rob_writes 78542452 # The number of ROB writes -system.cpu0.timesIdled 427204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27784943 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5160481977 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24199866 # Number of Instructions Simulated -system.cpu0.committedOps 31940015 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24199866 # Number of Instructions Simulated -system.cpu0.cpi 3.038882 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.038882 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.329068 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.329068 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176731885 # number of integer regfile reads -system.cpu0.int_regfile_writes 35129220 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3381 # number of floating regfile reads -system.cpu0.fp_regfile_writes 940 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47656068 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527809 # number of misc regfile writes -system.cpu0.icache.replacements 407270 # number of replacements -system.cpu0.icache.tagsinuse 511.577657 # Cycle average of tags in use -system.cpu0.icache.total_refs 3982592 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 407782 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.766473 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 7275068000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.577657 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3982592 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3982592 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3982592 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3982592 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3982592 # number of overall hits -system.cpu0.icache.overall_hits::total 3982592 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 441782 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 441782 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 441782 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 441782 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 441782 # number of overall misses -system.cpu0.icache.overall_misses::total 441782 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7132710997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7132710997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7132710997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7132710997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7132710997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7132710997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4424374 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4424374 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4424374 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4424374 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4424374 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4424374 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099852 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099852 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099852 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099852 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099852 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099852 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16145.318272 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16145.318272 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16145.318272 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16145.318272 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1383498 # number of cycles access was blocked +system.cpu0.rob.rob_reads 67501483 # The number of ROB reads +system.cpu0.rob.rob_writes 63684069 # The number of ROB writes +system.cpu0.timesIdled 366948 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25015318 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5170100782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 19875493 # Number of Instructions Simulated +system.cpu0.committedOps 26366129 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 19875493 # Number of Instructions Simulated +system.cpu0.cpi 3.197325 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.197325 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.312761 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.312761 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 145756307 # number of integer regfile reads +system.cpu0.int_regfile_writes 28747856 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4243 # number of floating regfile reads +system.cpu0.fp_regfile_writes 404 # number of floating regfile writes +system.cpu0.misc_regfile_reads 38262536 # number of misc regfile reads +system.cpu0.misc_regfile_writes 444175 # number of misc regfile writes +system.cpu0.icache.replacements 335591 # number of replacements +system.cpu0.icache.tagsinuse 511.578004 # Cycle average of tags in use +system.cpu0.icache.total_refs 3187209 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 336103 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.482834 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 7275076000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.578004 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999176 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999176 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3187209 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3187209 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3187209 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3187209 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3187209 # number of overall hits +system.cpu0.icache.overall_hits::total 3187209 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 363477 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 363477 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 363477 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 363477 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 363477 # number of overall misses +system.cpu0.icache.overall_misses::total 363477 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5925752494 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5925752494 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5925752494 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5925752494 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5925752494 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5925752494 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 3550686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 3550686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 3550686 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 3550686 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 3550686 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 3550686 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102368 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.102368 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102368 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.102368 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102368 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.102368 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16302.964133 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16302.964133 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16302.964133 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16302.964133 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1276494 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 169 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 156 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8186.378698 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8182.653846 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33988 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33988 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33988 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33988 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33988 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33988 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407794 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 407794 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 407794 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092170 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.092170 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.092170 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13416.665029 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4556806494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8394000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8394000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8394000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8394000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.094661 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.094661 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.094661 # 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number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1594295 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1594295 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9014 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9014 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7780 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7780 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1995851 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1995851 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1995851 # number of overall misses -system.cpu0.dcache.overall_misses::total 1995851 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7292954000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 7292954000 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178801 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178801 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18161.735848 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18161.735848 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44946.320697 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44946.320697 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12628.300422 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12628.300422 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11615.745501 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11615.745501 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39557.385975 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39557.385975 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7317992 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1712000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1467 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 85 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4988.406271 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20141.176471 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 225959 # 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number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 155489 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152427 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 152427 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7329543 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 7329543 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7329543 # number of overall hits +system.cpu0.dcache.overall_hits::total 7329543 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 331165 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 331165 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1441313 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1441313 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8607 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8607 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7989 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7989 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1772478 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1772478 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1772478 # number of overall misses +system.cpu0.dcache.overall_misses::total 1772478 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6024148000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6024148000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68192376390 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 68192376390 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 105659500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 105659500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 91795500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 91795500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 74216524390 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 74216524390 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 74216524390 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 74216524390 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5050252 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5050252 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4051769 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4051769 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 164096 # 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miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052451 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052451 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049802 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049802 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.194735 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.194735 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.194735 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.194735 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18190.774991 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18190.774991 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47312.676976 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 47312.676976 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12275.996282 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12275.996282 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11490.236575 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11490.236575 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41871.619501 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41871.619501 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 5649995 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1774500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1210 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 93 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4669.417355 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 19080.645161 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks -system.cpu0.dcache.writebacks::total 255942 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 212150 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 212150 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463164 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1463164 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 530 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 530 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1675314 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1675314 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1675314 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1675314 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189406 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189406 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131131 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131131 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8484 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8484 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7773 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7773 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320537 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320537 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320537 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320537 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2811014487 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2811014487 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4674099005 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4674099005 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79244002 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79244002 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65918035 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65918035 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7485113492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7485113492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7485113492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7485113492 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13455989500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13455989500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1298746899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1298746899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14754736399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14754736399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029881 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029881 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027185 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027185 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046281 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046281 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043342 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043342 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028716 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028716 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14841.211403 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14841.211403 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35644.500576 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35644.500576 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9340.405705 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9340.405705 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8480.385308 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8480.385308 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 209818 # number of writebacks +system.cpu0.dcache.writebacks::total 209818 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 177491 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 177491 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1323875 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1323875 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 700 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1501366 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1501366 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1501366 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1501366 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 153674 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 153674 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 117438 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 117438 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7907 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7907 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7979 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7979 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 271112 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 271112 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 271112 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 271112 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2311816775 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2311816775 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4408331005 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4408331005 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70347504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70347504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 66656537 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66656537 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6720147780 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6720147780 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6720147780 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6720147780 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12100601500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12100601500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1292553399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1292553399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13393154899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13393154899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030429 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030429 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048185 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.048185 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049739 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049739 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029786 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029786 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15043.642874 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15043.642874 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37537.517711 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37537.517711 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8896.864045 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8896.864045 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8353.996365 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8353.996365 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1081,27 +1107,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43452334 # DTB read hits -system.cpu1.dtb.read_misses 46277 # DTB read misses -system.cpu1.dtb.write_hits 7091337 # DTB write hits -system.cpu1.dtb.write_misses 12150 # DTB write misses +system.cpu1.dtb.read_hits 45088968 # DTB read hits +system.cpu1.dtb.read_misses 60619 # DTB read misses +system.cpu1.dtb.write_hits 7938217 # DTB write hits +system.cpu1.dtb.write_misses 15813 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2524 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3762 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2729 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3748 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43498611 # DTB read accesses -system.cpu1.dtb.write_accesses 7103487 # DTB write accesses +system.cpu1.dtb.perms_faults 727 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 45149587 # DTB read accesses +system.cpu1.dtb.write_accesses 7954030 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50543671 # DTB hits -system.cpu1.dtb.misses 58427 # DTB misses -system.cpu1.dtb.accesses 50602098 # DTB accesses -system.cpu1.itb.inst_hits 9232744 # ITB inst hits -system.cpu1.itb.inst_misses 6115 # ITB inst misses +system.cpu1.dtb.hits 53027185 # DTB hits +system.cpu1.dtb.misses 76432 # DTB misses +system.cpu1.dtb.accesses 53103617 # DTB accesses +system.cpu1.itb.inst_hits 10093689 # ITB inst hits +system.cpu1.itb.inst_misses 8052 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1110,542 +1136,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1606 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1586 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1727 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2426 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9238859 # ITB inst accesses -system.cpu1.itb.hits 9232744 # DTB hits -system.cpu1.itb.misses 6115 # DTB misses -system.cpu1.itb.accesses 9238859 # DTB accesses -system.cpu1.numCycles 420389270 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10101741 # ITB inst accesses +system.cpu1.itb.hits 10093689 # DTB hits +system.cpu1.itb.misses 8052 # DTB misses +system.cpu1.itb.accesses 10101741 # DTB accesses +system.cpu1.numCycles 430376404 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9847995 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 8081754 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 448433 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6818773 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5657403 # Number of BTB hits +system.cpu1.BPredUnit.lookups 11102078 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 9036479 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 529963 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7542756 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 6181694 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 833939 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50420 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 22177481 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71987538 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9847995 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6491342 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15338669 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4640041 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 86616 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 81067805 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5869 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 63713 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142087 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9230611 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 860735 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3603 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 122048207 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.712843 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.062128 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 958293 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 57467 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 24500240 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 78456444 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 11102078 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 7139987 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 16800094 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 5031478 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 107954 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 84138717 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 105572 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 161210 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10091008 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 896138 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 4286 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 129269647 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.735584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.091589 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 106717875 87.44% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 829211 0.68% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1015415 0.83% 88.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2063306 1.69% 90.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1641471 1.34% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 615009 0.50% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2274741 1.86% 94.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 467540 0.38% 94.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6423639 5.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 112479856 87.01% 87.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 952035 0.74% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1186228 0.92% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2188812 1.69% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1732150 1.34% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 728800 0.56% 92.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2428875 1.88% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 531185 0.41% 94.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 7041706 5.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 122048207 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.023426 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.171240 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23807304 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 80829213 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13786228 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 560401 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3065061 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1241341 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102643 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 81234919 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 343119 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3065061 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 25364340 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34010393 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 42304537 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12707018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4596858 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74746383 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 20429 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 720817 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3279864 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33412 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 79106997 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 344419030 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 344359691 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59339 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50193146 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28913851 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 487769 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 421850 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8399849 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14034972 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8614706 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1072487 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1529720 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 67446295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1206628 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 91979521 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 109681 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18910261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53596675 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 286825 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 122048207 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.753633 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.492572 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 129269647 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.025796 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.182297 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 26260600 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 83914684 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15106265 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 652780 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3335318 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1450901 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 116510 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 88966869 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 389379 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3335318 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 27931781 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34696050 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 44327698 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 14003132 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4975668 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 82212740 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 21319 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 759400 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3532141 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33925 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 86942184 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 378153831 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 378105448 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 48383 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 55944710 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 30997473 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 570448 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 494970 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9410070 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15640035 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 9547074 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1284923 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1813164 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 74425843 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1310750 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 98630822 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 132915 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 20366425 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 57377380 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 269048 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 129269647 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.762985 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.495609 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 90230410 73.93% 73.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9124502 7.48% 81.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4577298 3.75% 85.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4017634 3.29% 88.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10703333 8.77% 97.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1977632 1.62% 98.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1055737 0.87% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 281681 0.23% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 79980 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 94766617 73.31% 73.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10139907 7.84% 81.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 5158815 3.99% 85.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4427747 3.43% 88.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 11055431 8.55% 97.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 2157635 1.67% 98.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1155512 0.89% 99.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 316791 0.25% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 91192 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 122048207 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 129269647 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28913 0.37% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7574685 95.84% 96.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 298874 3.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 39597 0.49% 0.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1008 0.01% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7696421 95.46% 95.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 325487 4.04% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39479578 42.92% 43.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61492 0.07% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1697 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44651207 48.54% 91.88% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7471778 8.12% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 326092 0.33% 0.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 43501050 44.10% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 69634 0.07% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 16 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1718 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 46384595 47.03% 91.54% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 8347697 8.46% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 91979521 # Type of FU issued -system.cpu1.iq.rate 0.218796 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7903470 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.085926 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 314063875 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 87576510 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55784562 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14814 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8109 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 99561488 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7766 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 369403 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 98630822 # Type of FU issued +system.cpu1.iq.rate 0.229173 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 8062513 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.081744 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 334791339 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 96121166 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 62008917 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11647 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6672 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5500 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 106361230 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6013 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 441985 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4042367 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6847 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 22042 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1594624 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4452276 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7115 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 25628 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1723414 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965742 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1047944 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 32221586 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1050708 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3065061 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25634357 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 409319 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68777683 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 134755 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14034972 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8614706 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 896270 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 80399 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 14951 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 22042 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 226446 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 198201 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 424647 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 89117462 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43838045 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2862059 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3335318 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26012639 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 434151 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 75941872 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 151121 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15640035 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 9547074 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 940187 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 96009 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 15502 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 25628 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 268769 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 233332 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 502101 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 95691641 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 45532774 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2939181 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 124760 # number of nop insts executed -system.cpu1.iew.exec_refs 51234744 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7395685 # Number of branches executed -system.cpu1.iew.exec_stores 7396699 # Number of stores executed -system.cpu1.iew.exec_rate 0.211988 # Inst execution rate -system.cpu1.iew.wb_sent 87946957 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55791363 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30796912 # num instructions producing a value -system.cpu1.iew.wb_consumers 54575062 # num instructions consuming a value +system.cpu1.iew.exec_nop 205279 # number of nop insts executed +system.cpu1.iew.exec_refs 53793996 # number of memory reference insts executed +system.cpu1.iew.exec_branches 8312135 # Number of branches executed +system.cpu1.iew.exec_stores 8261222 # Number of stores executed +system.cpu1.iew.exec_rate 0.222344 # Inst execution rate +system.cpu1.iew.wb_sent 94462198 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 62014417 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 34071785 # num instructions producing a value +system.cpu1.iew.wb_consumers 60996509 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.132714 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.564304 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.144093 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.558586 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 19037243 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 919803 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 377326 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 119031582 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.414273 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.369590 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 20655264 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1041702 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 445913 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 125990352 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.435949 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.396620 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 101746657 85.48% 85.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8535054 7.17% 92.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2209116 1.86% 94.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1312161 1.10% 95.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1288209 1.08% 96.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 590684 0.50% 97.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 998098 0.84% 98.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 485890 0.41% 98.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1865713 1.57% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 106643597 84.64% 84.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9506424 7.55% 92.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2528568 2.01% 94.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1530167 1.21% 95.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1425850 1.13% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 711007 0.56% 97.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1063442 0.84% 97.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 518210 0.41% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 2063087 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 119031582 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38947564 # Number of instructions committed -system.cpu1.commit.committedOps 49311547 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 125990352 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 43322553 # Number of instructions committed +system.cpu1.commit.committedOps 54925314 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17012687 # Number of memory references committed -system.cpu1.commit.loads 9992605 # Number of loads committed -system.cpu1.commit.membars 202357 # Number of memory barriers committed -system.cpu1.commit.branches 6222202 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43701968 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556417 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1865713 # number cycles where commit BW limit reached +system.cpu1.commit.refs 19011419 # Number of memory references committed +system.cpu1.commit.loads 11187759 # Number of loads committed +system.cpu1.commit.membars 242679 # Number of memory barriers committed +system.cpu1.commit.branches 7019269 # Number of branches committed +system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 48550450 # Number of committed integer instructions. +system.cpu1.commit.function_calls 633769 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 2063087 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 184400014 # The number of ROB reads -system.cpu1.rob.rob_writes 139856425 # The number of ROB writes -system.cpu1.timesIdled 1519588 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 298341063 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4812976632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38877925 # Number of Instructions Simulated -system.cpu1.committedOps 49241908 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38877925 # Number of Instructions Simulated -system.cpu1.cpi 10.813058 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.813058 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092481 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092481 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 398800057 # number of integer regfile reads -system.cpu1.int_regfile_writes 58498146 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4943 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2344 # number of floating regfile writes -system.cpu1.misc_regfile_reads 91875872 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429758 # number of misc regfile writes -system.cpu1.icache.replacements 623101 # number of replacements -system.cpu1.icache.tagsinuse 498.730815 # Cycle average of tags in use -system.cpu1.icache.total_refs 8556871 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 623613 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.721444 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 75785780000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.730815 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974084 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974084 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8556871 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8556871 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8556871 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8556871 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8556871 # number of overall hits -system.cpu1.icache.overall_hits::total 8556871 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 673686 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 673686 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 673686 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 673686 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 673686 # number of overall misses -system.cpu1.icache.overall_misses::total 673686 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10642693998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10642693998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10642693998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10642693998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10642693998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10642693998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9230557 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9230557 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9230557 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9230557 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9230557 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9230557 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072984 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.072984 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072984 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.072984 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072984 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.072984 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15797.706941 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15797.706941 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15797.706941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15797.706941 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1133998 # number of cycles access was blocked +system.cpu1.rob.rob_reads 198211439 # The number of ROB reads +system.cpu1.rob.rob_writes 154591902 # The number of ROB writes +system.cpu1.timesIdled 1579473 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 301106757 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4803892671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 43196726 # Number of Instructions Simulated +system.cpu1.committedOps 54799487 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 43196726 # Number of Instructions Simulated +system.cpu1.cpi 9.963172 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 9.963172 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.100370 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.100370 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 429674423 # number of integer regfile reads +system.cpu1.int_regfile_writes 64872300 # number of integer regfile writes +system.cpu1.fp_regfile_reads 3964 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1982 # number of floating regfile writes +system.cpu1.misc_regfile_reads 101230364 # number of misc regfile reads +system.cpu1.misc_regfile_writes 513642 # number of misc regfile writes +system.cpu1.icache.replacements 694768 # number of replacements +system.cpu1.icache.tagsinuse 498.623067 # Cycle average of tags in use +system.cpu1.icache.total_refs 9339186 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 695280 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.432266 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 75785789000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.623067 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.973873 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.973873 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 9339186 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9339186 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9339186 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9339186 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9339186 # number of overall hits +system.cpu1.icache.overall_hits::total 9339186 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 751768 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 751768 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 751768 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 751768 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 751768 # number of overall misses +system.cpu1.icache.overall_misses::total 751768 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11830653994 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11830653994 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11830653994 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11830653994 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11830653994 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11830653994 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10090954 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10090954 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10090954 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10090954 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10090954 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10090954 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074499 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.074499 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074499 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.074499 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074499 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.074499 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15737.107717 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15737.107717 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15737.107717 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15737.107717 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1257996 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 174 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 215 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6517.229885 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5851.144186 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50044 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 50044 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 50044 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 50044 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 50044 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 50044 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623642 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 623642 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 623642 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 623642 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 623642 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 623642 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8149352498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8149352498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8149352498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8149352498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8149352498 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8149352498 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 56459 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 56459 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 56459 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 56459 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 56459 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 56459 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 695309 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 695309 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 695309 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 695309 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 695309 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 695309 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9048159496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 9048159496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9048159496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 9048159496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9048159496 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 9048159496 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3211500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3211500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3211500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3211500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067563 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067563 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.067563 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13067.356750 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068904 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.068904 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.068904 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13013.148824 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363581 # number of replacements -system.cpu1.dcache.tagsinuse 487.223522 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13117187 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363929 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.043258 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 71474573000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.223522 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951608 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951608 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8616147 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8616147 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4254446 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4254446 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105790 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105790 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100736 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100736 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12870593 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12870593 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12870593 # number of overall hits -system.cpu1.dcache.overall_hits::total 12870593 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 410065 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 410065 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1595508 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1595508 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10912 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10912 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2005573 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2005573 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2005573 # number of overall misses -system.cpu1.dcache.overall_misses::total 2005573 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8126055000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8126055000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66044305227 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 66044305227 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166791500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 166791500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95304000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 95304000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 74170360227 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 74170360227 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 74170360227 # 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miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134818 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134818 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134818 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19816.504700 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19816.504700 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41393.904153 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41393.904153 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11681.713125 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11681.713125 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8733.870968 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8733.870968 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 36982.129410 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 36982.129410 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29670016 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5568500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6658 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 173 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4456.295584 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 32187.861272 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 413009 # number of replacements +system.cpu1.dcache.tagsinuse 487.394187 # Cycle average of tags in use +system.cpu1.dcache.total_refs 14990250 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 413521 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.250275 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 71474582000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.394187 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951942 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951942 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 9825576 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9825576 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4872589 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4872589 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123205 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 123205 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 119861 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 119861 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 14698165 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 14698165 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 14698165 # number of overall hits +system.cpu1.dcache.overall_hits::total 14698165 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 478795 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 478795 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1745196 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1745196 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14728 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14728 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10805 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10805 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2223991 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2223991 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2223991 # number of overall misses +system.cpu1.dcache.overall_misses::total 2223991 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9322511500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9322511500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 69699331710 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 69699331710 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 175643000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 175643000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94845500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 94845500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 79021843210 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 79021843210 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 79021843210 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 79021843210 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10304371 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10304371 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6617785 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6617785 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137933 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 137933 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130666 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 130666 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16922156 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16922156 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16922156 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16922156 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046465 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.046465 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263713 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.263713 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106776 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106776 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.082692 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.082692 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131425 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.131425 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131425 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.131425 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19470.778726 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19470.778726 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39937.824582 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39937.824582 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11925.787615 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11925.787615 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8777.926886 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8777.926886 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 35531.548109 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 35531.548109 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 31184009 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5513500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4502.455819 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33213.855422 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328251 # number of writebacks -system.cpu1.dcache.writebacks::total 328251 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178277 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 178277 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432587 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1432587 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1464 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1464 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1610864 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1610864 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1610864 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1610864 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231788 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231788 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162921 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162921 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12814 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12814 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394709 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394709 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394709 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394709 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3566201462 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3566201462 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5537603585 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5537603585 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104573506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104573506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61265506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61265506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9103805047 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9103805047 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9103805047 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9103805047 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169309741500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169309741500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40933880282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40933880282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210243621782 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210243621782 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025679 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025679 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027850 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027850 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106723 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106723 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097709 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097709 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026533 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026533 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15385.617297 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15385.617297 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33989.501568 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33989.501568 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8160.879195 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8160.879195 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5616.051517 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5616.051517 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 373664 # number of writebacks +system.cpu1.dcache.writebacks::total 373664 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211355 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 211355 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1568704 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1568704 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1302 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1302 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1780059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1780059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1780059 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1780059 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267440 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 267440 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 176492 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 176492 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13426 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13426 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10800 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10800 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 443932 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 443932 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 443932 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 443932 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4040609191 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4040609191 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5818534579 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5818534579 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 114031007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 114031007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61142007 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61142007 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9859143770 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9859143770 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9859143770 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9859143770 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170666816500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170666816500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40957900116 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40957900116 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 211624716616 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 211624716616 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025954 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025954 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097337 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097337 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.082653 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.082653 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026234 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026234 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15108.469904 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15108.469904 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32967.695867 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32967.695867 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8493.297110 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8493.297110 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5661.296944 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5661.296944 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1667,18 +1693,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323189312111 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323189312111 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323290279244 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323290279244 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43824 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 36101 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 61677 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index c4b0f36dd..5e48f5c5e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538055 # Number of seconds simulated -sim_ticks 2538055224500 # Number of ticks simulated -final_tick 2538055224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.538087 # Number of seconds simulated +sim_ticks 2538087368500 # Number of ticks simulated +final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88262 # Simulator instruction rate (inst/s) -host_op_rate 113532 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3696075323 # Simulator tick rate (ticks/s) -host_mem_usage 390228 # Number of bytes of host memory used -host_seconds 686.69 # Real time elapsed on the host -sim_insts 60608338 # Number of instructions simulated -sim_ops 77960937 # Number of ops (including micro ops) simulated +host_inst_rate 89486 # Simulator instruction rate (inst/s) +host_op_rate 115106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3747392596 # Simulator tick rate (ticks/s) +host_mem_usage 390008 # Number of bytes of host memory used +host_seconds 677.29 # Real time elapsed on the host +sim_insts 60608307 # Number of instructions simulated +sim_ops 77960925 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090192 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797960 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59092 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813110 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717846 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2678413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4769898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54294380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64349 # number of replacements -system.l2c.tagsinuse 51370.291201 # Cycle average of tags in use -system.l2c.total_refs 1966684 # Total number of references to valid blocks. -system.l2c.sampled_refs 129742 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.158422 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2527049892000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36909.964338 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.537302 # Average occupied blocks per requestor +system.l2c.replacements 64372 # number of replacements +system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use +system.l2c.total_refs 1967256 # Total number of references to valid blocks. +system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8186.541319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6225.247998 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563201 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000741 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124917 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094990 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783848 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11547 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 978702 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 387818 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1500728 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits -system.l2c.Writeback_hits::total 608398 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112928 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112928 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 978702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 500746 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613656 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122661 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11547 # number of overall hits -system.l2c.overall_hits::cpu.inst 978702 # number of overall hits -system.l2c.overall_hits::cpu.data 500746 # number of overall hits -system.l2c.overall_hits::total 1613656 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.124757 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094926 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783730 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 123430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 978266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 387692 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1501094 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits +system.l2c.Writeback_hits::total 608347 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits +system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits +system.l2c.overall_hits::cpu.inst 978266 # number of overall hits +system.l2c.overall_hits::cpu.data 500583 # number of overall hits +system.l2c.overall_hits::total 1613985 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2903 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10685 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23113 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133164 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133164 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 133199 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133199 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12372 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143855 # number of demand (read+write) misses -system.l2c.demand_misses::total 156289 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143884 # number of demand (read+write) misses +system.l2c.demand_misses::total 156312 # number of demand (read+write) misses system.l2c.overall_misses::cpu.dtb.walker 61 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 1 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::cpu.inst 507249999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5869808998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6379552997 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5320000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745798500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166751118500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32081918388 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32081918388 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5320000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 198827716888 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198833036888 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026679 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015132 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.987079 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.987079 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541115 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541115 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026671 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015120 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088264 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088259 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088259 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.964560 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40466.541176 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40775.015144 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.247849 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.247849 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,27 +332,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51779226 # DTB read hits -system.cpu.dtb.read_misses 81574 # DTB read misses -system.cpu.dtb.write_hits 11882622 # DTB write hits -system.cpu.dtb.write_misses 18093 # DTB write misses +system.cpu.dtb.read_hits 51778790 # DTB read hits +system.cpu.dtb.read_misses 81353 # DTB read misses +system.cpu.dtb.write_hits 11881898 # DTB write hits +system.cpu.dtb.write_misses 18166 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4488 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3293 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 606 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4472 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1237 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860800 # DTB read accesses -system.cpu.dtb.write_accesses 11900715 # DTB write accesses +system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51860143 # DTB read accesses +system.cpu.dtb.write_accesses 11900064 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63661848 # DTB hits -system.cpu.dtb.misses 99667 # DTB misses -system.cpu.dtb.accesses 63761515 # DTB accesses -system.cpu.itb.inst_hits 13144692 # ITB inst hits -system.cpu.itb.inst_misses 11967 # ITB inst misses +system.cpu.dtb.hits 63660688 # DTB hits +system.cpu.dtb.misses 99519 # DTB misses +system.cpu.dtb.accesses 63760207 # DTB accesses +system.cpu.itb.inst_hits 13142674 # ITB inst hits +system.cpu.itb.inst_misses 12012 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -361,122 +361,122 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2661 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13156659 # ITB inst accesses -system.cpu.itb.hits 13144692 # DTB hits -system.cpu.itb.misses 11967 # DTB misses -system.cpu.itb.accesses 13156659 # DTB accesses -system.cpu.numCycles 487285069 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154686 # ITB inst accesses +system.cpu.itb.hits 13142674 # DTB hits +system.cpu.itb.misses 12012 # DTB misses +system.cpu.itb.accesses 13154686 # DTB accesses +system.cpu.numCycles 487300785 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15533008 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12472748 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753945 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10621013 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369898 # Number of BTB hits +system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450891 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 81082 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33390116 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101781554 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15533008 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9820789 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22319812 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6080499 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158808 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102222011 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133571 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 207903 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13140422 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021772 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6316 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134680 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140314971 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367844 0.84% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761669 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2653320 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2361626 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142802 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2916048 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808288 0.50% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9291255 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031877 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208875 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35567426 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101892214 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20037549 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109983 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010651 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100654 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174914 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316762 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572114 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010651 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37681511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40491658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54797467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18895098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6741438 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110776004 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22866 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1160313 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487001 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30716 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115615239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507028919 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506935731 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93188 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747197 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36868041 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898954 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797959 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13563069 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21067127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13877132 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956196 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2590406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101357427 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126494913 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 198538 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24680718 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65543860 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514575 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162617823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777866 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488052 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116473756 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14895850 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7383355 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6325930 3.89% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12628751 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810327 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536412 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438084 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125358 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162617823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53829 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available @@ -504,13 +504,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366722 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411335 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100692 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95407 0.08% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued @@ -523,10 +523,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued @@ -538,361 +538,361 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53419362 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12513627 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126494913 # Type of FU issued -system.cpu.iq.rate 0.259591 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8831890 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069820 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424714403 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128119104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467949 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12866 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10326 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134951003 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 645792 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued +system.cpu.iq.rate 0.259577 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5347388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11096 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2076739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107215 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052024 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010651 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30083339 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540488 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103672693 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219471 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21067127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13877132 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126042 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41068 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376458 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332668 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709126 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123289616 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469824 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3205297 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255493 # number of nop insts executed -system.cpu.iew.exec_refs 64863659 # number of memory reference insts executed -system.cpu.iew.exec_branches 11931891 # Number of branches executed -system.cpu.iew.exec_stores 12393835 # Number of stores executed -system.cpu.iew.exec_rate 0.253013 # Inst execution rate -system.cpu.iew.wb_sent 121912605 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87478275 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47524907 # num instructions producing a value -system.cpu.iew.wb_consumers 86445005 # num instructions consuming a value +system.cpu.iew.exec_nop 255111 # number of nop insts executed +system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed +system.cpu.iew.exec_branches 11930392 # Number of branches executed +system.cpu.iew.exec_stores 12393079 # Number of stores executed +system.cpu.iew.exec_rate 0.253002 # Inst execution rate +system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47523827 # num instructions producing a value +system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179522 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549770 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24740610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545198 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625619 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158689613 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492227 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459221 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130476861 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14004142 8.82% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942589 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238161 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2017118 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1061710 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402075 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657613 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889344 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158689613 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758719 # Number of instructions committed -system.cpu.commit.committedOps 78111318 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60758688 # Number of instructions committed +system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520132 # Number of memory references committed -system.cpu.commit.loads 15719739 # Number of loads committed -system.cpu.commit.membars 413350 # Number of memory barriers committed -system.cpu.commit.branches 10163894 # Number of branches committed +system.cpu.commit.refs 27520186 # Number of memory references committed +system.cpu.commit.loads 15719769 # Number of loads committed +system.cpu.commit.membars 413359 # Number of memory barriers committed +system.cpu.commit.branches 10163898 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148099 # Number of committed integer instructions. -system.cpu.commit.function_calls 996264 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889344 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. +system.cpu.commit.function_calls 996262 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256736769 # The number of ROB reads -system.cpu.rob.rob_writes 209812510 # The number of ROB writes -system.cpu.timesIdled 1906775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324667246 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588737338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608338 # Number of Instructions Simulated -system.cpu.committedOps 77960937 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608338 # Number of Instructions Simulated -system.cpu.cpi 8.039902 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.039902 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124380 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124380 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558055785 # number of integer regfile reads -system.cpu.int_regfile_writes 90157820 # number of integer regfile writes -system.cpu.fp_regfile_reads 8288 # number of floating regfile reads -system.cpu.fp_regfile_writes 2908 # number of floating regfile writes -system.cpu.misc_regfile_reads 134082325 # number of misc regfile reads -system.cpu.misc_regfile_writes 913357 # number of misc regfile writes -system.cpu.icache.replacements 991945 # number of replacements -system.cpu.icache.tagsinuse 511.576100 # Cycle average of tags in use -system.cpu.icache.total_refs 12062971 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992457 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.154654 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225347000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.576100 # Average occupied blocks per requestor +system.cpu.rob.rob_reads 256700614 # The number of ROB reads +system.cpu.rob.rob_writes 209796185 # The number of ROB writes +system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60608307 # Number of Instructions Simulated +system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated +system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 558050322 # number of integer regfile reads +system.cpu.int_regfile_writes 90161620 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads +system.cpu.misc_regfile_writes 913390 # number of misc regfile writes +system.cpu.icache.replacements 991554 # number of replacements +system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use +system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12062971 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12062971 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12062971 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12062971 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12062971 # number of overall hits -system.cpu.icache.overall_hits::total 12062971 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1077319 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1077319 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1077319 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1077319 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1077319 # number of overall misses -system.cpu.icache.overall_misses::total 1077319 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16672871489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16672871489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16672871489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16672871489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16672871489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16672871489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13140290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13140290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13140290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13140290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081986 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081986 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081986 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081986 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2904990 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits +system.cpu.icache.overall_hits::total 12061582 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1076715 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1076715 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1076715 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1076715 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1076715 # number of overall misses +system.cpu.icache.overall_misses::total 1076715 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16664677991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16664677991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16664677991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16664677991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 436 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 446 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6662.821101 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84824 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84824 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84824 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84824 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84824 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84824 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992495 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 992495 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 992495 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 992495 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 992495 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 992495 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12649346990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12649346990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12649346990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12649346990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84611 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992104 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 992104 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 992104 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 992104 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 992104 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 992104 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12645073993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12645073993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12645073993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12645073993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644089 # number of replacements -system.cpu.dcache.tagsinuse 511.991456 # Cycle average of tags in use -system.cpu.dcache.total_refs 21738846 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644601 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724499 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991456 # Average occupied blocks per requestor +system.cpu.dcache.replacements 643955 # number of replacements +system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use +system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908205 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13908205 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258424 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258424 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283313 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283313 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285772 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285772 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21166629 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21166629 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21166629 # number of overall hits -system.cpu.dcache.overall_hits::total 21166629 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 766922 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 766922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2994004 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2994004 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13808 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13808 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3759495 # number of overall misses +system.cpu.dcache.overall_misses::total 3759495 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14876538000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14876538000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129441839072 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129441839072 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224157500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224157500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 359000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 359000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144318377072 # 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number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24926244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24926244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24926244 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24926244 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052182 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052182 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292007 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292007 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046437 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046437 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150825 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150825 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150825 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150825 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19428.423293 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19428.423293 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43236.852036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43236.852036 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16228.009846 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16228.009846 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22437.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 22437.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38387.702889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38387.702889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33577415 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7376000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7440 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4513.093414 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26063.604240 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608398 # number of writebacks -system.cpu.dcache.writebacks::total 608398 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 380638 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 380638 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2745107 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2745107 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1447 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3125745 # 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number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744878 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1442 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1442 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3124452 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3124452 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3124452 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3124452 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386136 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386136 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248907 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248907 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12371 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12371 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635043 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -914,16 +914,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323890643510 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index c2225df75..ef4c69b34 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.167942 # Number of seconds simulated -sim_ticks 5167941639500 # Number of ticks simulated -final_tick 5167941639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.163939 # Number of seconds simulated +sim_ticks 5163939423500 # Number of ticks simulated +final_tick 5163939423500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128954 # Simulator instruction rate (inst/s) -host_op_rate 254914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1633898837 # Simulator tick rate (ticks/s) -host_mem_usage 412792 # Number of bytes of host memory used -host_seconds 3162.95 # Real time elapsed on the host -sim_insts 407876198 # Number of instructions simulated -sim_ops 806280456 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2473280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory +host_inst_rate 202828 # Simulator instruction rate (inst/s) +host_op_rate 400952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2568035232 # Simulator tick rate (ticks/s) +host_mem_usage 368532 # Number of bytes of host memory used +host_seconds 2010.85 # Real time elapsed on the host +sim_insts 407858031 # Number of instructions simulated +sim_ops 806254969 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2460224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1074496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10579456 # Number of bytes read from this memory -system.physmem.bytes_read::total 14130624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1074496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1074496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9348288 # Number of bytes written to this memory -system.physmem.bytes_written::total 9348288 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38645 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1069888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10576384 # Number of bytes read from this memory +system.physmem.bytes_read::total 14109824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1069888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1069888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9320448 # Number of bytes written to this memory +system.physmem.bytes_written::total 9320448 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38441 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16789 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165304 # Number of read requests responded to by this memory -system.physmem.num_reads::total 220791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 146067 # Number of write requests responded to by this memory -system.physmem.num_writes::total 146067 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 478581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 582 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16717 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165256 # Number of read requests responded to by this memory +system.physmem.num_reads::total 220466 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145632 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145632 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 570 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 207916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2047131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2734285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 207916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 207916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1808900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1808900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1808900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 478581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 207184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2048123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2732376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 207184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 207184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1804910 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1804910 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1804910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 570 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 207916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2047131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4543184 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 109808 # number of replacements -system.l2c.tagsinuse 64836.655656 # Cycle average of tags in use -system.l2c.total_refs 3979638 # Total number of references to valid blocks. -system.l2c.sampled_refs 173786 # Sample count of references to valid blocks. -system.l2c.avg_refs 22.899647 # Average number of references to valid blocks. +system.physmem.bw_total::cpu.inst 207184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2048123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4537286 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 109190 # number of replacements +system.l2c.tagsinuse 64839.015299 # Cycle average of tags in use +system.l2c.total_refs 3984882 # Total number of references to valid blocks. +system.l2c.sampled_refs 173424 # Sample count of references to valid blocks. +system.l2c.avg_refs 22.977685 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50087.148367 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 11.882077 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.155165 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3382.932484 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11354.537562 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.764269 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000181 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 49968.765370 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 13.151051 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.155230 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3435.794855 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11421.148791 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.762463 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051619 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.173256 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989329 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 103999 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 8349 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1054675 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1347003 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2514026 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1610152 # number of Writeback hits -system.l2c.Writeback_hits::total 1610152 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 315 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 315 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 158022 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 158022 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 103999 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 8349 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1054675 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1505025 # number of demand (read+write) hits -system.l2c.demand_hits::total 2672048 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 103999 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 8349 # number of overall hits -system.l2c.overall_hits::cpu.inst 1054675 # number of overall hits -system.l2c.overall_hits::cpu.data 1505025 # number of overall hits -system.l2c.overall_hits::total 2672048 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 47 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.052426 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.174273 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989365 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 103321 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 8437 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1055749 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1347777 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2515284 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1610495 # number of Writeback hits +system.l2c.Writeback_hits::total 1610495 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 337 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 158131 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 158131 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 103321 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 8437 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1055749 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1505908 # number of demand (read+write) hits +system.l2c.demand_hits::total 2673415 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 103321 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 8437 # number of overall hits +system.l2c.overall_hits::cpu.inst 1055749 # number of overall hits +system.l2c.overall_hits::cpu.data 1505908 # number of overall hits +system.l2c.overall_hits::total 2673415 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 16790 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 35954 # number of ReadReq misses -system.l2c.ReadReq_misses::total 52797 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 3370 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3370 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 130295 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130295 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 47 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000718 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015669 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025996 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020568 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.914518 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.914518 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.451916 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.451916 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000718 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.015669 # 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 88673398500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 88673398500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2308733000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2308733000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 90982131500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 90982131500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026002 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020541 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.909433 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.909433 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.451599 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.451599 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.064056 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.064056 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40872.595092 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41157.459919 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 41066.020722 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40119.436202 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40119.436202 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.744403 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.744403 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40351.063830 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40895.585332 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41169.311553 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41081.715621 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40131.796690 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40131.796690 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.130527 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.130527 # 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average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40872.595092 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40312.023682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40363.427076 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47571 # number of replacements -system.iocache.tagsinuse 0.197047 # Cycle average of tags in use +system.iocache.replacements 47573 # number of replacements +system.iocache.tagsinuse 0.184801 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47587 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996693441000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.197047 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.012315 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.012315 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses -system.iocache.ReadReq_misses::total 906 # number of ReadReq misses +system.iocache.warmup_cycle 4996693675000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.184801 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.011550 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.011550 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # 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number of overall miss cycles -system.iocache.overall_miss_latency::total 7049863092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47628 # number of demand (read+write) misses +system.iocache.demand_misses::total 47628 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47628 # number of overall misses +system.iocache.overall_misses::total 47628 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137681932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 137681932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9939428160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9939428160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10077110092 # 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number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,40 +330,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150165.487859 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 150165.487859 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147984.014555 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 147984.014555 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148025.513207 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 148025.513207 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148025.513207 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 148025.513207 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151632.083700 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 151632.083700 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212744.609589 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 212744.609589 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 211579.534979 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 211579.534979 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72537008 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8981 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8076.718406 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 908 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47626 # 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number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47628 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47628 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47628 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47628 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90434000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 90434000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7509668946 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7509668946 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7600102946 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7600102946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98130.242826 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 98130.242826 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95977.267080 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 95977.267080 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96018.223617 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 96018.223617 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96018.223617 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 96018.223617 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99596.916300 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 99596.916300 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160737.777098 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 160737.777098 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,141 +393,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 465854401 # number of cpu cycles simulated +system.cpu.numCycles 465816448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86523106 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86523106 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1197724 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 82002674 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79454296 # Number of BTB hits +system.cpu.BPredUnit.lookups 86514848 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86514848 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1196192 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 82053392 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79452542 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31142494 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427260156 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86523106 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79454296 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164033620 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5133412 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 157235 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 72542740 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 65499 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9290212 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 538342 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3947 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 271874324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.102439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.406784 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31181464 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427226624 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86514848 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79452542 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164016210 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5124580 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 155814 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 72471814 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36433 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 65503 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9296745 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 539923 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4055 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 271815204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.102878 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.406830 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 108271510 39.82% 39.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1601345 0.59% 40.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71956301 26.47% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 975717 0.36% 67.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1623613 0.60% 67.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2452165 0.90% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1122687 0.41% 69.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1426947 0.52% 69.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82444039 30.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 108229721 39.82% 39.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1589699 0.58% 40.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71960202 26.47% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 971866 0.36% 67.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1623537 0.60% 67.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2454126 0.90% 68.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1122252 0.41% 69.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1424890 0.52% 69.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82438911 30.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 271874324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185730 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.917154 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34951113 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 69967599 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159705810 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3354905 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3894897 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840212837 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1268 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3894897 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37909479 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43328722 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11932417 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159774211 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15034598 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836385126 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 33598 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7166437 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5990052 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 17455 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998119194 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816357971 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816357131 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 840 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964226207 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33892980 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468339 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476044 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 32058525 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17336195 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10280230 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1246899 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 991215 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 830038809 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1256743 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824423080 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186157 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23985276 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36420028 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 206597 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 271874324 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.032368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.413899 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 271815204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185727 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.917157 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34976255 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 69906357 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159691682 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3353316 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3887594 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840157503 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1253 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3887594 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37933620 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43316590 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11886084 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159761513 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15029803 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836332638 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 33622 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7171271 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5982447 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 16586 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998051723 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816227596 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816227024 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 572 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964187470 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33864246 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 467105 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 474137 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 32047540 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17336278 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10273791 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1251259 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 987046 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829985579 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1254715 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824362930 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 185325 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23972130 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36446956 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 204607 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 271815204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.032807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.413784 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82559406 30.37% 30.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18414875 6.77% 37.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10591768 3.90% 41.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7608288 2.80% 43.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75794422 27.88% 71.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3619554 1.33% 73.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72418483 26.64% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 726775 0.27% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 140753 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82518813 30.36% 30.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18405041 6.77% 37.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10590940 3.90% 41.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7611334 2.80% 43.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75787785 27.88% 71.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3621369 1.33% 73.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72414876 26.64% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 725602 0.27% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 139444 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 271874324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 271815204 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 331331 32.21% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547593 53.24% 85.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 149610 14.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 330736 32.15% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 548005 53.27% 85.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150045 14.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 308279 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796609033 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308450 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796558014 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -556,246 +556,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18024617 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9481151 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18020026 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9476440 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824423080 # Type of FU issued -system.cpu.iq.rate 1.769701 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1028534 # FU busy when requested +system.cpu.iq.FU_type_0::total 824362930 # Type of FU issued +system.cpu.iq.rate 1.769716 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1028786 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1922068884 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 855291159 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819794003 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 201 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 398 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825143243 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1662305 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 1921889039 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 855222885 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819729616 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825083173 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1659720 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3372855 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25441 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11901 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1870494 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3372872 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25465 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11865 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1866399 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1917611 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21826 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1917615 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3894897 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28837700 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2469058 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831295552 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 338895 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17336195 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10280230 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 727529 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1778064 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16969 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11901 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 715653 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 628490 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1344143 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822456639 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17610649 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1966440 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3887594 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28830241 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2469402 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831240294 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 338803 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17336278 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10273791 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 725681 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1777576 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17730 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11865 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 713088 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 629130 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1342218 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822392031 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17604275 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1970898 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26845315 # number of memory reference insts executed -system.cpu.iew.exec_branches 83298308 # Number of branches executed -system.cpu.iew.exec_stores 9234666 # Number of stores executed -system.cpu.iew.exec_rate 1.765480 # Inst execution rate -system.cpu.iew.wb_sent 821926439 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819794057 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639752157 # num instructions producing a value -system.cpu.iew.wb_consumers 1045352654 # num instructions consuming a value +system.cpu.iew.exec_refs 26833761 # number of memory reference insts executed +system.cpu.iew.exec_branches 83292230 # Number of branches executed +system.cpu.iew.exec_stores 9229486 # Number of stores executed +system.cpu.iew.exec_rate 1.765485 # Inst execution rate +system.cpu.iew.wb_sent 821862423 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819729668 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639700217 # num instructions producing a value +system.cpu.iew.wb_consumers 1045258728 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.759765 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611996 # average fanout of values written-back +system.cpu.iew.wb_rate 1.759770 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612002 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24913133 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1050144 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1202812 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267994872 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.008567 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.862606 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24883748 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1050106 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1201289 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267943051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.009053 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.862554 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95708063 35.71% 35.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12360558 4.61% 40.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3940570 1.47% 41.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74894252 27.95% 69.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2417220 0.90% 70.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1553799 0.58% 71.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1057768 0.39% 71.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70929617 26.47% 98.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5133025 1.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95668224 35.70% 35.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12347484 4.61% 40.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3939395 1.47% 41.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74898098 27.95% 69.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2419496 0.90% 70.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1554494 0.58% 71.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1057385 0.39% 71.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70928163 26.47% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5130312 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267994872 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407876198 # Number of instructions committed -system.cpu.commit.committedOps 806280456 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267943051 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407858031 # Number of instructions committed +system.cpu.commit.committedOps 806254969 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22373073 # Number of memory references committed -system.cpu.commit.loads 13963337 # Number of loads committed -system.cpu.commit.membars 471701 # Number of memory barriers committed -system.cpu.commit.branches 82186197 # Number of branches committed +system.cpu.commit.refs 22370795 # Number of memory references committed +system.cpu.commit.loads 13963403 # Number of loads committed +system.cpu.commit.membars 471705 # Number of memory barriers committed +system.cpu.commit.branches 82181312 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735221140 # Number of committed integer instructions. +system.cpu.commit.int_insts 735195017 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5133025 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5130312 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1093976833 # The number of ROB reads -system.cpu.rob.rob_writes 1666301286 # The number of ROB writes -system.cpu.timesIdled 1419086 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 193980077 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9870026331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407876198 # Number of Instructions Simulated -system.cpu.committedOps 806280456 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407876198 # Number of Instructions Simulated -system.cpu.cpi 1.142147 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.142147 # CPI: Total CPI of All Threads -system.cpu.ipc 0.875544 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.875544 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508347107 # number of integer regfile reads -system.cpu.int_regfile_writes 977902256 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.misc_regfile_reads 265221380 # number of misc regfile reads -system.cpu.misc_regfile_writes 402568 # number of misc regfile writes -system.cpu.icache.replacements 1070981 # number of replacements -system.cpu.icache.tagsinuse 510.788530 # Cycle average of tags in use -system.cpu.icache.total_refs 8144587 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1071493 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.601157 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1093872885 # The number of ROB reads +system.cpu.rob.rob_writes 1666184214 # The number of ROB writes +system.cpu.timesIdled 1421273 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 194001244 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9862059849 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407858031 # Number of Instructions Simulated +system.cpu.committedOps 806254969 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407858031 # Number of Instructions Simulated +system.cpu.cpi 1.142104 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.142104 # CPI: Total CPI of All Threads +system.cpu.ipc 0.875577 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.875577 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508209791 # number of integer regfile reads +system.cpu.int_regfile_writes 977816443 # number of integer regfile writes +system.cpu.fp_regfile_reads 52 # number of floating regfile reads +system.cpu.misc_regfile_reads 265196274 # number of misc regfile reads +system.cpu.misc_regfile_writes 402502 # number of misc regfile writes +system.cpu.icache.replacements 1071989 # number of replacements +system.cpu.icache.tagsinuse 510.817098 # Cycle average of tags in use +system.cpu.icache.total_refs 8149627 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1072501 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.598713 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 147426882000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.788530 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997634 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997634 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8144587 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8144587 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8144587 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8144587 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8144587 # number of overall hits -system.cpu.icache.overall_hits::total 8144587 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1145619 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1145619 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1145619 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1145619 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1145619 # number of overall misses -system.cpu.icache.overall_misses::total 1145619 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18957217490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18957217490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18957217490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18957217490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18957217490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18957217490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9290206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9290206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9290206 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9290206 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9290206 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9290206 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123315 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123315 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123315 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123315 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123315 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123315 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16547.576018 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16547.576018 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16547.576018 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16547.576018 # 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mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115580 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115580 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13787.270193 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13787.270193 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13787.270193 # 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average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,78 +804,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1799 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1799 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10696 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10696 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10696 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10696 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10696 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10696 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143761538 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143761538 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143761538 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143761538 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143761538 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143761538 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245119 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245119 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245102 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245102 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245102 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245102 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13440.682311 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13440.682311 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13440.682311 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10825 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10825 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10825 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10825 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10825 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10825 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 145034027 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 145034027 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 145034027 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 145034027 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 145034027 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 145034027 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245181 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245181 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245165 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245165 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13398.062540 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109374 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.962684 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 139077 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109389 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.271398 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108961672000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.962684 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810168 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.810168 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139087 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 139087 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139087 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 139087 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139087 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 139087 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110364 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110364 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110364 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110364 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110364 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110364 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2009314000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2009314000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2009314000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2009314000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2009314000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2009314000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249451 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 249451 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249451 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 249451 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249451 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 249451 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442428 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442428 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442428 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442428 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442428 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442428 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18206.244790 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18206.244790 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18206.244790 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18206.244790 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18206.244790 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18206.244790 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 109056 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.865602 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 139886 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109072 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.282511 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5108962066000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.865602 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866600 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.866600 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139886 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 139886 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 139886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139886 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 139886 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110096 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110096 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110096 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110096 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110096 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110096 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2001823500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2001823500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2001823500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2001823500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2001823500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2001823500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249982 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 249982 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249982 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 249982 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249982 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 249982 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.440416 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.440416 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.440416 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.440416 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.440416 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.440416 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18182.527067 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18182.527067 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18182.527067 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -884,146 +884,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35688 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35688 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110364 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110364 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110364 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110364 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110364 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110364 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1675589507 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1675589507 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1675589507 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442428 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442428 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442428 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15182.391967 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15182.391967 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15182.391967 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35215 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35215 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110096 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110096 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110096 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110096 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110096 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110096 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1668892003 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1668892003 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1668892003 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.440416 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.440416 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.440416 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15158.516231 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1671342 # number of replacements -system.cpu.dcache.tagsinuse 511.998194 # Cycle average of tags in use -system.cpu.dcache.total_refs 19219573 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1671854 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.495964 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1672208 # number of replacements +system.cpu.dcache.tagsinuse 511.998155 # Cycle average of tags in use +system.cpu.dcache.total_refs 19212274 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1672720 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.485649 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 35774000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.998194 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.998155 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11132776 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11132776 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8081984 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8081984 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19214760 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19214760 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19214760 # number of overall hits -system.cpu.dcache.overall_hits::total 19214760 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2269875 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2269875 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318465 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318465 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2588340 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2588340 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2588340 # number of overall misses -system.cpu.dcache.overall_misses::total 2588340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 48782293500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48782293500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10759861985 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10759861985 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 59542155485 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 59542155485 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 59542155485 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 59542155485 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13402651 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13402651 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8400449 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8400449 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21803100 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21803100 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21803100 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21803100 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169360 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169360 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037910 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037910 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118714 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118714 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118714 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21491.180572 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21491.180572 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33786.638987 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33786.638987 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23003.993094 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23003.993094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23003.993094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23003.993094 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 188390485 # number of cycles access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 11127928 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11127928 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8079547 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8079547 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19207475 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19207475 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19207475 # number of overall hits +system.cpu.dcache.overall_hits::total 19207475 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2271021 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2271021 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318564 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318564 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2589585 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2589585 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2589585 # number of overall misses +system.cpu.dcache.overall_misses::total 2589585 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48812772000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48812772000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10760956984 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10760956984 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 59573728984 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 59573728984 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 59573728984 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 59573728984 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13398949 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13398949 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8398111 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8398111 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21797060 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21797060 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21797060 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21797060 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169492 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169492 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037933 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037933 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118804 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118804 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118804 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118804 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21493.756333 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21493.756333 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33779.576424 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33779.576424 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23005.125912 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23005.125912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23005.125912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23005.125912 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 188289984 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 47569 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 47618 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3960.362526 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3954.176656 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1572665 # number of writebacks -system.cpu.dcache.writebacks::total 1572665 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 885789 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 885789 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26582 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 26582 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 912371 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912371 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 912371 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912371 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1384086 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1384086 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291883 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291883 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1675969 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1675969 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1675969 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1675969 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25963695523 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25963695523 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9454770488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9454770488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35418466011 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 35418466011 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35418466011 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 35418466011 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96735790500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96735790500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2476089500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2476089500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99211880000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99211880000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103270 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103270 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034746 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034746 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076868 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076868 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076868 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076868 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18758.729965 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18758.729965 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32392.330105 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32392.330105 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21133.127171 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21133.127171 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21133.127171 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21133.127171 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1573408 # number of writebacks +system.cpu.dcache.writebacks::total 1573408 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 886097 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 886097 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26577 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26577 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912674 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912674 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912674 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912674 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1384924 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1384924 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291987 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291987 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1676911 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1676911 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1676911 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1676911 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25980128023 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25980128023 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9456082986 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9456082986 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35436211009 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 35436211009 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35436211009 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 35436211009 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96735395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96735395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2475863500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2475863500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99211259000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99211259000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034768 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034768 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076933 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076933 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076933 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076933 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18759.244567 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18759.244567 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32385.287653 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32385.287653 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21131.837652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21131.837652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21131.837652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21131.837652 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 5b9902e79..56312634f 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.274137 # Number of seconds simulated -sim_ticks 274137499500 # Number of ticks simulated -final_tick 274137499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 274137453500 # Number of ticks simulated +final_tick 274137453500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167497 # Simulator instruction rate (inst/s) -host_op_rate 167497 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76292716 # Simulator tick rate (ticks/s) -host_mem_usage 218988 # Number of bytes of host memory used -host_seconds 3593.23 # Real time elapsed on the host +host_inst_rate 134061 # Simulator instruction rate (inst/s) +host_op_rate 134061 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61063086 # Simulator tick rate (ticks/s) +host_mem_usage 219148 # Number of bytes of host memory used +host_seconds 4489.41 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -24,32 +24,32 @@ system.physmem.num_reads::total 26157 # Nu system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory system.physmem.num_writes::total 891 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5910260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6106600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5910261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6106601 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5910260 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6314612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5910261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6314613 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114518785 # DTB read hits +system.cpu.dtb.read_hits 114518787 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114521416 # DTB read accesses -system.cpu.dtb.write_hits 39662429 # DTB write hits +system.cpu.dtb.read_accesses 114521418 # DTB read accesses +system.cpu.dtb.write_hits 39662426 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39664731 # DTB write accesses -system.cpu.dtb.data_hits 154181214 # DTB hits +system.cpu.dtb.write_accesses 39664728 # DTB write accesses +system.cpu.dtb.data_hits 154181213 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154186147 # DTB accesses +system.cpu.dtb.data_accesses 154186146 # DTB accesses system.cpu.itb.fetch_hits 25086764 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 548275000 # number of cpu cycles simulated +system.cpu.numCycles 548274908 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups @@ -80,13 +80,13 @@ system.cpu.branch_predictor.RASInCorrect 6 # Nu system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541561070 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 541561072 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005415916 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1005415918 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255070177 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 255070175 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 155050348 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken). @@ -97,12 +97,12 @@ system.cpu.execution_unit.executions 412334459 # Nu system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 539843930 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 539843953 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 672410 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59138192 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489136808 # Number of cycles cpu stages are processed. -system.cpu.activity 89.213772 # Percentage of cycles cpu is active +system.cpu.timesIdled 672397 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59138093 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489136815 # Number of cycles cpu stages are processed. +system.cpu.activity 89.213788 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -120,28 +120,28 @@ system.cpu.cpi_total 0.910972 # CP system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 209383014 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338891986 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.810585 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 237433241 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310841759 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.694498 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 206489440 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341785560 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.338345 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 436702963 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 209382923 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338891985 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.810595 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 237433150 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310841758 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 56.694507 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 206489347 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341785561 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.338355 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 436702871 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.349649 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201266098 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347008902 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.291031 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 20.349652 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 201266007 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347008901 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.291042 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.512372 # Cycle average of tags in use +system.cpu.icache.tagsinuse 728.512382 # Cycle average of tags in use system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.512372 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 728.512382 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits @@ -220,12 +220,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801 system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.836595 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4093.836594 # Cycle average of tags in use system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.836595 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.836594 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits @@ -244,14 +244,14 @@ system.cpu.dcache.demand_misses::cpu.data 1559322 # n system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses system.cpu.dcache.overall_misses::total 1559322 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7771987500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228669000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30228669000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38000656500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38000656500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38000656500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38000656500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7771987000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228329000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30228329000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38000316000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38000316000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38000316000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38000316000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -268,19 +268,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.010128 system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.662796 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.662796 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25930.061238 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25930.061238 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24369.986763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24369.986763 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28255500 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.661525 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.661525 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25929.769587 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25929.769587 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24369.768399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24369.768399 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28216000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3561 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3564 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7934.709351 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7916.947250 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136800000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136800000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820778500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7820778500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820778500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7820778500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136655500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136655500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820633500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7820633500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820633500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7820633500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,24 +318,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.732070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.732070 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.652219 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.652219 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.729586 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.729586 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.083686 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.083686 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 917 # number of replacements -system.cpu.l2cache.tagsinuse 22837.818259 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22837.818508 # Cycle average of tags in use system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21635.297134 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 719.415397 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 483.105728 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21635.297320 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 719.415407 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 483.105781 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy @@ -365,16 +365,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 841 # system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses system.cpu.l2cache.overall_misses::total 26157 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 260244500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215316500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1215316500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 260244000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215397500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1215397500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1430177000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1475561000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1430257500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1475641500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1430177000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1475561000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1430257500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1475641500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses) @@ -400,21 +400,21 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.606796 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52458.072969 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57337.068315 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57337.068315 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.485437 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.972183 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57340.889791 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57340.889791 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56411.706235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56414.783805 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56411.706235 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3459500 # number of cycles access was blocked +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56414.783805 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3419500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 116 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 115 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29823.275862 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29734.782609 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -434,14 +434,14 @@ system.cpu.l2cache.overall_mshr_misses::total 26157 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954428500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954428500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954509500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954509500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119789500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1154935500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119870500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1155016500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119789500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1154935500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119870500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1155016500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses @@ -456,14 +456,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45028.708247 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45028.708247 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45032.529723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45032.529723 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 5f66a5052..f78f2bef4 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.135505 # Number of seconds simulated -sim_ticks 135504709500 # Number of ticks simulated -final_tick 135504709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.135471 # Number of seconds simulated +sim_ticks 135471331500 # Number of ticks simulated +final_tick 135471331500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 302966 # Simulator instruction rate (inst/s) -host_op_rate 302966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72589653 # Simulator tick rate (ticks/s) -host_mem_usage 220016 # Number of bytes of host memory used -host_seconds 1866.72 # Real time elapsed on the host +host_inst_rate 255662 # Simulator instruction rate (inst/s) +host_op_rate 255662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61240707 # Simulator tick rate (ticks/s) +host_mem_usage 220172 # Number of bytes of host memory used +host_seconds 2212.11 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1627200 # Number of bytes read from this memory -system.physmem.bytes_read::total 1688960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 58880 # Number of bytes written to this memory -system.physmem.bytes_written::total 58880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25425 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26390 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 920 # Number of write requests responded to by this memory -system.physmem.num_writes::total 920 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 455778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12008439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12464216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 455778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 455778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 434524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 434524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 434524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 455778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12008439 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12898740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627392 # Number of bytes read from this memory +system.physmem.bytes_read::total 1689280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 58944 # Number of bytes written to this memory +system.physmem.bytes_written::total 58944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25428 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26395 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 921 # Number of write requests responded to by this memory +system.physmem.num_writes::total 921 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 456835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12012815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12469649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 456835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 456835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 435103 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 435103 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 435103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 456835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12012815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12904752 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123973202 # DTB read hits -system.cpu.dtb.read_misses 28801 # DTB read misses +system.cpu.dtb.read_hits 123970603 # DTB read hits +system.cpu.dtb.read_misses 28720 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 124002003 # DTB read accesses -system.cpu.dtb.write_hits 40826098 # DTB write hits -system.cpu.dtb.write_misses 43038 # DTB write misses +system.cpu.dtb.read_accesses 123999323 # DTB read accesses +system.cpu.dtb.write_hits 40821734 # DTB write hits +system.cpu.dtb.write_misses 42993 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40869136 # DTB write accesses -system.cpu.dtb.data_hits 164799300 # DTB hits -system.cpu.dtb.data_misses 71839 # DTB misses +system.cpu.dtb.write_accesses 40864727 # DTB write accesses +system.cpu.dtb.data_hits 164792337 # DTB hits +system.cpu.dtb.data_misses 71713 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164871139 # DTB accesses -system.cpu.itb.fetch_hits 66654125 # ITB hits +system.cpu.dtb.data_accesses 164864050 # DTB accesses +system.cpu.itb.fetch_hits 66629589 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66654164 # ITB accesses +system.cpu.itb.fetch_accesses 66629628 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,140 +67,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 271009420 # number of cpu cycles simulated +system.cpu.numCycles 270942664 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78550084 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72909802 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3049618 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42960098 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41697412 # Number of BTB hits +system.cpu.BPredUnit.lookups 78540801 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72908130 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3045250 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42784442 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41679238 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1627945 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 225 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68633140 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 712310900 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78550084 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43325357 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119402153 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13096957 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 72942972 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1625962 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68608304 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 712216936 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78540801 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43305200 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119376688 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13084394 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72934666 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66654125 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 952316 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 270973447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.628711 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.455670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 66629589 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 948387 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 270906593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.629013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.455853 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151571294 55.94% 55.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10370513 3.83% 59.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11843929 4.37% 64.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10611726 3.92% 68.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6997698 2.58% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2669321 0.99% 71.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3542857 1.31% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3106060 1.15% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70260049 25.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151529905 55.93% 55.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10364245 3.83% 59.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11839822 4.37% 64.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10610225 3.92% 68.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6991463 2.58% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2667986 0.98% 71.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3540757 1.31% 72.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3105472 1.15% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70256718 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270973447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289843 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.628362 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 86239898 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56889648 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104078394 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13772489 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9993018 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3907857 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703284399 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4152 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9993018 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 94515684 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12291800 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1567 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104313558 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49857820 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 691204157 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5604 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37465189 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6251536 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527653035 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 907560525 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 907557502 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3023 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 270906593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289880 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.628663 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 86218522 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56873885 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104030125 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13799230 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9984831 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3903379 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1089 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703205131 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9984831 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 94485896 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12289062 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1666 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104300720 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49844418 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 691143238 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5409 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 37459217 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 6250189 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527606706 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 907468723 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 907465803 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2920 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63798146 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 98 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 109 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 110554649 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129201281 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42494660 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14706454 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9724071 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626942555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608726605 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 349964 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60693556 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33842727 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 71 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270973447 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.246444 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.833475 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63751817 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 122 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 110700400 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129196942 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42484118 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14760258 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9703253 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626892028 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 99 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608695355 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 350153 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60644934 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33797171 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 82 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270906593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.246883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.833563 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55588929 20.51% 20.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55068872 20.32% 40.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 54063102 19.95% 60.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36829632 13.59% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31174989 11.50% 85.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23761374 8.77% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10484912 3.87% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3386761 1.25% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 614876 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55377469 20.44% 20.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55325876 20.42% 40.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 54071762 19.96% 60.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36846414 13.60% 74.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30891550 11.40% 85.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23842623 8.80% 94.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10560250 3.90% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3379294 1.25% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 611355 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270973447 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270906593 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2718607 75.19% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 33 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 573635 15.86% 91.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323505 8.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2755770 75.48% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 573872 15.72% 91.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 321392 8.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441168683 72.47% 72.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7348 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441149057 72.47% 72.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7297 0.00% 72.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued @@ -228,84 +228,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126287390 20.75% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41263140 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126283457 20.75% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41255500 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608726605 # Type of FU issued -system.cpu.iq.rate 2.246146 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3615780 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005940 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1492388483 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 687638825 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598965859 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3918 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2476 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608695355 # Type of FU issued +system.cpu.iq.rate 2.246584 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3651064 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005998 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1492294648 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 687539732 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598944947 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3872 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2425 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1713 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612340430 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1955 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12180256 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 612344476 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1943 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12180058 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14687239 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33196 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5150 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3043339 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14682900 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33847 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5158 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3032797 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6743 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162277 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6745 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 162513 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9993018 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 593522 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 81920 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 671227772 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1733098 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129201281 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42494660 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9721 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 904 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5150 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1349008 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2205914 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3554922 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602873827 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 124002105 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5852778 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9984831 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 591994 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 80208 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 671175480 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1733020 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129196942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42484118 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 99 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8476 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 909 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5158 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342632 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2208039 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3550671 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602850413 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123999444 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5844942 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 44285129 # number of nop insts executed -system.cpu.iew.exec_refs 164888589 # number of memory reference insts executed -system.cpu.iew.exec_branches 67046898 # Number of branches executed -system.cpu.iew.exec_stores 40886484 # Number of stores executed -system.cpu.iew.exec_rate 2.224549 # Inst execution rate -system.cpu.iew.wb_sent 600233130 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598967572 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417280903 # num instructions producing a value -system.cpu.iew.wb_consumers 532263406 # num instructions consuming a value +system.cpu.iew.exec_nop 44283353 # number of nop insts executed +system.cpu.iew.exec_refs 164880697 # number of memory reference insts executed +system.cpu.iew.exec_branches 67045865 # Number of branches executed +system.cpu.iew.exec_stores 40881253 # Number of stores executed +system.cpu.iew.exec_rate 2.225011 # Inst execution rate +system.cpu.iew.wb_sent 600209978 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598946660 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417271834 # num instructions producing a value +system.cpu.iew.wb_consumers 532298467 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.210136 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.783974 # average fanout of values written-back +system.cpu.iew.wb_rate 2.210603 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.783906 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69254422 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69202424 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3048560 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 260980429 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.306138 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.692981 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3044252 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 260921762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.306657 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.693748 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82002311 31.42% 31.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72802901 27.90% 59.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26180796 10.03% 69.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8233037 3.15% 72.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10839669 4.15% 76.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20863917 7.99% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6243794 2.39% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3659698 1.40% 88.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30154306 11.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 81870366 31.38% 31.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72918515 27.95% 59.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26232772 10.05% 69.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8204750 3.14% 72.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10788682 4.13% 76.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20849092 7.99% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6203888 2.38% 87.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3594438 1.38% 88.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30259259 11.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 260980429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 260921762 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30154306 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30259259 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 901873119 # The number of ROB reads -system.cpu.rob.rob_writes 1352238413 # The number of ROB writes -system.cpu.timesIdled 924 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35973 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 901657501 # The number of ROB reads +system.cpu.rob.rob_writes 1352126118 # The number of ROB writes +system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 36071 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.479194 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.479194 # CPI: Total CPI of All Threads -system.cpu.ipc 2.086837 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.086837 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848955638 # number of integer regfile reads -system.cpu.int_regfile_writes 492807399 # number of integer regfile writes -system.cpu.fp_regfile_reads 373 # number of floating regfile reads +system.cpu.cpi 0.479076 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.479076 # CPI: Total CPI of All Threads +system.cpu.ipc 2.087351 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.087351 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848921354 # number of integer regfile reads +system.cpu.int_regfile_writes 492788777 # number of integer regfile writes +system.cpu.fp_regfile_reads 376 # number of floating regfile reads system.cpu.fp_regfile_writes 51 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 45 # number of replacements -system.cpu.icache.tagsinuse 834.184340 # Cycle average of tags in use -system.cpu.icache.total_refs 66652701 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 988 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67462.247976 # Average number of references to valid blocks. +system.cpu.icache.replacements 46 # number of replacements +system.cpu.icache.tagsinuse 834.348638 # Cycle average of tags in use +system.cpu.icache.total_refs 66628172 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67301.183838 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 834.184340 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.407317 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.407317 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66652701 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66652701 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66652701 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66652701 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66652701 # number of overall hits -system.cpu.icache.overall_hits::total 66652701 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1424 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1424 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1424 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1424 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1424 # number of overall misses -system.cpu.icache.overall_misses::total 1424 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 52187000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 52187000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 52187000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 52187000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 52187000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 52187000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66654125 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66654125 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66654125 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66654125 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66654125 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66654125 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 834.348638 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.407397 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.407397 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66628172 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66628172 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66628172 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66628172 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66628172 # number of overall hits +system.cpu.icache.overall_hits::total 66628172 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1417 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1417 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1417 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1417 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1417 # number of overall misses +system.cpu.icache.overall_misses::total 1417 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51973000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51973000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51973000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51973000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51973000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51973000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66629589 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66629589 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66629589 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66629589 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66629589 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66629589 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36648.174157 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36648.174157 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36648.174157 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36648.174157 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36648.174157 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36648.174157 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36678.193366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36678.193366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36678.193366 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36678.193366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36678.193366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36678.193366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,296 +388,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 436 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 436 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 436 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 988 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 988 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 988 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 988 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 988 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37189000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37189000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37189000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37189000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37189000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37189000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 427 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 427 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 427 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 427 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 427 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 427 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 990 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 990 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 990 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 990 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 990 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37151000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37151000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37151000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37151000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37151000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37151000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37640.688259 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37640.688259 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37640.688259 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37640.688259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37640.688259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37640.688259 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37526.262626 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37526.262626 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37526.262626 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37526.262626 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37526.262626 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37526.262626 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460628 # number of replacements -system.cpu.dcache.tagsinuse 4093.382195 # Cycle average of tags in use -system.cpu.dcache.total_refs 148766128 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464724 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 320.117162 # Average number of references to valid blocks. +system.cpu.dcache.replacements 460520 # number of replacements +system.cpu.dcache.tagsinuse 4093.381550 # Cycle average of tags in use +system.cpu.dcache.total_refs 148763474 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464616 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 320.185861 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 141133000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.382195 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.381550 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999361 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999361 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 111085210 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 111085210 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37680869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37680869 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 148766079 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 148766079 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 148766079 # number of overall hits -system.cpu.dcache.overall_hits::total 148766079 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 577881 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 577881 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1770452 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1770452 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2348333 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2348333 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2348333 # number of overall misses -system.cpu.dcache.overall_misses::total 2348333 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8220967500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8220967500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 45275400067 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45275400067 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 31000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 31000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 53496367567 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53496367567 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 53496367567 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53496367567 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 111663091 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 111663091 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 111082723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111082723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37680696 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37680696 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 55 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 55 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 148763419 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 148763419 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 148763419 # number of overall hits +system.cpu.dcache.overall_hits::total 148763419 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 577759 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 577759 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1770625 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1770625 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2348384 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2348384 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2348384 # number of overall misses +system.cpu.dcache.overall_misses::total 2348384 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8217146500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8217146500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 45283421033 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45283421033 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 15500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 15500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53500567533 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53500567533 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53500567533 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53500567533 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111660482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111660482 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 51 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 51 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151114412 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151114412 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151114412 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151114412 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005175 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005175 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.044877 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.044877 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.039216 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.039216 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015540 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015540 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015540 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015540 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14226.056057 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14226.056057 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25572.791619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25572.791619 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151111803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151111803 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151111803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151111803 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005174 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005174 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.044881 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.044881 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017857 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017857 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015541 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015541 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015541 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015541 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14222.446556 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14222.446556 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25574.823033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25574.823033 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22780.571396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22780.571396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22780.571396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22780.571396 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 267496 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22781.865118 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22781.865118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22781.865118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22781.865118 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 260996 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 204500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 99 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2286.290598 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2636.323232 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 20450 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444923 # number of writebacks -system.cpu.dcache.writebacks::total 444923 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367661 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 367661 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1515948 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1515948 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1883609 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1883609 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1883609 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1883609 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210220 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210220 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254504 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254504 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464724 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464724 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464724 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464724 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1663922500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1663922500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5123963342 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5123963342 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6787885842 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6787885842 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6787885842 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6787885842 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 444797 # number of writebacks +system.cpu.dcache.writebacks::total 444797 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367652 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 367652 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1516116 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1516116 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1883768 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1883768 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1883768 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1883768 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210107 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210107 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254509 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254509 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464616 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464616 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464616 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464616 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1661680500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1661680500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5124983839 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5124983839 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6786664339 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6786664339 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6786664339 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6786664339 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003075 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7915.148416 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7915.148416 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20133.134811 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20133.134811 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14606.273491 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14606.273491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14606.273491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14606.273491 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7908.734597 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7908.734597 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20136.748952 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20136.748952 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14607.039661 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14607.039661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14607.039661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14607.039661 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 949 # number of replacements -system.cpu.l2cache.tagsinuse 22947.355822 # Cycle average of tags in use -system.cpu.l2cache.total_refs 555465 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23383 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.755078 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 950 # number of replacements +system.cpu.l2cache.tagsinuse 22952.523790 # Cycle average of tags in use +system.cpu.l2cache.total_refs 555154 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23388 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.736703 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21503.111139 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 828.347740 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 615.896944 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.656223 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025279 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018796 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.700298 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21504.844350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 828.512552 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 619.166888 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.656276 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.025284 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.018895 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.700455 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 205921 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 205944 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 444923 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 444923 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233378 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 233378 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 205806 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 205829 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 444797 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 444797 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 233382 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 233382 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 439299 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 439322 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 439188 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 439211 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 23 # 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Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 373e7efc5..c74978b2c 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164812 # Number of seconds simulated -sim_ticks 164812294500 # Number of ticks simulated -final_tick 164812294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164804 # Number of seconds simulated +sim_ticks 164803697500 # Number of ticks simulated +final_tick 164803697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186522 # Simulator instruction rate (inst/s) -host_op_rate 197094 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53926880 # Simulator tick rate (ticks/s) -host_mem_usage 234728 # Number of bytes of host memory used -host_seconds 3056.22 # Real time elapsed on the host -sim_insts 570052720 # Number of instructions simulated -sim_ops 602360926 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1770688 # Number of bytes read from this memory -system.physmem.bytes_read::total 1818880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 203712 # Number of bytes written to this memory -system.physmem.bytes_written::total 203712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 753 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27667 # Number of read requests responded to by this memory -system.physmem.num_reads::total 28420 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3183 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3183 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 292405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10743665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11036070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 292405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 292405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1236024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1236024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1236024 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 292405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10743665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12272094 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 225505 # Simulator instruction rate (inst/s) +host_op_rate 238286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65194032 # Simulator tick rate (ticks/s) +host_mem_usage 234780 # Number of bytes of host memory used +host_seconds 2527.90 # Real time elapsed on the host +sim_insts 570052730 # Number of instructions simulated +sim_ops 602360936 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1769280 # Number of bytes read from this memory +system.physmem.bytes_read::total 1816896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 202944 # Number of bytes written to this memory +system.physmem.bytes_written::total 202944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27645 # Number of read requests responded to by this memory +system.physmem.num_reads::total 28389 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3171 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3171 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 288926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10735681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11024607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 288926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 288926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1231429 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1231429 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1231429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 288926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10735681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12256036 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,106 +77,106 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329624590 # number of cpu cycles simulated +system.cpu.numCycles 329607396 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85521151 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80320824 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2362426 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47149352 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46837857 # Number of BTB hits +system.cpu.BPredUnit.lookups 85521262 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80324005 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2361364 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47163773 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46836425 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1443093 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 967 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68941793 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669884423 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85521151 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48280950 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130081078 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13500418 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119459363 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1442496 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 971 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68931742 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669855776 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85521262 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48278921 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130072968 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13495551 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119465420 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 639 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67507706 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 807322 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 329533342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166395 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.195647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 697 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67497575 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 806206 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 329517095 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.166390 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.195660 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199452502 60.53% 60.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20948711 6.36% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4950582 1.50% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14318865 4.35% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8979173 2.72% 75.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9434613 2.86% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4385548 1.33% 79.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5816824 1.77% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61246524 18.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 199444353 60.53% 60.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20947099 6.36% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4950101 1.50% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14318334 4.35% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8976585 2.72% 75.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9434873 2.86% 78.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4385962 1.33% 79.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5814434 1.76% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61245354 18.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 329533342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259450 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.032265 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93614628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96158900 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108189069 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20521940 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11048805 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4786965 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1741 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 706200361 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6232 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11048805 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107837275 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14152380 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49672 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114426981 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82018229 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697376779 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 154 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59681814 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20119568 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 658 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723981883 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3242139777 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3242139649 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 329517095 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259464 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.032284 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93615293 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96153951 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108189677 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20513543 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11044631 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4783839 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1715 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 706162861 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6102 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11044631 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107837587 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14124315 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49845 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114419609 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82041108 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697343102 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59702950 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20121716 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723953896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241969745 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241969617 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96562694 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6452 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6400 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169999822 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172950765 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80642212 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21622434 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28168591 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 682111188 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4787 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646911424 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1425738 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79572817 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 198257861 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1856 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 329533342 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.963114 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.727328 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419205 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96534691 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6461 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6411 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169960309 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172942863 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80636505 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21738448 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28392401 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 682081084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4755 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646873471 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1427255 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79546312 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 198336630 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1822 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 329517095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.963095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.726025 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69109124 20.97% 20.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85502964 25.95% 46.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75902592 23.03% 69.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 41003361 12.44% 82.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28586147 8.67% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15096087 4.58% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5691070 1.73% 97.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6514226 1.98% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2127771 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69073062 20.96% 20.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85428169 25.93% 46.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76011979 23.07% 69.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40983157 12.44% 82.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28619491 8.69% 91.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15088313 4.58% 95.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5676552 1.72% 97.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6597944 2.00% 99.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2038428 0.62% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 329533342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 329517095 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205938 5.35% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205689 5.35% 5.35% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.35% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.35% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.35% # attempts to use FU when none available @@ -205,13 +205,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.35% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.35% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.35% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2629007 68.31% 73.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1013747 26.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2625601 68.27% 73.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1014507 26.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403964135 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6565 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403948716 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -239,157 +239,157 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166144548 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76796173 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166134463 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76783723 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646911424 # Type of FU issued -system.cpu.iq.rate 1.962570 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3848692 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005949 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1628630584 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761700595 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638589501 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646873471 # Type of FU issued +system.cpu.iq.rate 1.962558 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3845797 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005945 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1628537053 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761643882 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638542497 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650760096 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650719248 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30444381 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30433842 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23997945 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 128330 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12058 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10420972 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23990041 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 126515 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11992 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10415263 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12743 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 33964 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12768 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35443 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11048805 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 670880 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80193 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682182162 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 671811 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172950765 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80642212 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3436 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21821 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3936 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12058 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1313101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1582689 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2895790 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642749974 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 164016211 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4161450 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11044631 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 670742 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 80165 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682151912 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 669326 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172942863 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80636505 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3402 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21938 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3947 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11992 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1313002 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1582154 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2895156 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642705109 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 164002272 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4168362 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66187 # number of nop insts executed -system.cpu.iew.exec_refs 240022824 # number of memory reference insts executed -system.cpu.iew.exec_branches 74673150 # Number of branches executed -system.cpu.iew.exec_stores 76006613 # Number of stores executed -system.cpu.iew.exec_rate 1.949945 # Inst execution rate -system.cpu.iew.wb_sent 640083965 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638589517 # cumulative count of insts written-back -system.cpu.iew.wb_producers 419034564 # num instructions producing a value -system.cpu.iew.wb_consumers 650591569 # num instructions consuming a value +system.cpu.iew.exec_nop 66073 # number of nop insts executed +system.cpu.iew.exec_refs 239994615 # number of memory reference insts executed +system.cpu.iew.exec_branches 74670654 # Number of branches executed +system.cpu.iew.exec_stores 75992343 # Number of stores executed +system.cpu.iew.exec_rate 1.949911 # Inst execution rate +system.cpu.iew.wb_sent 640039570 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638542513 # cumulative count of insts written-back +system.cpu.iew.wb_producers 419139421 # num instructions producing a value +system.cpu.iew.wb_consumers 650719166 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937324 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644082 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937282 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644117 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79830456 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2422889 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 318484538 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.891335 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233401 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 79800581 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2933 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2421751 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 318472465 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.891407 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233429 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93876011 29.48% 29.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104566020 32.83% 62.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43293403 13.59% 75.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8795442 2.76% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26035150 8.17% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12750697 4.00% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7572699 2.38% 93.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1269382 0.40% 93.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20325734 6.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93877002 29.48% 29.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104551194 32.83% 62.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43288621 13.59% 75.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8793504 2.76% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26039044 8.18% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12759663 4.01% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7570973 2.38% 93.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1268002 0.40% 93.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20324462 6.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 318484538 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052771 # Number of instructions committed -system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 318472465 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052781 # Number of instructions committed +system.cpu.commit.committedOps 602360987 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174060 # Number of memory references committed -system.cpu.commit.loads 148952820 # Number of loads committed +system.cpu.commit.refs 219174064 # Number of memory references committed +system.cpu.commit.loads 148952822 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828827 # Number of branches committed +system.cpu.commit.branches 70828829 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523539 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523547 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20325734 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20324462 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 980349625 # The number of ROB reads -system.cpu.rob.rob_writes 1375464218 # The number of ROB writes -system.cpu.timesIdled 6594 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 91248 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052720 # Number of Instructions Simulated -system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated -system.cpu.cpi 0.578235 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.578235 # CPI: Total CPI of All Threads -system.cpu.ipc 1.729400 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.729400 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210711882 # number of integer regfile reads -system.cpu.int_regfile_writes 664273083 # number of integer regfile writes +system.cpu.rob.rob_reads 980308959 # The number of ROB reads +system.cpu.rob.rob_writes 1375400190 # The number of ROB writes +system.cpu.timesIdled 6717 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 90301 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052730 # Number of Instructions Simulated +system.cpu.committedOps 602360936 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052730 # Number of Instructions Simulated +system.cpu.cpi 0.578205 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.578205 # CPI: Total CPI of All Threads +system.cpu.ipc 1.729490 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.729490 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210477235 # number of integer regfile reads +system.cpu.int_regfile_writes 664240650 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905231466 # number of misc regfile reads -system.cpu.misc_regfile_writes 3110 # number of misc regfile writes -system.cpu.icache.replacements 57 # number of replacements -system.cpu.icache.tagsinuse 692.699547 # Cycle average of tags in use -system.cpu.icache.total_refs 67506606 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 819 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 82425.648352 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905174301 # number of misc regfile reads +system.cpu.misc_regfile_writes 3114 # number of misc regfile writes +system.cpu.icache.replacements 52 # number of replacements +system.cpu.icache.tagsinuse 687.184912 # Cycle average of tags in use +system.cpu.icache.total_refs 67496491 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 806 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 83742.544665 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 692.699547 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.338232 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.338232 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67506606 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67506606 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67506606 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67506606 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67506606 # number of overall hits -system.cpu.icache.overall_hits::total 67506606 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1100 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1100 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1100 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1100 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1100 # number of overall misses -system.cpu.icache.overall_misses::total 1100 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38665000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38665000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38665000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38665000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38665000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38665000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67507706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67507706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67507706 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67507706 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67507706 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67507706 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 687.184912 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.335540 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.335540 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67496491 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67496491 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67496491 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67496491 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67496491 # number of overall hits +system.cpu.icache.overall_hits::total 67496491 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1084 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1084 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1084 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1084 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1084 # number of overall misses +system.cpu.icache.overall_misses::total 1084 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38240500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38240500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38240500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38240500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38240500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38240500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67497575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67497575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67497575 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67497575 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67497575 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67497575 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35150 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35150 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35150 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35150 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35277.214022 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35277.214022 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35277.214022 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35277.214022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35277.214022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35277.214022 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,146 +398,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 281 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 281 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 281 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 281 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 281 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 281 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28673500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28673500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28673500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28673500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28673500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28673500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 278 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 278 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 278 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 278 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 278 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 806 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 806 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 806 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 806 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 806 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 806 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28447000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28447000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28447000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28447000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28447000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28447000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35010.378510 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35010.378510 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35010.378510 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35010.378510 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35010.378510 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35010.378510 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35294.044665 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35294.044665 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35294.044665 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35294.044665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35294.044665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35294.044665 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440349 # number of replacements -system.cpu.dcache.tagsinuse 4094.167847 # Cycle average of tags in use -system.cpu.dcache.total_refs 198867214 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444445 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 447.450672 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 114097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.167847 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 132006402 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 132006402 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66857562 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66857562 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1696 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1696 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 198863964 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 198863964 # 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Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999539 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999539 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 132001023 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 132001023 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66855661 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66855661 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1682 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1682 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1556 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1556 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 198856684 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 198856684 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 198856684 # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40398908535 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40398908535 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 237000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 237000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 44092364035 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 44092364035 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 44092364035 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 44092364035 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 132307849 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 132307849 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2863199 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2863199 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2863199 # number of overall misses +system.cpu.dcache.overall_misses::total 2863199 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3693934500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3693934500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 40457905629 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40457905629 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 239500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 239500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 44151840129 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 44151840129 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 44151840129 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 44151840129 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 132302352 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 132302352 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1717 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1717 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201725380 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201725380 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201725380 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201725380 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1703 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1703 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1556 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1556 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201719883 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201719883 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201719883 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201719883 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002278 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002278 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036878 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.036878 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012231 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012231 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014185 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014185 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014185 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014185 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12252.420824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12252.420824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15781.014745 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15781.014745 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11285.714286 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11285.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15409.281291 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15409.281291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15409.281291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15409.281291 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30249535 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036905 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.036905 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012331 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012331 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014194 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014194 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014194 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014194 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12258.808478 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12258.808478 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15792.333580 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15792.333580 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11404.761905 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11404.761905 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15420.458071 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15420.458071 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15420.458071 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15420.458071 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30335630 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 47000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3035 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2896 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9966.897858 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10475.010359 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 420982 # number of writebacks -system.cpu.dcache.writebacks::total 420982 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104126 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104126 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2312844 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2312844 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 420959 # number of writebacks +system.cpu.dcache.writebacks::total 420959 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104056 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104056 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2314755 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2314755 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 21 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 21 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2416970 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2416970 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2416970 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2416970 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197321 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4299529629 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4299529629 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001491 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001491 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses @@ -546,161 +546,161 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002203 system.cpu.dcache.demand_mshr_miss_rate::total 0.002203 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002203 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002203 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7834.229504 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7834.229504 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 812123285 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24642000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 987604285 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1012246285 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24642000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 987604285 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1012246285 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919414 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027823 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031509 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089738 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089738 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919414 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062251 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063827 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919414 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062251 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063827 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32725.099602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31963.752277 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32055.582252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36620.069667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36620.069667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32725.099602 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35696.110348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35617.392153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32725.099602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35696.110348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35617.392153 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5477 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 6221 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22168 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 22168 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 744 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 27645 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 28389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 744 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 27645 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 28389 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24393000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 175108500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199501500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 838007785 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 838007785 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24393000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1013116285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1037509285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24393000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1013116285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1037509285 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.923077 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027765 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089705 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089705 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.923077 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062209 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063768 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.923077 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062209 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063768 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32786.290323 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31971.608545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32069.040347 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37802.588641 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37802.588641 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32786.290323 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36647.360644 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36546.172285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32786.290323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36647.360644 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36546.172285 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 009981c70..c0dac2931 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.389171 # Number of seconds simulated -sim_ticks 389171398000 # Number of ticks simulated -final_tick 389171398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 389171400000 # Number of ticks simulated +final_tick 389171400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172352 # Simulator instruction rate (inst/s) -host_op_rate 172895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47869738 # Simulator tick rate (ticks/s) -host_mem_usage 232600 # Number of bytes of host memory used -host_seconds 8129.80 # Real time elapsed on the host +host_inst_rate 248197 # Simulator instruction rate (inst/s) +host_op_rate 248980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68935275 # Simulator tick rate (ticks/s) +host_mem_usage 223264 # Number of bytes of host memory used +host_seconds 5645.46 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 78528 # Number of bytes read from this memory @@ -35,7 +35,7 @@ system.physmem.bw_total::cpu.inst 201783 # To system.physmem.bw_total::cpu.data 4314891 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4936519 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 778342797 # number of cpu cycles simulated +system.cpu.numCycles 778342801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 98197174 # Number of BP lookups @@ -52,16 +52,16 @@ system.cpu.fetch.Branches 98197174 # Nu system.cpu.fetch.predictedBranches 65666167 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 330411204 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 21674066 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264316799 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 264316803 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 122 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2684 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 162819499 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 755607 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 778298464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 778298468 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.124294 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.146110 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 447887260 57.55% 57.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 447887264 57.55% 57.55% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 74376407 9.56% 67.10% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 37977630 4.88% 71.98% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 9084449 1.17% 73.15% # Number of instructions fetched each cycle (Total) @@ -73,24 +73,24 @@ system.cpu.fetch.rateDist::8 146598890 18.84% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 778298464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 778298468 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.126162 # Number of branch fetches per cycle system.cpu.fetch.rate 2.118344 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217730423 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214714894 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285147826 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 43019383 # Number of cycles decode is unblocking +system.cpu.decode.IdleCycles 217730424 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214714897 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285147825 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 43019384 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 17685938 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 1642518992 # Number of instructions handled by decode system.cpu.rename.SquashCycles 17685938 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241679768 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 241679770 # Number of cycles rename is idle system.cpu.rename.BlockCycles 36912628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 51960575 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 51960576 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 303022356 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 127037199 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 127037200 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 1631180439 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 31545211 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73402474 # Number of times rename has blocked due to LSQ full +system.cpu.rename.LSQFullEvents 73402475 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 3147906 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 1360824399 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 2755700072 # Number of register rename lookups that rename has made @@ -104,7 +104,7 @@ system.cpu.rename.skidInsts 273063750 # co system.cpu.memDep0.insertedLoads 438707438 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 180249753 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 255184370 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82754828 # Number of conflicting stores. +system.cpu.memDep0.conflictingStores 82754827 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 1516941659 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 2635026 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 1460769058 # Number of instructions issued @@ -112,23 +112,23 @@ system.cpu.iq.iqSquashedInstsIssued 54636 # Nu system.cpu.iq.iqSquashedInstsExamined 113641063 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 136677185 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 391355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 778298464 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 778298468 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.876875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.427909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147064057 18.90% 18.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 186545297 23.97% 42.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210910023 27.10% 69.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147064058 18.90% 18.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 186545303 23.97% 42.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210910021 27.10% 69.96% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 130868567 16.81% 86.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70782480 9.09% 95.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70782478 9.09% 95.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 20278912 2.61% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7762488 1.00% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7762489 1.00% 99.47% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 3994514 0.51% 99.99% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 92126 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 778298464 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 778298468 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 113664 7.00% 7.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 7.00% # attempts to use FU when none available @@ -159,7 +159,7 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 17.26% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 17.26% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.26% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1139490 70.19% 87.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1139492 70.19% 87.45% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 203791 12.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available @@ -199,15 +199,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 1460769058 # Type of FU issued system.cpu.iq.rate 1.876768 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1623524 # FU busy when requested +system.cpu.iq.fu_busy_cnt 1623526 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001111 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3683829696 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 3683829702 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 1624339460 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1444358901 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 17685044 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 9115270 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 8537907 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453371390 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1453371392 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 9021192 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 215484580 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -245,8 +245,8 @@ system.cpu.iew.exec_stores 170572268 # Nu system.cpu.iew.exec_rate 1.869642 # Inst execution rate system.cpu.iew.wb_sent 1453822475 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1452896808 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154316777 # num instructions producing a value -system.cpu.iew.wb_consumers 1205166277 # num instructions consuming a value +system.cpu.iew.wb_producers 1154316776 # num instructions producing a value +system.cpu.iew.wb_consumers 1205166275 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.866654 # insts written-back per cycle system.cpu.iew.wb_fanout 0.957807 # average fanout of values written-back @@ -254,23 +254,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 124161815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 3785239 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 760613137 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 760613141 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.958319 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.503249 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 241688690 31.78% 31.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276879553 36.40% 68.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43195227 5.68% 73.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276879555 36.40% 68.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43195229 5.68% 73.86% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 54904670 7.22% 81.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19686775 2.59% 83.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13341138 1.75% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19686776 2.59% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13341139 1.75% 85.42% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 30448610 4.00% 89.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10352977 1.36% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70115497 9.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10352976 1.36% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70115496 9.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 760613137 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 760613141 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -281,9 +281,9 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70115497 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70115496 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2304117867 # The number of ROB reads +system.cpu.rob.rob_reads 2304117872 # The number of ROB reads system.cpu.rob.rob_writes 3245080355 # The number of ROB writes system.cpu.timesIdled 1467 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 44333 # Total number of cycles that the CPU has spent unscheduled due to idling @@ -415,14 +415,14 @@ system.cpu.dcache.overall_misses::cpu.data 2771932 # system.cpu.dcache.overall_misses::total 2771932 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 11940266500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11940266500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57531206941 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57531206941 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57531211441 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57531211441 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 69000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 69000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 69471473441 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 69471473441 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 69471473441 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 69471473441 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 69471477941 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 69471477941 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 69471477941 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 69471477941 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 201522884 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 201522884 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) @@ -445,14 +445,14 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.007525 system.cpu.dcache.overall_miss_rate::total 0.007525 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13262.541930 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13262.541930 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30738.524956 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30738.524956 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30738.527361 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30738.527361 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 9857.142857 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 9857.142857 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25062.473914 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25062.473914 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25062.473914 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25062.473914 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25062.475537 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25062.475537 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25062.475537 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25062.475537 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 4500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -483,14 +483,14 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 461980 system.cpu.dcache.overall_mshr_misses::total 461980 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 927311500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 927311500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5914389505 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5914389505 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5914391005 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5914391005 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 47000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 47000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6841701005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6841701005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6841701005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6841701005 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6841702505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6841702505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6841702505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6841702505 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001570 # mshr miss rate for WriteReq accesses @@ -503,24 +503,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4637.577767 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4637.577767 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22571.938086 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22571.938086 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22571.943810 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22571.943810 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 6714.285714 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 6714.285714 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14809.517739 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14809.517739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14809.517739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14809.517739 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14809.520986 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14809.520986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14809.520986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14809.520986 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2682 # number of replacements -system.cpu.l2cache.tagsinuse 22381.194058 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22381.194051 # Cycle average of tags in use system.cpu.l2cache.total_refs 541474 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 24308 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.275547 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20744.863113 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 994.979192 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 641.351753 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 20744.863109 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 994.979191 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 641.351751 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.633083 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.030364 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019573 # Average percentage of cache occupancy @@ -552,14 +552,14 @@ system.cpu.l2cache.overall_misses::total 27465 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42694000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 151831500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 194525500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 842839500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 842839500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 842840000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 842840000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 42694000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 994671000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1037365000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 994671500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1037365500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 42694000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 994671000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1037365000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 994671500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1037365500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1363 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 199948 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 201311 # number of ReadReq accesses(hits+misses) @@ -587,14 +587,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.059275 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34795.436023 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34234.836528 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 34356.322854 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.042609 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.042609 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.065541 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.065541 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34795.436023 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.558655 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37770.435099 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.577712 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37770.453304 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34795.436023 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.558655 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37770.435099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.577712 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37770.453304 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 64232919f..516126aba 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.064346 # Number of seconds simulated -sim_ticks 64346039000 # Number of ticks simulated -final_tick 64346039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 64346040000 # Number of ticks simulated +final_tick 64346040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77016 # Simulator instruction rate (inst/s) -host_op_rate 135613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31367260 # Simulator tick rate (ticks/s) -host_mem_usage 410996 # Number of bytes of host memory used -host_seconds 2051.38 # Real time elapsed on the host +host_inst_rate 132449 # Simulator instruction rate (inst/s) +host_op_rate 233222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53944275 # Simulator tick rate (ticks/s) +host_mem_usage 365660 # Number of bytes of host memory used +host_seconds 1192.82 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory @@ -24,7 +24,7 @@ system.physmem.num_reads::total 30652 # Nu system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory system.physmem.num_writes::total 319 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 29424904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 29424903 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s) @@ -32,10 +32,10 @@ system.physmem.bw_write::writebacks 317284 # Wr system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 29424904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30804445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 29424903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30804444 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 128692079 # number of cpu cycles simulated +system.cpu.numCycles 128692081 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups @@ -287,7 +287,7 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 426345169 # The number of ROB reads system.cpu.rob.rob_writes 653150724 # The number of ROB writes system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33722 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 33724 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated @@ -301,12 +301,12 @@ system.cpu.fp_regfile_reads 165 # nu system.cpu.fp_regfile_writes 88 # number of floating regfile writes system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads system.cpu.icache.replacements 92 # number of replacements -system.cpu.icache.tagsinuse 843.498154 # Cycle average of tags in use +system.cpu.icache.tagsinuse 843.498155 # Cycle average of tags in use system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 843.498154 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 843.498155 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits @@ -321,12 +321,12 @@ system.cpu.icache.demand_misses::cpu.inst 1385 # n system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses system.cpu.icache.overall_misses::total 1385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51448500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51448500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51448500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51448500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51448500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51448500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51455500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51455500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51455500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51455500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51455500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51455500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses @@ -339,12 +339,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37146.931408 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37146.931408 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37146.931408 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37146.931408 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37151.985560 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37151.985560 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37151.985560 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37151.985560 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,24 +365,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1078 system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39433000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39433000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39438000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39438000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39438000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39438000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39438000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39438000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36579.777365 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36579.777365 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36584.415584 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36584.415584 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2072148 # number of replacements system.cpu.dcache.tagsinuse 4072.029897 # Cycle average of tags in use @@ -493,14 +493,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4704.008866 system.cpu.dcache.overall_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1466 # number of replacements -system.cpu.l2cache.tagsinuse 19909.538266 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19909.538394 # Cycle average of tags in use system.cpu.l2cache.total_refs 4027133 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 30632 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 131.468171 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19409.012511 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 268.281429 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 232.244325 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 19409.012644 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 268.281425 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 232.244324 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.592316 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.008187 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.007088 # Average percentage of cache occupancy @@ -533,17 +533,17 @@ system.cpu.l2cache.demand_misses::total 30652 # nu system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29584 # number of overall misses system.cpu.l2cache.overall_misses::total 30652 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37875000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37880000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20966500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 58841500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 58846500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 988882500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 988882500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37875000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37880000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1009849000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1047724000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37875000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 1047729000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37880000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1009849000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1047724000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1047729000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1994091 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1995167 # number of ReadReq accesses(hits+misses) @@ -572,17 +572,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014756 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014249 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014756 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35463.483146 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35468.164794 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35657.312925 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35532.306763 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35535.326087 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34181.260603 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34181.423724 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34181.260603 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34181.423724 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,19 +606,19 @@ system.cpu.l2cache.demand_mshr_misses::total 30652 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34493000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53606000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34498500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53612000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34493000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 952804000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34493000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 952804000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34498500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 952810000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34498500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 952810000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses @@ -632,19 +632,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32296.816479 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.102041 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32370.772947 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32301.966292 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.952381 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32374.396135 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index fb71d744c..c461f7be8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.213306 # Number of seconds simulated -sim_ticks 213305827500 # Number of ticks simulated -final_tick 213305827500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.213288 # Number of seconds simulated +sim_ticks 213288042000 # Number of ticks simulated +final_tick 213288042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122434 # Simulator instruction rate (inst/s) -host_op_rate 137922 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51312604 # Simulator tick rate (ticks/s) -host_mem_usage 243816 # Number of bytes of host memory used -host_seconds 4156.99 # Real time elapsed on the host +host_inst_rate 175103 # Simulator instruction rate (inst/s) +host_op_rate 197255 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73380577 # Simulator tick rate (ticks/s) +host_mem_usage 239036 # Number of bytes of host memory used +host_seconds 2906.60 # Real time elapsed on the host sim_insts 508955143 # Number of instructions simulated sim_ops 573341703 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 218880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10018112 # Number of bytes read from this memory -system.physmem.bytes_read::total 10236992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6680832 # Number of bytes written to this memory -system.physmem.bytes_written::total 6680832 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 159953 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104388 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104388 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1026132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46965955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47992088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1026132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1026132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31320438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31320438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31320438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1026132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46965955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 79312526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 218176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10017792 # Number of bytes read from this memory +system.physmem.bytes_read::total 10235968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6680384 # Number of bytes written to this memory +system.physmem.bytes_written::total 6680384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3409 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156528 # Number of read requests responded to by this memory +system.physmem.num_reads::total 159937 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104381 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1022917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46968372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47991289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1022917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1022917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31320950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31320950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31320950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1022917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46968372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 79312238 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +77,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 426611656 # number of cpu cycles simulated +system.cpu.numCycles 426576085 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 180727823 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 143302439 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7746795 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 94842136 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 87606401 # Number of BTB hits +system.cpu.BPredUnit.lookups 180740413 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 143314852 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7747678 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 94843879 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 87610894 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12449624 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 117248 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 121010673 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 797304667 # Number of instructions fetch has processed -system.cpu.fetch.Branches 180727823 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 100056025 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 177314401 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 41698826 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 95806477 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 633 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 114358410 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2503764 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 425037502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.155810 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.022430 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12444215 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 117322 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 121008241 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 797329554 # Number of instructions fetch has processed +system.cpu.fetch.Branches 180740413 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 100055109 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 177305493 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 41694280 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 95788373 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 733 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 114354334 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2502299 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 425002999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.155911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.022478 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 247735901 58.29% 58.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14398989 3.39% 61.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 20690991 4.87% 66.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22948184 5.40% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21028166 4.95% 76.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13190111 3.10% 79.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13289231 3.13% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12171348 2.86% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 59584581 14.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 247710334 58.28% 58.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14399236 3.39% 61.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 20683472 4.87% 66.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22949546 5.40% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21027590 4.95% 76.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13189722 3.10% 79.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13290408 3.13% 83.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12169042 2.86% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59583649 14.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 425037502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.423635 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.868924 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 133844968 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89919956 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165224759 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5218013 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 30829806 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26552808 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 78494 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 873544954 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 311862 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 30829806 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 144308291 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8889002 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 66226963 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159805436 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14978004 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 818752285 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1493 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2838539 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8233022 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 166 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 966651195 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3575004515 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3574999805 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4710 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 425002999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.423700 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.869138 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 133837358 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89905115 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165211809 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5224015 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 30824702 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26552626 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 78407 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 873532911 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312665 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 30824702 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 144300164 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8880120 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 66226908 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159798205 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14972900 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 818719964 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1527 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2831804 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8232958 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 169 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 966624126 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3574819006 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3574814464 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4542 # Number of floating rename lookups system.cpu.rename.CommittedMaps 672200163 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 294451032 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5324262 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5323899 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 70506892 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172716678 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75192368 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27652992 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15476560 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 763674623 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6775753 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 672581286 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1543643 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 194823037 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 494499430 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3054637 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 425037502 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.582405 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.714766 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 294423963 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5324035 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5323684 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 70502461 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172694215 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 75173419 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27528293 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15558221 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 763633649 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6775757 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 672560408 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1538791 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 194774219 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 494406883 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3054641 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 425002999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.582484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.714723 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 161217436 37.93% 37.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 79193919 18.63% 56.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71219740 16.76% 73.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 52703176 12.40% 85.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30630317 7.21% 92.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16016984 3.77% 96.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9411904 2.21% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3391461 0.80% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1252565 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 161186473 37.93% 37.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 79207972 18.64% 56.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71181654 16.75% 73.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 52720158 12.40% 85.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30652473 7.21% 92.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16004592 3.77% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9408207 2.21% 98.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3385200 0.80% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1256270 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 425037502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 425002999 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 468985 4.81% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6682386 68.55% 73.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2596899 26.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 468819 4.82% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6672896 68.60% 73.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2585103 26.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 451788730 67.17% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 385834 0.06% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 451779647 67.17% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 385833 0.06% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 242 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 224 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued @@ -239,84 +239,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 155276883 23.09% 90.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65129594 9.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 155287999 23.09% 90.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65106702 9.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 672581286 # Type of FU issued -system.cpu.iq.rate 1.576566 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9748270 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014494 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1781491468 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 966076983 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 652193699 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 519 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 994 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 672560408 # Type of FU issued +system.cpu.iq.rate 1.576648 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9726818 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014462 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1781388941 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 965987028 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 652168068 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 483 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 954 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 682329295 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 261 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8459367 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 682286983 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 243 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8456716 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 45943639 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 43480 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 808541 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17588407 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 45921176 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 43296 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 808281 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17569458 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19485 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1190 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19481 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1162 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 30829806 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4164559 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 269371 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 776620659 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1214502 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172716678 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75192368 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5287034 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 138183 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8014 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 808541 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4710218 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6437306 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11147524 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 662618807 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 151738432 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9962479 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 30824702 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4157242 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 268994 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 776579176 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1213475 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172694215 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 75173419 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5287043 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 138286 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7916 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 808281 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4709079 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6438741 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11147820 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 662598495 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 151749553 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9961913 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 6170283 # number of nop insts executed -system.cpu.iew.exec_refs 215459970 # number of memory reference insts executed -system.cpu.iew.exec_branches 137327241 # Number of branches executed -system.cpu.iew.exec_stores 63721538 # Number of stores executed -system.cpu.iew.exec_rate 1.553213 # Inst execution rate -system.cpu.iew.wb_sent 657384625 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 652193715 # cumulative count of insts written-back -system.cpu.iew.wb_producers 375712620 # num instructions producing a value -system.cpu.iew.wb_consumers 644546393 # num instructions consuming a value +system.cpu.iew.exec_nop 6169770 # number of nop insts executed +system.cpu.iew.exec_refs 215449893 # number of memory reference insts executed +system.cpu.iew.exec_branches 137324622 # Number of branches executed +system.cpu.iew.exec_stores 63700340 # Number of stores executed +system.cpu.iew.exec_rate 1.553295 # Inst execution rate +system.cpu.iew.wb_sent 657360539 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 652168084 # cumulative count of insts written-back +system.cpu.iew.wb_producers 375706484 # num instructions producing a value +system.cpu.iew.wb_consumers 644527400 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.528776 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.582910 # average fanout of values written-back +system.cpu.iew.wb_rate 1.528844 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.582918 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 201955385 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 201913792 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 3721116 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9921280 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 394207697 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.457824 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.150931 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9922149 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 394178298 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.457933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.151181 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 179674322 45.58% 45.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103038794 26.14% 71.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 36295508 9.21% 80.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18900800 4.79% 85.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16480626 4.18% 89.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8181222 2.08% 91.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6907237 1.75% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3752163 0.95% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20977025 5.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 179646663 45.57% 45.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103047571 26.14% 71.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 36291741 9.21% 80.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18910694 4.80% 85.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16473731 4.18% 89.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8163992 2.07% 91.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6899886 1.75% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3743908 0.95% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 21000112 5.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 394207697 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 394178298 # Number of insts commited each cycle system.cpu.commit.committedInsts 510299027 # Number of instructions committed system.cpu.commit.committedOps 574685587 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -327,69 +327,69 @@ system.cpu.commit.branches 120192224 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 473701629 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20977025 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 21000112 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1149864506 # The number of ROB reads -system.cpu.rob.rob_writes 1584255068 # The number of ROB writes -system.cpu.timesIdled 77013 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1574154 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1149770427 # The number of ROB reads +system.cpu.rob.rob_writes 1584166126 # The number of ROB writes +system.cpu.timesIdled 75828 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1573086 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 508955143 # Number of Instructions Simulated system.cpu.committedOps 573341703 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 508955143 # Number of Instructions Simulated -system.cpu.cpi 0.838211 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.838211 # CPI: Total CPI of All Threads -system.cpu.ipc 1.193017 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.193017 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3092210365 # number of integer regfile reads -system.cpu.int_regfile_writes 760501959 # number of integer regfile writes +system.cpu.cpi 0.838141 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.838141 # CPI: Total CPI of All Threads +system.cpu.ipc 1.193117 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.193117 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3092127855 # number of integer regfile reads +system.cpu.int_regfile_writes 760494999 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1025217817 # number of misc regfile reads +system.cpu.misc_regfile_reads 1025229715 # number of misc regfile reads system.cpu.misc_regfile_writes 4464052 # number of misc regfile writes -system.cpu.icache.replacements 15942 # number of replacements -system.cpu.icache.tagsinuse 1098.022149 # Cycle average of tags in use -system.cpu.icache.total_refs 114338741 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17803 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6422.442341 # Average number of references to valid blocks. +system.cpu.icache.replacements 16005 # number of replacements +system.cpu.icache.tagsinuse 1098.211630 # Cycle average of tags in use +system.cpu.icache.total_refs 114334583 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17866 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6399.562465 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1098.022149 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.536144 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.536144 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114338741 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114338741 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114338741 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114338741 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114338741 # number of overall hits -system.cpu.icache.overall_hits::total 114338741 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19669 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19669 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19669 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19669 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19669 # number of overall misses -system.cpu.icache.overall_misses::total 19669 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 281943000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 281943000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 281943000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 281943000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 281943000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 281943000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114358410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114358410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114358410 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114358410 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114358410 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114358410 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000172 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000172 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000172 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000172 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000172 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000172 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14334.384056 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14334.384056 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14334.384056 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14334.384056 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14334.384056 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14334.384056 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1098.211630 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.536236 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.536236 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114334583 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114334583 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114334583 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114334583 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114334583 # number of overall hits +system.cpu.icache.overall_hits::total 114334583 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19751 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19751 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19751 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19751 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19751 # number of overall misses +system.cpu.icache.overall_misses::total 19751 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 282522500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 282522500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 282522500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 282522500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 282522500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 282522500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114354334 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114354334 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114354334 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114354334 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114354334 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114354334 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000173 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000173 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000173 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000173 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000173 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000173 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14304.212445 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14304.212445 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14304.212445 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14304.212445 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14304.212445 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14304.212445 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,254 +398,258 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1810 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1810 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1810 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1810 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1810 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1810 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17859 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17859 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17859 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17859 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17859 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 184851000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 184851000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 184851000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 184851000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 184851000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 184851000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000156 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000156 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000156 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10350.579540 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10350.579540 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10350.579540 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10350.579540 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10350.579540 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10350.579540 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1832 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1832 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1832 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1832 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1832 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1832 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17919 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17919 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 17919 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 17919 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 17919 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 17919 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 184521500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 184521500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 184521500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 184521500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 184521500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 184521500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000157 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000157 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000157 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000157 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000157 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000157 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10297.533344 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10297.533344 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10297.533344 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10297.533344 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10297.533344 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10297.533344 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1188372 # number of replacements -system.cpu.dcache.tagsinuse 4054.528843 # Cycle average of tags in use -system.cpu.dcache.total_refs 194724251 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1192468 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.295158 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1188505 # number of replacements +system.cpu.dcache.tagsinuse 4054.525384 # Cycle average of tags in use +system.cpu.dcache.total_refs 194736963 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1192601 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.287607 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 4858281000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.528843 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989875 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989875 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137575577 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137575577 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52683646 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52683646 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2232872 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2232872 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 4054.525384 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989874 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989874 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 137587270 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 137587270 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52684677 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52684677 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2232876 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2232876 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 2232025 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 2232025 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 190259223 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 190259223 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 190259223 # number of overall hits -system.cpu.dcache.overall_hits::total 190259223 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1266823 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1266823 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1555660 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1555660 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 190271947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 190271947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 190271947 # number of overall hits +system.cpu.dcache.overall_hits::total 190271947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1267361 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1267361 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1554629 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1554629 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2822483 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2822483 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2822483 # number of overall misses -system.cpu.dcache.overall_misses::total 2822483 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15537538000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15537538000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33101884500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33101884500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2821990 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2821990 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2821990 # number of overall misses +system.cpu.dcache.overall_misses::total 2821990 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15534754000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15534754000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33071578000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33071578000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 516500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 516500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48639422500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48639422500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48639422500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48639422500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 138842400 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 138842400 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 48606332000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48606332000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48606332000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48606332000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 138854631 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 138854631 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232913 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2232913 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232917 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2232917 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232025 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 2232025 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 193081706 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 193081706 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 193081706 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 193081706 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009124 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009124 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028681 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028681 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 193093937 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 193093937 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 193093937 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 193093937 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009127 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009127 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028662 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028662 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014618 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014618 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014618 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12264.963614 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12264.963614 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21278.354203 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21278.354203 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.014615 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014615 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014615 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014615 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12257.560395 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12257.560395 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21272.971236 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21272.971236 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12597.560976 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12597.560976 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17232.848701 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17232.848701 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17232.848701 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17232.848701 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17224.133324 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17224.133324 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17224.133324 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17224.133324 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3299000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3250000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 559 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5901.610018 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5834.829443 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1102743 # number of writebacks -system.cpu.dcache.writebacks::total 1102743 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422432 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 422432 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1207529 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1207529 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1102963 # number of writebacks +system.cpu.dcache.writebacks::total 1102963 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422886 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 422886 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1206451 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1206451 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1629961 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1629961 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1629961 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1629961 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 844391 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34600.099134 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4250 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34276.522033 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34276.522033 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35330.600293 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34370.284375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34390.785090 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35330.600293 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34370.284375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34390.785090 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -654,69 +658,69 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 104388 # number of writebacks -system.cpu.l2cache.writebacks::total 104388 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3420 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53041 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 56461 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103493 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 103493 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 156534 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 159954 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 156534 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 159954 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110207000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1665041000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775248000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3213249000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3213249000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110207000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4878290000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4988497000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110207000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4878290000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 4988497000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192102 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.063116 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065792 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.111111 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.111111 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.293933 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.293933 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131269 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.132164 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131269 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.132164 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32224.269006 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31391.583869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31442.021927 # average ReadReq mshr miss latency +system.cpu.l2cache.writebacks::writebacks 104381 # number of writebacks +system.cpu.l2cache.writebacks::total 104381 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 25 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 25 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 25 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 31 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3409 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53049 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 56458 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103480 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 103480 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3409 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 156529 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 159938 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3409 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 156529 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 159938 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109839000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1666010000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775849000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 248000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 248000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3212774500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3212774500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109839000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4878784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4988623500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109839000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4878784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4988623500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.190852 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.063119 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065777 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.153846 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.293856 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.293856 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.190852 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131250 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.132130 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.190852 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131250 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.132130 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32220.299208 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31405.116025 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31454.337738 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.983922 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.983922 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32224.269006 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31164.411566 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31187.072533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32224.269006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31164.411566 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31187.072533 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.298995 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.298995 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32220.299208 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31168.566208 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31190.983381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32220.299208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31168.566208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31190.983381 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index c2c9b6670..6f010c94a 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,137 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.433562 # Number of seconds simulated -sim_ticks 433562236500 # Number of ticks simulated -final_tick 433562236500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.433409 # Number of seconds simulated +sim_ticks 433408519000 # Number of ticks simulated +final_tick 433408519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69861 # Simulator instruction rate (inst/s) -host_op_rate 129182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36630948 # Simulator tick rate (ticks/s) -host_mem_usage 312956 # Number of bytes of host memory used -host_seconds 11835.95 # Real time elapsed on the host +host_inst_rate 113614 # Simulator instruction rate (inst/s) +host_op_rate 210085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59550946 # Simulator tick rate (ticks/s) +host_mem_usage 266596 # Number of bytes of host memory used +host_seconds 7277.95 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 223808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27615936 # Number of bytes read from this memory -system.physmem.bytes_read::total 27839744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 223808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 223808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20802240 # Number of bytes written to this memory -system.physmem.bytes_written::total 20802240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431499 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434996 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 325035 # Number of write requests responded to by this memory -system.physmem.num_writes::total 325035 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 516207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 63695437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64211644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 516207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 47979824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 47979824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 47979824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 516207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 63695437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 112191469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 223616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27616960 # Number of bytes read from this memory +system.physmem.bytes_read::total 27840576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 223616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 223616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20804096 # Number of bytes written to this memory +system.physmem.bytes_written::total 20804096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431515 # Number of read requests responded to by this memory +system.physmem.num_reads::total 435009 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 325064 # Number of write requests responded to by this memory +system.physmem.num_writes::total 325064 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 515947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 63720390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64236338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 515947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 48001124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 48001124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 48001124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 515947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 63720390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 112237462 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 867124474 # number of cpu cycles simulated +system.cpu.numCycles 866817039 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 221451605 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 221451605 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14391219 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 156554468 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 152744780 # Number of BTB hits +system.cpu.BPredUnit.lookups 221487081 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 221487081 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14390308 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 156608955 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 152775295 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 187033735 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1232378576 # Number of instructions fetch has processed -system.cpu.fetch.Branches 221451605 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 152744780 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 382759458 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 92090467 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 211510860 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30313 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 293412 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 179381043 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4119516 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 859080204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.662810 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.408007 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 187015787 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1232613370 # Number of instructions fetch has processed +system.cpu.fetch.Branches 221487081 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 152775295 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 382812407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 92129156 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 211136743 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29595 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 290923 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 179403606 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4116177 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 858776870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.664123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.408324 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 480734760 55.96% 55.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25482181 2.97% 58.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28110276 3.27% 62.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 29422032 3.42% 65.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18933642 2.20% 67.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25065200 2.92% 70.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31695568 3.69% 74.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30727505 3.58% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 188909040 21.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 480379655 55.94% 55.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25485451 2.97% 58.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28110483 3.27% 62.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29418527 3.43% 65.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18947498 2.21% 67.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25073247 2.92% 70.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31697541 3.69% 74.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30731731 3.58% 78.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 188932737 22.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 859080204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.255386 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.421225 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 243920658 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 168382016 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 324921479 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 44403625 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 77452426 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2234163398 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 77452426 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 277622568 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38425038 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15999 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 333490253 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 132073920 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2182629484 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24122 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19618394 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 98320386 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 151 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282631567 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5519360713 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5519123398 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 237315 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 858776870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.255518 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.421999 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 243893330 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 168016637 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 325049297 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 44326191 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 77491415 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2234477290 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 77491415 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 277619036 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38518487 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15798 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 333479611 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 131652523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2182901177 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23899 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19427368 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 98042792 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 161 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282806171 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5519898710 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5519661560 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 237150 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 668590716 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1589 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1547 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 322287185 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528399687 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210789135 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 202484637 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58642789 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2088380391 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 24636 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1835578469 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 977153 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 553508636 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 915245477 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24083 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 859080204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.136679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.890485 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 668765320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1577 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1532 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 321506074 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528464573 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210836617 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 202710665 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58518610 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2088631495 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25170 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1835731702 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 979947 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 553767245 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 915534947 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24617 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 858776870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.137612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.891337 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233267501 27.15% 27.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 144027396 16.77% 43.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 136780566 15.92% 59.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 136553598 15.90% 75.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 99295309 11.56% 87.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 59689212 6.95% 94.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 35426860 4.12% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12177405 1.42% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1862357 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233191073 27.15% 27.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 144020170 16.77% 43.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 136609479 15.91% 59.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 135995630 15.84% 75.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 99689263 11.61% 87.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59771994 6.96% 94.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35471375 4.13% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12162676 1.42% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1865210 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 859080204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 858776870 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5022876 32.65% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5023267 32.65% 32.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 32.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.65% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.65% # attempts to use FU when none available @@ -160,12 +161,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.65% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7731976 50.26% 82.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2628669 17.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7736612 50.28% 82.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2627522 17.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2701218 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1210723498 65.96% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2697797 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1210853930 65.96% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued @@ -194,84 +195,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 444235410 24.20% 90.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177918343 9.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 444242795 24.20% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177937180 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1835578469 # Type of FU issued -system.cpu.iq.rate 2.116857 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15383521 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008381 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4546556112 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2642088218 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1793025560 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 41704 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 79014 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 9750 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1848241436 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 19336 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170057316 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1835731702 # Type of FU issued +system.cpu.iq.rate 2.117785 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15387401 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4546566873 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2642600298 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1793170888 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 40749 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 78738 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 9468 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1848402423 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 18883 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170058795 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144297531 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 517217 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 266012 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61629484 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144362417 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 511205 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 267668 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61676904 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10771 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 10972 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 77452426 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5095399 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 776506 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2088405027 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2538461 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528399687 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210789669 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5336 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 420481 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 70453 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 266012 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10035135 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4886780 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 14921915 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805657318 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 435939313 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29921151 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 77491415 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5069554 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 791692 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2088656665 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2509040 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528464573 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210837089 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5181 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 437341 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 70182 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 267668 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10030872 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4891333 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 14922205 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1805797916 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 435944125 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29933786 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 608546299 # number of memory reference insts executed -system.cpu.iew.exec_branches 171183701 # Number of branches executed -system.cpu.iew.exec_stores 172606986 # Number of stores executed -system.cpu.iew.exec_rate 2.082351 # Inst execution rate -system.cpu.iew.wb_sent 1800375599 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1793035310 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1362115146 # num instructions producing a value -system.cpu.iew.wb_consumers 1993206857 # num instructions consuming a value +system.cpu.iew.exec_refs 608566280 # number of memory reference insts executed +system.cpu.iew.exec_branches 171216670 # Number of branches executed +system.cpu.iew.exec_stores 172622155 # Number of stores executed +system.cpu.iew.exec_rate 2.083252 # Inst execution rate +system.cpu.iew.wb_sent 1800513420 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1793180356 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1362010404 # num instructions producing a value +system.cpu.iew.wb_consumers 1993207324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.067795 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.683379 # average fanout of values written-back +system.cpu.iew.wb_rate 2.068695 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.683326 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 559448088 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 559701427 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14421135 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 781627778 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.956160 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.445660 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14419517 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 781285455 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.957017 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.446096 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 285492936 36.53% 36.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 197198069 25.23% 61.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62579121 8.01% 69.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 91937051 11.76% 81.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26882169 3.44% 84.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29023123 3.71% 88.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9810981 1.26% 89.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10323566 1.32% 91.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68380762 8.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 285259296 36.51% 36.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 196991997 25.21% 61.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62815706 8.04% 69.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 91733389 11.74% 81.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26919948 3.45% 84.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 29020227 3.71% 88.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9830313 1.26% 89.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10314314 1.32% 91.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68400265 8.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 781627778 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 781285455 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -282,69 +283,69 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68380762 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 68400265 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2801683803 # The number of ROB reads -system.cpu.rob.rob_writes 4254544815 # The number of ROB writes -system.cpu.timesIdled 198794 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8044270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2801575316 # The number of ROB reads +system.cpu.rob.rob_writes 4255093941 # The number of ROB writes +system.cpu.timesIdled 198389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8040169 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.048674 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.048674 # CPI: Total CPI of All Threads -system.cpu.ipc 0.953585 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.953585 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3391389205 # number of integer regfile reads -system.cpu.int_regfile_writes 1872893526 # number of integer regfile writes -system.cpu.fp_regfile_reads 9748 # number of floating regfile reads -system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.misc_regfile_reads 993246616 # number of misc regfile reads -system.cpu.icache.replacements 5750 # number of replacements -system.cpu.icache.tagsinuse 1040.901542 # Cycle average of tags in use -system.cpu.icache.total_refs 179166863 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7354 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24363.185069 # Average number of references to valid blocks. +system.cpu.cpi 1.048302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.048302 # CPI: Total CPI of All Threads +system.cpu.ipc 0.953923 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.953923 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3391505058 # number of integer regfile reads +system.cpu.int_regfile_writes 1872959305 # number of integer regfile writes +system.cpu.fp_regfile_reads 9467 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.misc_regfile_reads 993321385 # number of misc regfile reads +system.cpu.icache.replacements 5754 # number of replacements +system.cpu.icache.tagsinuse 1042.434990 # Cycle average of tags in use +system.cpu.icache.total_refs 179199016 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7367 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24324.557622 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1040.901542 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.508253 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.508253 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 179183149 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179183149 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179183149 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179183149 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179183149 # number of overall hits -system.cpu.icache.overall_hits::total 179183149 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 197894 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 197894 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 197894 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 197894 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 197894 # number of overall misses -system.cpu.icache.overall_misses::total 197894 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1518962500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1518962500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1518962500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1518962500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1518962500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1518962500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179381043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179381043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179381043 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179381043 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179381043 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179381043 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001103 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001103 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001103 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001103 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001103 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7675.636957 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 7675.636957 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7675.636957 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 7675.636957 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7675.636957 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 7675.636957 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1042.434990 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.509001 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.509001 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 179215714 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179215714 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179215714 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179215714 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179215714 # number of overall hits +system.cpu.icache.overall_hits::total 179215714 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 187892 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 187892 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 187892 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 187892 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 187892 # number of overall misses +system.cpu.icache.overall_misses::total 187892 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1425771000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1425771000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1425771000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1425771000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1425771000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1425771000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179403606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179403606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179403606 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179403606 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179403606 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179403606 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001047 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001047 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001047 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001047 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001047 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001047 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7588.247504 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 7588.247504 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7588.247504 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 7588.247504 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7588.247504 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 7588.247504 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1612 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1612 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1612 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1612 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1612 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1612 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 196282 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 196282 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 196282 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 196282 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 196282 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 196282 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 850572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 850572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 850572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 850572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 850572000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 850572000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001094 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001094 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001094 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4333.418245 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4333.418245 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4333.418245 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4333.418245 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4333.418245 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4333.418245 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1602 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1602 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1602 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1602 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1602 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1602 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 186290 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 186290 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 186290 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 186290 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 186290 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 186290 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 789947000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 789947000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 789947000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 789947000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 789947000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 789947000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001038 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001038 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001038 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4240.415481 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4240.415481 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4240.415481 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4240.415481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4240.415481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4240.415481 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529239 # number of replacements -system.cpu.dcache.tagsinuse 4087.824868 # Cycle average of tags in use -system.cpu.dcache.total_refs 410277951 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533335 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 161.951716 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2529214 # number of replacements +system.cpu.dcache.tagsinuse 4087.821968 # Cycle average of tags in use +system.cpu.dcache.total_refs 410284602 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533310 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 161.955940 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1779749000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.824868 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998004 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998004 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 261532697 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 261532697 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148197019 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148197019 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 409729716 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 409729716 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 409729716 # number of overall hits -system.cpu.dcache.overall_hits::total 409729716 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2781068 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2781068 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 963182 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 963182 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3744250 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3744250 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3744250 # number of overall misses -system.cpu.dcache.overall_misses::total 3744250 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36062982500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36062982500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18107985000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18107985000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54170967500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54170967500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54170967500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54170967500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264313765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264313765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4087.821968 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998003 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998003 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 261560100 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 261560100 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148207018 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148207018 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 409767118 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 409767118 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 409767118 # number of overall hits +system.cpu.dcache.overall_hits::total 409767118 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53391126000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53391126000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53391126000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53391126000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264320137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264320137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 413473966 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 413473966 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 413473966 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 413473966 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010522 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010522 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006457 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006457 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009056 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009056 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009056 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009056 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12967.314176 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12967.314176 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18800.169646 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18800.169646 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14467.775255 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14467.775255 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14467.775255 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14467.775255 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 413480338 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 413480338 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 413480338 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 413480338 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010442 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010442 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006390 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006390 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008980 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008980 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008980 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008980 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12918.215227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12918.215227 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18607.522375 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18607.522375 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14378.659492 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14378.659492 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14378.659492 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14378.659492 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,144 +450,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2304434 # number of writebacks -system.cpu.dcache.writebacks::total 2304434 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1018833 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1018833 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3201 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3201 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1022034 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1022034 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1022034 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1022034 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762235 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762235 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 959981 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 959981 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2722216 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2722216 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2722216 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2722216 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12600404545 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12600404545 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15024414005 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 15024414005 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27624818550 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27624818550 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27624818550 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27624818550 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2304349 # number of writebacks +system.cpu.dcache.writebacks::total 2304349 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 997818 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 997818 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3197 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3197 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1001015 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1001015 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1001015 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1001015 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762219 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762219 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 949986 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 949986 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2712205 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2712205 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2712205 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2712205 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12599150566 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12599150566 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14683018004 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14683018004 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27282168570 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27282168570 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27282168570 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27282168570 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006667 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006667 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006436 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006436 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006584 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006584 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006584 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006584 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7150.240771 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7150.240771 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15650.741009 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15650.741009 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10147.915724 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10147.915724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10147.915724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10147.915724 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006369 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006369 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006559 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006559 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006559 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006559 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7149.594100 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7149.594100 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15456.036198 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15456.036198 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10059.036308 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10059.036308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10059.036308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10059.036308 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 408708 # number of replacements -system.cpu.l2cache.tagsinuse 29318.138904 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3612304 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 441048 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 8.190274 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 211122250000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21095.553590 # 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mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991855 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271084 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271084 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.477518 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170352 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171237 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.477518 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170352 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171237 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31932.598741 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31224.426305 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31235.385299 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31011.173043 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31011.173043 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.914186 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.914186 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31932.598741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31121.861638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31128.372894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31932.598741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31121.861638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31128.372894 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 95e13097c..0912a812f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.646278 # Number of seconds simulated -sim_ticks 646278131000 # Number of ticks simulated -final_tick 646278131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 646278143000 # Number of ticks simulated +final_tick 646278143000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212773 # Simulator instruction rate (inst/s) -host_op_rate 212773 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75429257 # Simulator tick rate (ticks/s) -host_mem_usage 229040 # Number of bytes of host memory used -host_seconds 8568.00 # Real time elapsed on the host +host_inst_rate 208687 # Simulator instruction rate (inst/s) +host_op_rate 208687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73980757 # Simulator tick rate (ticks/s) +host_mem_usage 229204 # Number of bytes of host memory used +host_seconds 8735.76 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 191680 # Number of bytes read from this memory @@ -24,16 +24,16 @@ system.physmem.num_reads::total 1479012 # Nu system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 296591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146167855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 146464445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146167852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146464443 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 296591 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 296591 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 6624813 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 6624813 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 6624813 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 296591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146167855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 153089259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146167852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 153089256 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1292556263 # number of cpu cycles simulated +system.cpu.numCycles 1292556287 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 394747270 # Number of BP lookups @@ -78,22 +78,22 @@ system.cpu.BPredUnit.BTBHits 262010178 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 57787448 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 7273 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421195056 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 421195062 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 3322341707 # Number of instructions fetch has processed system.cpu.fetch.Branches 394747270 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 319797626 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 638354680 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162914777 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 98034183 # Number of cycles fetch has spent blocked +system.cpu.fetch.SquashCycles 162914776 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 98034186 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9273 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 9284 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 401438115 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 8412038 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1292428853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 1292428872 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.570619 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.140035 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 654074173 50.61% 50.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 654074192 50.61% 50.61% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 60911661 4.71% 55.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 43750931 3.39% 58.71% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 72637907 5.62% 64.33% # Number of instructions fetched each cycle (Total) @@ -105,65 +105,65 @@ system.cpu.fetch.rateDist::8 240462043 18.61% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1292428853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1292428872 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.305400 # Number of branch fetches per cycle system.cpu.fetch.rate 2.570365 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 452871359 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80658875 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 614115226 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9960098 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134823295 # Number of cycles decode is squashing +system.cpu.decode.IdleCycles 452871377 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80658879 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 614115225 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9960097 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134823294 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 34649231 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 12312 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3231646724 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 3231646719 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 46688 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134823295 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 482927881 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33597057 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 134823294 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 482927898 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33597059 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 26321 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 592678256 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48376043 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3142025534 # Number of instructions processed by rename +system.cpu.rename.RunCycles 592678255 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48376045 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3142025529 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 359 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 11387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42577596 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2088048295 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3654580538 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3537192552 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 42577598 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2088048291 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3654580534 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3537192548 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 117387986 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 703079225 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 703079221 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4247 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 139 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 143016933 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 739120184 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 143016934 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 739120183 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 360450433 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 67842482 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 9359459 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2647443518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 2647443516 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 119 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2196739038 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2196739037 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 17945817 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 824288888 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 711675230 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 824288886 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 711675229 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1292428853 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1292428872 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.699698 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.805222 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 470829214 36.43% 36.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 470829232 36.43% 36.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 219635474 16.99% 53.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 252835920 19.56% 72.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120249082 9.30% 82.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 106312850 8.23% 90.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 252835921 19.56% 72.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120249084 9.30% 82.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 106312849 8.23% 90.52% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 78591497 6.08% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21017975 1.63% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17286985 1.34% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21017973 1.63% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17286986 1.34% 99.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 5669856 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1292428853 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1292428872 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 1140834 3.16% 3.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available @@ -199,7 +199,7 @@ system.cpu.iq.fu_full::MemWrite 10866173 30.12% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1257954368 57.26% 57.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1257954367 57.26% 57.26% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 29223285 1.33% 58.60% # Type of FU issued @@ -232,21 +232,21 @@ system.cpu.iq.FU_type_0::MemRead 590393009 26.88% 86.18% # Ty system.cpu.iq.FU_type_0::MemWrite 303689578 13.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2196739038 # Type of FU issued +system.cpu.iq.FU_type_0::total 2196739037 # Type of FU issued system.cpu.iq.rate 1.699531 # Inst issue rate system.cpu.iq.fu_busy_cnt 36075558 # FU busy when requested system.cpu.iq.fu_busy_rate 0.016422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5585448848 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3387972541 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_reads 5585448865 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3387972537 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 2024033733 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 154479456 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 83833082 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 75371142 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2153745376 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 2153745375 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 79066468 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69378492 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 228050158 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 228050157 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2255425 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 75959 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 149655537 # Number of stores squashed @@ -255,12 +255,12 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 4423 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134823295 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4267154 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 134823294 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4267155 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 460832 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3006059050 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2702145 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 739120184 # Number of dispatched load instructions +system.cpu.iew.iewDispatchedInsts 3006059047 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2702146 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 739120183 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 360450433 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 119 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 451591 # Number of times the IQ has become full, causing a stall @@ -271,41 +271,41 @@ system.cpu.iew.predictedNotTakenIncorrect 31610 # N system.cpu.iew.branchMispredicts 27624768 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 2105923301 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 528979869 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 90815737 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 90815736 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 358615413 # number of nop insts executed +system.cpu.iew.exec_nop 358615412 # number of nop insts executed system.cpu.iew.exec_refs 821261997 # number of memory reference insts executed system.cpu.iew.exec_branches 282350798 # Number of branches executed system.cpu.iew.exec_stores 292282128 # Number of stores executed system.cpu.iew.exec_rate 1.629270 # Inst execution rate system.cpu.iew.wb_sent 2102194150 # cumulative count of insts sent to commit system.cpu.iew.wb_count 2099404875 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1185212781 # num instructions producing a value -system.cpu.iew.wb_consumers 1754721969 # num instructions consuming a value +system.cpu.iew.wb_producers 1185212780 # num instructions producing a value +system.cpu.iew.wb_consumers 1754721967 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.624227 # insts written-back per cycle system.cpu.iew.wb_fanout 0.675442 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 980398498 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 980398495 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 27578641 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1157605558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 1157605578 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.735468 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.494432 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 541345046 46.76% 46.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227581474 19.66% 66.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119272187 10.30% 76.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56742029 4.90% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 51019589 4.41% 86.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24162951 2.09% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18255182 1.58% 89.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 541345066 46.76% 46.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227581476 19.66% 66.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119272186 10.30% 76.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56742028 4.90% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 51019590 4.41% 86.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24162950 2.09% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18255180 1.58% 89.70% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 15605334 1.35% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103621766 8.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103621768 8.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1157605558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1157605578 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,12 +316,12 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 103621766 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103621768 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4037733484 # The number of ROB reads -system.cpu.rob.rob_writes 6113598013 # The number of ROB writes -system.cpu.timesIdled 3574 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 127410 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4037733499 # The number of ROB reads +system.cpu.rob.rob_writes 6113598006 # The number of ROB writes +system.cpu.timesIdled 3575 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 127415 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated @@ -356,12 +356,12 @@ system.cpu.icache.demand_misses::cpu.inst 11347 # n system.cpu.icache.demand_misses::total 11347 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11347 # number of overall misses system.cpu.icache.overall_misses::total 11347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 204563500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 204563500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 204563500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 204563500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 204563500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 204563500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 204562000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 204562000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 204562000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 204562000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 204562000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 204562000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 401438115 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 401438115 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 401438115 # number of demand (read+write) accesses @@ -374,12 +374,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 system.cpu.icache.demand_miss_rate::total 0.000028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.980964 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18027.980964 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.980964 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18027.980964 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.980964 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18027.980964 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.848771 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18027.848771 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18027.848771 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18027.848771 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,14 +446,14 @@ system.cpu.dcache.demand_misses::cpu.data 2543931 # n system.cpu.dcache.demand_misses::total 2543931 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2543931 # number of overall misses system.cpu.dcache.overall_misses::total 2543931 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609230000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76609230000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362374985 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30362374985 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106971604985 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106971604985 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106971604985 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106971604985 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609210500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76609210500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362476485 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30362476485 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106971686985 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106971686985 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106971686985 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106971686985 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 458970336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 458970336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -472,14 +472,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003798 system.cpu.dcache.demand_miss_rate::total 0.003798 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003798 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003798 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.875316 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.875316 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.193322 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.193322 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.727365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42049.727365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.727365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42049.727365 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.865203 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.865203 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.358194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.358194 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42049.759598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42049.759598 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 174500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -506,14 +506,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1532162 system.cpu.dcache.demand_mshr_misses::total 1532162 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1532162 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1532162 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266374000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266374000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176553000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176553000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 53442927000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 53442927000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176578500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176578500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 53442927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 53442927500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses @@ -522,24 +522,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.940516 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.940516 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44360.928401 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44360.928401 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728670 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728670 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728670 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728670 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.923399 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.923399 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44361.284511 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44361.284511 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1480672 # number of replacements -system.cpu.l2cache.tagsinuse 32700.801266 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32700.801233 # Cycle average of tags in use system.cpu.l2cache.total_refs 66336 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1513408 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.043832 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3222.422706 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 46.121130 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29432.257430 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 3222.422931 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 46.121134 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29432.257169 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.098341 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001408 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.898201 # Average percentage of cache occupancy @@ -569,16 +569,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2995 # system.cpu.l2cache.overall_misses::cpu.data 1476017 # number of overall misses system.cpu.l2cache.overall_misses::total 1479012 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48399950500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 48506918500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2813587500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2813587500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48399927000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 48506895000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2813613000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2813613000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 106968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 51213538000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 51320506000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 51213540000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 51320508000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 106968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 51213538000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 51320506000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 51213540000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 51320508000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10134 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1460549 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1470683 # number of ReadReq accesses(hits+misses) @@ -604,16 +604,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.295540 system.cpu.l2cache.overall_miss_rate::cpu.data 0.963356 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.958968 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35715.525876 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34346.594752 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34349.498073 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42085.552099 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42085.552099 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34346.578075 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34349.481432 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42085.933527 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42085.933527 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35715.525876 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34697.119342 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34699.181616 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34697.120697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34699.182968 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35715.525876 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34697.119342 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34699.181616 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34697.120697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34699.182968 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 107500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked @@ -636,16 +636,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2995 system.cpu.l2cache.overall_mshr_misses::cpu.data 1476017 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1479012 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43717529000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43814894000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2612258000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2612258000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43717505000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43814870000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2612284000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2612284000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97365000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46329787000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46427152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46329789000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46427154000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97365000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46329787000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46427152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46329789000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46427154000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295540 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964817 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960206 # mshr miss rate for ReadReq accesses @@ -658,16 +658,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295540 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963356 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.958968 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32509.181970 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.755946 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.906338 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.071858 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.071858 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.738915 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.889342 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.460765 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.460765 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.383061 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.652679 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.384416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.654031 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.383061 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.652679 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.384416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.654031 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 639c0707a..6cef7cd16 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.735463 # Number of seconds simulated -sim_ticks 735462942500 # Number of ticks simulated -final_tick 735462942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.737495 # Number of seconds simulated +sim_ticks 737494828500 # Number of ticks simulated +final_tick 737494828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115593 # Simulator instruction rate (inst/s) -host_op_rate 157422 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61409842 # Simulator tick rate (ticks/s) -host_mem_usage 243732 # Number of bytes of host memory used -host_seconds 11976.30 # Real time elapsed on the host -sim_insts 1384378705 # Number of instructions simulated -sim_ops 1885333457 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 209152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94513152 # Number of bytes read from this memory -system.physmem.bytes_read::total 94722304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 209152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 209152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3268 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476768 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1480036 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 284381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 128508381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 128792762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 284381 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 284381 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5751849 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5751849 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5751849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 284381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 128508381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134544612 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 117861 # Simulator instruction rate (inst/s) +host_op_rate 160511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62787760 # Simulator tick rate (ticks/s) +host_mem_usage 243784 # Number of bytes of host memory used +host_seconds 11745.84 # Real time elapsed on the host +sim_insts 1384378545 # Number of instructions simulated +sim_ops 1885333297 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 209536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94516480 # Number of bytes read from this memory +system.physmem.bytes_read::total 94726016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 209536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 209536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3274 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476820 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1480094 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 284119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 128158838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 128442956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 284119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 284119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5736089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5736089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5736089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 284119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 128158838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134179045 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1470925886 # number of cpu cycles simulated +system.cpu.numCycles 1474989658 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 526944807 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 400998639 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 36103831 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 389912593 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 290078755 # Number of BTB hits +system.cpu.BPredUnit.lookups 524417855 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 399374260 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 35885746 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 373085909 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 286974367 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59371448 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2810327 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 451184041 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2630280787 # Number of instructions fetch has processed -system.cpu.fetch.Branches 526944807 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 349450203 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 714901139 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 225817309 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 101657894 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 20337 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 420935290 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11687737 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1451892883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.541647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.159630 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 58521049 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2814397 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 448543327 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2629766387 # Number of instructions fetch has processed +system.cpu.fetch.Branches 524417855 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 345495416 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 712413372 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 224871613 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 101150257 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2305 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 27764 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 417868916 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11061583 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1445533834 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.549178 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.166303 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 737052267 50.76% 50.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 55648987 3.83% 54.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 113021811 7.78% 62.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71058557 4.89% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 83474414 5.75% 73.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 55105836 3.80% 76.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35245314 2.43% 79.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 35853884 2.47% 81.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 265431813 18.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 733184926 50.72% 50.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 55708468 3.85% 54.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 112020823 7.75% 62.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 70937824 4.91% 67.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 82697525 5.72% 72.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 53946539 3.73% 76.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34097920 2.36% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36269848 2.51% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 266669961 18.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1451892883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.358240 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.788180 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 498609504 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80967892 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 677644967 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10558484 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 184112036 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 82169847 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 15539 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3562988403 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 34450 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 184112036 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 537763866 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 32181538 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 530906 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 647549947 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49754590 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3439334544 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 1445533834 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.355540 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.782905 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 495848393 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80424598 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 675057973 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10827570 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 183375300 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 81502199 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 23236 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3555990026 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 53741 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 183375300 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 535002639 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31838463 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 561864 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 645033334 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49722234 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3433849661 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 240 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4507727 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40704108 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1637 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3357877059 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16273276362 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15612337004 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 660939358 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153074 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1364723985 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50374 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 45755 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138448530 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1057693537 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 579697033 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 32301976 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40224751 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3204253855 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55204 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2728539607 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 26296633 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1318520975 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3049786617 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 32197 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1451892883 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.879298 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.913242 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 4442600 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40377333 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1619 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3343633011 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16242490520 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15601606149 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 640884371 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993152818 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1350480193 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 55128 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 50419 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 136573484 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1056851261 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 578467186 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 33770671 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40675012 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3200649154 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 58384 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2726502260 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 25388775 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1314914344 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3030342592 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 35409 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1445533834 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.886156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.918040 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 529391229 36.46% 36.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201881649 13.90% 50.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217086646 14.95% 65.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 180698536 12.45% 77.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 155303824 10.70% 88.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 101627119 7.00% 95.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 47687061 3.28% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10818751 0.75% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7398068 0.51% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 525278081 36.34% 36.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201262430 13.92% 50.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 215918123 14.94% 65.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 180162301 12.46% 77.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 154926049 10.72% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 101550700 7.03% 95.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47554041 3.29% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10922133 0.76% 99.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7959976 0.55% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1451892883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1445533834 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1769730 1.85% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23897 0.03% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 57017691 59.74% 61.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36624161 38.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1492509 1.56% 1.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23896 0.02% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56884483 59.48% 61.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37239793 38.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1267852875 46.47% 46.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11249841 0.41% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876502 0.25% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5509242 0.20% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 10 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23422716 0.86% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 900241539 32.99% 81.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 512011592 18.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1265251443 46.41% 46.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11240550 0.41% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876520 0.25% 47.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5507594 0.20% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 50 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23397304 0.86% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 900321510 33.02% 81.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 512531999 18.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2728539607 # Type of FU issued -system.cpu.iq.rate 1.854981 # Inst issue rate -system.cpu.iq.fu_busy_cnt 95435479 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.034977 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6896111029 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4417455828 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2500265065 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 134593180 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 105438972 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 60061785 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2754719800 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 69255286 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 70868561 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2726502260 # Type of FU issued +system.cpu.iq.rate 1.848489 # Inst issue rate +system.cpu.iq.fu_busy_cnt 95640681 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035078 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6886689526 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4415187143 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2498660773 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 132878284 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 100500200 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59720745 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2753616267 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 68526674 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 71560936 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 426304733 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 264948 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1116073 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 302700113 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 425462489 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 295662 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1252623 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 301470298 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 184112036 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17217570 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2222077 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3204383976 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3801477 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1057693537 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 579697033 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 44065 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2220604 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1116073 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 37419443 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9018722 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 46438165 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2627591050 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 846492275 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 100948557 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 183375300 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17460814 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1976242 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3200787719 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6982578 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1056851261 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 578467186 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 47271 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1974574 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 647 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1252623 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 36804150 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9241017 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 46045167 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2625801566 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 846122172 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 100700694 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 74917 # number of nop insts executed -system.cpu.iew.exec_refs 1329282286 # number of memory reference insts executed -system.cpu.iew.exec_branches 361424797 # Number of branches executed -system.cpu.iew.exec_stores 482790011 # Number of stores executed -system.cpu.iew.exec_rate 1.786352 # Inst execution rate -system.cpu.iew.wb_sent 2588656133 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2560326850 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1477151291 # num instructions producing a value -system.cpu.iew.wb_consumers 2761912490 # num instructions consuming a value +system.cpu.iew.exec_nop 80181 # number of nop insts executed +system.cpu.iew.exec_refs 1330053445 # number of memory reference insts executed +system.cpu.iew.exec_branches 359055744 # Number of branches executed +system.cpu.iew.exec_stores 483931273 # Number of stores executed +system.cpu.iew.exec_rate 1.780217 # Inst execution rate +system.cpu.iew.wb_sent 2586917302 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2558381518 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1475385900 # num instructions producing a value +system.cpu.iew.wb_consumers 2766219416 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.740623 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534829 # average fanout of values written-back +system.cpu.iew.wb_rate 1.734508 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533358 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1319039983 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23007 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 41626374 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1267780849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.487122 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.205349 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 1315443833 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22975 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 41404056 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1262158536 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.493746 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.206193 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 586908423 46.29% 46.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 318188211 25.10% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 101915381 8.04% 79.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79184752 6.25% 85.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 52930899 4.18% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24002778 1.89% 91.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17056118 1.35% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9057246 0.71% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78537041 6.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 581725846 46.09% 46.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 316852279 25.10% 71.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 102044776 8.08% 79.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79824424 6.32% 85.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 53115957 4.21% 89.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24396464 1.93% 91.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17091653 1.35% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8923952 0.71% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78183185 6.19% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1267780849 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384389721 # Number of instructions committed -system.cpu.commit.committedOps 1885344473 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1262158536 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384389561 # Number of instructions committed +system.cpu.commit.committedOps 1885344313 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385724 # Number of memory references committed -system.cpu.commit.loads 631388804 # Number of loads committed +system.cpu.commit.refs 908385660 # Number of memory references committed +system.cpu.commit.loads 631388772 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350167 # Number of branches committed +system.cpu.commit.branches 291350135 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705359 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705231 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 78537041 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 78183185 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4393609919 # The number of ROB reads -system.cpu.rob.rob_writes 6592898385 # The number of ROB writes -system.cpu.timesIdled 1319009 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19033003 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384378705 # Number of Instructions Simulated -system.cpu.committedOps 1885333457 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384378705 # Number of Instructions Simulated -system.cpu.cpi 1.062517 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.062517 # CPI: Total CPI of All Threads -system.cpu.ipc 0.941161 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.941161 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12954963873 # number of integer regfile reads -system.cpu.int_regfile_writes 2433899431 # number of integer regfile writes -system.cpu.fp_regfile_reads 71453474 # number of floating regfile reads -system.cpu.fp_regfile_writes 51512029 # number of floating regfile writes -system.cpu.misc_regfile_reads 4110345957 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776148 # number of misc regfile writes -system.cpu.icache.replacements 27727 # number of replacements -system.cpu.icache.tagsinuse 1657.357291 # Cycle average of tags in use -system.cpu.icache.total_refs 420895339 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 29422 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14305.463225 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4384745152 # The number of ROB reads +system.cpu.rob.rob_writes 6584968170 # The number of ROB writes +system.cpu.timesIdled 1343543 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29455824 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384378545 # Number of Instructions Simulated +system.cpu.committedOps 1885333297 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384378545 # Number of Instructions Simulated +system.cpu.cpi 1.065453 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.065453 # CPI: Total CPI of All Threads +system.cpu.ipc 0.938568 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.938568 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12950426831 # number of integer regfile reads +system.cpu.int_regfile_writes 2427369394 # number of integer regfile writes +system.cpu.fp_regfile_reads 71525918 # number of floating regfile reads +system.cpu.fp_regfile_writes 50683175 # number of floating regfile writes +system.cpu.misc_regfile_reads 4109052133 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776084 # number of misc regfile writes +system.cpu.icache.replacements 27555 # number of replacements +system.cpu.icache.tagsinuse 1659.051734 # Cycle average of tags in use +system.cpu.icache.total_refs 417829104 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 29252 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14283.779024 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1657.357291 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.809256 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.809256 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 420900012 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420900012 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420900012 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420900012 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420900012 # number of overall hits -system.cpu.icache.overall_hits::total 420900012 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35278 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35278 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35278 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35278 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35278 # number of overall misses -system.cpu.icache.overall_misses::total 35278 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 347510000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 347510000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 347510000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 347510000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 347510000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 347510000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420935290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420935290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 420935290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 420935290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 420935290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 420935290 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1659.051734 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.810084 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.810084 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 417833790 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 417833790 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 417833790 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 417833790 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 417833790 # number of overall hits +system.cpu.icache.overall_hits::total 417833790 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35126 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35126 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35126 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35126 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35126 # number of overall misses +system.cpu.icache.overall_misses::total 35126 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 348458500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 348458500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 348458500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 348458500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 348458500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 348458500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 417868916 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 417868916 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 417868916 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 417868916 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 417868916 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 417868916 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9850.615114 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 9850.615114 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9850.615114 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 9850.615114 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9850.615114 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 9850.615114 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9920.244264 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 9920.244264 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 9920.244264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 9920.244264 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,110 +399,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 933 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 933 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 933 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 933 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 933 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 933 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34345 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 34345 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 34345 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 34345 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 34345 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 34345 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 217293500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 217293500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 217293500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 217293500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 217293500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 217293500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 940 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 940 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 940 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 940 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 940 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 940 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34186 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 34186 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 34186 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 34186 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 34186 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 34186 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 218551000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 218551000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 218551000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 218551000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 218551000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 218551000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6326.787014 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6326.787014 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6326.787014 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6326.787014 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6326.787014 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6326.787014 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6392.997133 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6392.997133 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532802 # number of replacements -system.cpu.dcache.tagsinuse 4094.906416 # Cycle average of tags in use -system.cpu.dcache.total_refs 1033702432 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536898 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 672.590134 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1533020 # number of replacements +system.cpu.dcache.tagsinuse 4094.909429 # Cycle average of tags in use +system.cpu.dcache.total_refs 1033013851 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537116 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 672.046775 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 306710000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.906416 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 757546654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 757546654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276115180 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276115180 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11970 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11970 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11608 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11608 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1033661834 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1033661834 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1033661834 # number of overall hits -system.cpu.dcache.overall_hits::total 1033661834 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2867388 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2867388 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 820498 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 820498 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3687886 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3687886 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3687886 # number of overall misses -system.cpu.dcache.overall_misses::total 3687886 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 99520769500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 99520769500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963338500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33963338500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 216500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133484108000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133484108000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133484108000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133484108000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 760414042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 760414042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4094.909429 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999734 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999734 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 756858216 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 756858216 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276115103 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276115103 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11921 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11921 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11576 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11576 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1032973319 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1032973319 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1032973319 # number of overall hits +system.cpu.dcache.overall_hits::total 1032973319 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2483728 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2483728 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 820575 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 820575 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3304303 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3304303 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3304303 # number of overall misses +system.cpu.dcache.overall_misses::total 3304303 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 90046240500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 90046240500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963890000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33963890000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 124010130500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 124010130500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 124010130500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 124010130500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 759341944 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 759341944 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11976 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11976 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11608 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11608 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1037349720 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1037349720 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1037349720 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1037349720 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003771 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003771 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11576 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11576 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1036277622 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1036277622 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1036277622 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1036277622 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003271 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003271 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002963 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002963 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000501 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000501 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003555 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003555 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003555 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003555 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34707.814045 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34707.814045 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41393.566468 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41393.566468 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36083.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 36083.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36195.291286 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36195.291286 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36195.291286 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36195.291286 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000335 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000335 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003189 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003189 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003189 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003189 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36254.469290 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36254.469290 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41390.354325 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41390.354325 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37529.890721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37529.890721 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,142 +511,142 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108638 # number of writebacks -system.cpu.dcache.writebacks::total 108638 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1403027 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1403027 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743038 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 743038 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2146065 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2146065 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2146065 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2146065 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464361 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464361 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77460 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77460 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541821 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541821 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541821 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541821 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50337065001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50337065001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2525124500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2525124500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52862189501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52862189501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52862189501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52862189501 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001926 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001926 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 108316 # number of writebacks +system.cpu.dcache.writebacks::total 108316 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1019154 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1019154 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743098 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 743098 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1762252 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1762252 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1762252 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1762252 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464574 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464574 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77477 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 77477 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1542051 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1542051 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1542051 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1542051 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50338229502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50338229502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2525857500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2525857500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52864087002 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52864087002 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52864087002 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52864087002 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001929 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001929 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001486 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001486 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001486 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001486 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34374.764830 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34374.764830 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32599.076943 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32599.076943 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34285.555522 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34285.555522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34285.555522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34285.555522 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34370.560656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34370.560656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32601.384927 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32601.384927 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480261 # number of replacements -system.cpu.l2cache.tagsinuse 32698.232813 # Cycle average of tags in use -system.cpu.l2cache.total_refs 88469 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.058472 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480259 # number of replacements +system.cpu.l2cache.tagsinuse 32698.440647 # Cycle average of tags in use +system.cpu.l2cache.total_refs 88180 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513003 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.058281 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3127.449947 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 61.048059 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29509.734807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.095442 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001863 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.900566 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997871 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26144 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 53654 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 79798 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108638 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108638 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 3112.320696 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 61.394609 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29524.725342 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.094980 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001874 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.901023 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997877 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 25967 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53813 # 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average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3274 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1476820 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1480094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3274 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1476820 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1480094 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105728000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44228314000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44334042000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 152892000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 152892000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049197000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049197000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105728000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46277511000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46383239000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105728000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46277511000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46383239000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963243 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.946572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999392 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999392 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.944921 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.944921 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32293.219304 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.167012 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.348237 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.547661 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.547661 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32274.479804 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31336.011141 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.083330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32274.479804 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31336.011141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.083330 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.381199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.381199 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 52b1e9eb7..361b9fcbc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.047910 # Number of seconds simulated -sim_ticks 47910283500 # Number of ticks simulated -final_tick 47910283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.047911 # Number of seconds simulated +sim_ticks 47910588500 # Number of ticks simulated +final_tick 47910588500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137428 # Simulator instruction rate (inst/s) -host_op_rate 137428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74532010 # Simulator tick rate (ticks/s) -host_mem_usage 227148 # Number of bytes of host memory used -host_seconds 642.82 # Real time elapsed on the host +host_inst_rate 102205 # Simulator instruction rate (inst/s) +host_op_rate 102205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55429613 # Simulator tick rate (ticks/s) +host_mem_usage 227308 # Number of bytes of host memory used +host_seconds 864.35 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 515328 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 160515 # Nu system.physmem.num_reads::total 168567 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10756104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 214420773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 225176877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10756104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10756104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 154922899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 154922899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 154922899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10756104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 214420773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380099775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10756036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 214419408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 225175443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10756036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10756036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 154921913 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 154921913 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 154921913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10756036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 214419408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380097356 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 95820568 # number of cpu cycles simulated +system.cpu.numCycles 95821178 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 18829757 # Number of BP lookups @@ -97,12 +97,12 @@ system.cpu.execution_unit.executions 44775821 # Nu system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78582823 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78582835 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 467369 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25529650 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70290918 # Number of cycles cpu stages are processed. -system.cpu.activity 73.356816 # Percentage of cycles cpu is active +system.cpu.timesIdled 467389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25530263 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70290915 # Number of cycles cpu stages are processed. +system.cpu.activity 73.356346 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,34 +114,34 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.084671 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.084678 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.084671 # CPI: Total CPI of All Threads -system.cpu.ipc 0.921939 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.084678 # CPI: Total CPI of All Threads +system.cpu.ipc 0.921933 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.921939 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 42393437 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53427131 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 55.757477 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 53162471 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42658097 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 44.518727 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 52693934 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43126634 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.007700 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 73699390 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22121178 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.086043 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 49718373 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46102195 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 48.113047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.921933 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 42394050 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53427128 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 55.757119 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 53163082 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42658096 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 44.518442 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 52694545 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43126633 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.007413 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 73699998 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22121180 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.085899 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 49718969 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46102209 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 48.112755 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 85335 # number of replacements -system.cpu.icache.tagsinuse 1885.674809 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1885.674638 # Cycle average of tags in use system.cpu.icache.total_refs 12357256 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 87381 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 141.418111 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1885.674809 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1885.674638 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.920740 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.920740 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 12357256 # number of ReadReq hits @@ -156,12 +156,12 @@ system.cpu.icache.demand_misses::cpu.inst 118639 # n system.cpu.icache.demand_misses::total 118639 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 118639 # number of overall misses system.cpu.icache.overall_misses::total 118639 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081821000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2081821000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2081821000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2081821000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2081821000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2081821000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081863500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2081863500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2081863500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2081863500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2081863500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2081863500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 12475895 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 12475895 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 12475895 # number of demand (read+write) accesses @@ -174,12 +174,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.009509 system.cpu.icache.demand_miss_rate::total 0.009509 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009509 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009509 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.526530 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17547.526530 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17547.526530 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17547.526530 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.884760 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17547.884760 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17547.884760 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17547.884760 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 1176500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,32 +200,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 87381 system.cpu.icache.demand_mshr_misses::total 87381 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 87381 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 87381 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364843500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1364843500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364843500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1364843500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364843500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1364843500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364888000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1364888000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364888000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1364888000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364888000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1364888000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.007004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.007004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.453886 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.453886 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.963150 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.963150 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.238674 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4073.238819 # Cycle average of tags in use system.cpu.dcache.total_refs 34125947 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 166.999990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 499859000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.238674 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4073.238819 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994443 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994443 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20180530 # number of ReadReq hits @@ -244,14 +244,14 @@ system.cpu.dcache.demand_misses::cpu.data 764068 # n system.cpu.dcache.demand_misses::total 764068 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 764068 # number of overall misses system.cpu.dcache.overall_misses::total 764068 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4228645500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 42086848500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 42086848500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46315494000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46315494000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46315494000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46315494000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4228645000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 42089863000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 42089863000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46318508000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46318508000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46318508000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46318508000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -268,20 +268,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.021899 system.cpu.dcache.demand_miss_rate::total 0.021899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.021899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.021899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.891872 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.891872 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63008.037158 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63008.037158 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60616.979117 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60616.979117 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.886669 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.886669 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63012.550153 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63012.550153 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60620.923792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60620.923792 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6945858000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6946123500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 124169 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 55938.744775 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 55940.882990 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 165805 # number of writebacks @@ -304,12 +304,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 204347 system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1936845000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 1936845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7868977000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7868977000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9805822000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9805822000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9805822000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9805822000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7870166500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7870166500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9807011500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9807011500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9807011500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9807011500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -320,24 +320,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31873.302944 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31873.302944 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54805.523053 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54805.523053 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47986.131433 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 47986.131433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47986.131433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 47986.131433 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54813.807633 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54813.807633 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 136141 # number of replacements -system.cpu.l2cache.tagsinuse 28773.047265 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 28773.050902 # Cycle average of tags in use system.cpu.l2cache.total_refs 146499 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 167004 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.877219 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25287.688081 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1723.908362 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1761.450821 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 25287.699561 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1723.905670 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1761.445671 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.771719 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052609 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.053755 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.878084 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 79329 # number of ReadReq hits @@ -367,14 +367,14 @@ system.cpu.l2cache.overall_misses::total 168567 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 427362500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1541002500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1968365000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6838998500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6838998500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6840080000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6840080000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 427362500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8380001000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8807363500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8381082500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8808445000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 427362500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8380001000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8807363500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8381082500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8808445000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 87381 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 147958 # number of ReadReq accesses(hits+misses) @@ -402,14 +402,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.577822 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53075.322901 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52295.873350 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52463.152003 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52186.973475 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52186.973475 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52195.226177 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52195.226177 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52206.965081 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52248.444239 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52213.702769 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52254.860085 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52206.965081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52248.444239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52213.702769 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52254.860085 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,14 +434,14 @@ system.cpu.l2cache.overall_mshr_misses::total 168567 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329154000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1181438500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1510592500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5254733000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5254733000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5255819000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5255819000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329154000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6436171500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6765325500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6437257500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6766411500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329154000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6436171500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6765325500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6437257500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6766411500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486439 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253579 # mshr miss rate for ReadReq accesses @@ -456,14 +456,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.577822 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40878.539493 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40093.613194 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40262.067219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40097.773335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40097.773335 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40106.060375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40106.060375 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 7baadddcc..e1fb122e9 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.021620 # Number of seconds simulated -sim_ticks 21619648000 # Number of ticks simulated -final_tick 21619648000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21619627000 # Number of ticks simulated +final_tick 21619627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236725 # Simulator instruction rate (inst/s) -host_op_rate 236725 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64301983 # Simulator tick rate (ticks/s) -host_mem_usage 228176 # Number of bytes of host memory used -host_seconds 336.22 # Real time elapsed on the host +host_inst_rate 209503 # Simulator instruction rate (inst/s) +host_op_rate 209503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56907639 # Simulator tick rate (ticks/s) +host_mem_usage 228332 # Number of bytes of host memory used +host_seconds 379.91 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 559360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10295744 # Number of bytes read from this memory -system.physmem.bytes_read::total 10855104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 559360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 559360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7426560 # Number of bytes written to this memory -system.physmem.bytes_written::total 7426560 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160871 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169611 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116040 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116040 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25872762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476221630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 502094391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25872762 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25872762 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 343509756 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 343509756 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 343509756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25872762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476221630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845604147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 559680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10295552 # Number of bytes read from this memory +system.physmem.bytes_read::total 10855232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 559680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 559680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7426432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7426432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160868 # Number of read requests responded to by this memory +system.physmem.num_reads::total 169613 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116038 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116038 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25887588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 476213211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 502100799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25887588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25887588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 343504169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 343504169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 343504169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25887588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 476213211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845604968 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22479620 # DTB read hits -system.cpu.dtb.read_misses 218266 # DTB read misses -system.cpu.dtb.read_acv 51 # DTB read access violations -system.cpu.dtb.read_accesses 22697886 # DTB read accesses -system.cpu.dtb.write_hits 15794697 # DTB write hits -system.cpu.dtb.write_misses 42457 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 15837154 # DTB write accesses -system.cpu.dtb.data_hits 38274317 # DTB hits -system.cpu.dtb.data_misses 260723 # DTB misses +system.cpu.dtb.read_hits 22478221 # DTB read hits +system.cpu.dtb.read_misses 218727 # DTB read misses +system.cpu.dtb.read_acv 49 # DTB read access violations +system.cpu.dtb.read_accesses 22696948 # DTB read accesses +system.cpu.dtb.write_hits 15797623 # DTB write hits +system.cpu.dtb.write_misses 42281 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 15839904 # DTB write accesses +system.cpu.dtb.data_hits 38275844 # DTB hits +system.cpu.dtb.data_misses 261008 # DTB misses system.cpu.dtb.data_acv 51 # DTB access violations -system.cpu.dtb.data_accesses 38535040 # DTB accesses -system.cpu.itb.fetch_hits 14126097 # ITB hits -system.cpu.itb.fetch_misses 39352 # ITB misses +system.cpu.dtb.data_accesses 38536852 # DTB accesses +system.cpu.itb.fetch_hits 14126153 # ITB hits +system.cpu.itb.fetch_misses 38209 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14165449 # ITB accesses +system.cpu.itb.fetch_accesses 14164362 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,146 +67,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 43239299 # number of cpu cycles simulated +system.cpu.numCycles 43239256 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16709943 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10781072 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 476192 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12038225 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7471491 # Number of BTB hits +system.cpu.BPredUnit.lookups 16713940 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10785641 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 474517 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12148042 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7471828 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1995310 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44665 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15444845 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106679218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16709943 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9466801 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19799027 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2146422 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5702055 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 320776 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14126097 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 222277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42829816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.490770 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.154588 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1996046 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44341 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15442173 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106653150 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16713940 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9467874 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19795691 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2142333 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5738431 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8227 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 318072 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14126153 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 221095 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 42854841 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.488707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.154001 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23030789 53.77% 53.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1545838 3.61% 57.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1407824 3.29% 60.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1518177 3.54% 64.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4200095 9.81% 74.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1866083 4.36% 78.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 683567 1.60% 79.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1088540 2.54% 82.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7488903 17.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23059150 53.81% 53.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1544639 3.60% 57.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1408806 3.29% 60.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1522467 3.55% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4195710 9.79% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1864977 4.35% 78.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 685640 1.60% 79.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1085683 2.53% 82.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7487769 17.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42829816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.386453 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.467182 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16586159 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5216387 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18831807 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 747368 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1448095 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3802176 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109343 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104798684 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 306113 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1448095 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17060162 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2943499 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 82970 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19071081 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2224009 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103374463 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 294 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 47714 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2072135 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62309566 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124647358 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124190382 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 456976 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 42854841 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.386546 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.466582 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16604436 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5227614 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18845700 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 731163 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1445928 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3801623 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109086 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104782719 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304838 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1445928 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17078558 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2955442 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 82947 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19068517 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2223449 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103359605 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 254 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 47854 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2072460 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62291613 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124619411 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124164571 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 454840 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9762685 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5585 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5583 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4545963 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23367723 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16390642 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1133008 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 393146 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91432081 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5446 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89033358 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 121532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11257440 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4905922 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 863 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42829816 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.078770 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.113525 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9744732 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5573 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5571 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4558890 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23363714 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16388828 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1131841 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 391237 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91420984 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5434 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89018152 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 120887 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11240273 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4901766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 851 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 42854841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.077202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.113927 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 14329925 33.46% 33.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7119620 16.62% 50.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5526453 12.90% 62.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4793299 11.19% 74.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4689695 10.95% 85.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2671983 6.24% 91.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1950910 4.56% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1326668 3.10% 99.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 421263 0.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 14370838 33.53% 33.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7100087 16.57% 50.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5540527 12.93% 63.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4772141 11.14% 74.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4704722 10.98% 85.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2673915 6.24% 91.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1941470 4.53% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1325823 3.09% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 425318 0.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42829816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42854841 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 128939 6.83% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 795203 42.12% 48.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 964007 51.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 128315 6.76% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 799448 42.10% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 971123 51.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49729867 55.86% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43817 0.05% 55.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49717774 55.85% 55.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43792 0.05% 55.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121200 0.14% 56.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 120893 0.14% 56.04% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 122187 0.14% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121944 0.14% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38928 0.04% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.22% # Type of FU issued @@ -228,84 +228,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.22% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22972171 25.80% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16005027 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22969813 25.80% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16004865 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89033358 # Type of FU issued -system.cpu.iq.rate 2.059084 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1888149 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222297193 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102291434 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86992301 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 609020 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 419648 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 296730 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90616918 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 304589 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1450786 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89018152 # Type of FU issued +system.cpu.iq.rate 2.058735 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1898886 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021331 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222303440 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102266391 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86984314 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 607478 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 416601 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 296142 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90613228 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 303810 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1449481 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3091085 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5211 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17173 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1777265 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3087076 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5237 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1775451 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2461 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 40 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2459 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1448095 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1762662 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 92194 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100976081 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 242299 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23367723 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16390642 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 53221 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 430 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17173 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250537 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 173902 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 424439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88065648 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22701440 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 967710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1445928 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1740049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88499 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100965460 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 244137 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23363714 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16388828 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5434 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 53254 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 431 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17226 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 250564 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 172705 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423269 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88055069 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22700407 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 963083 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9538554 # number of nop insts executed -system.cpu.iew.exec_refs 38538948 # number of memory reference insts executed -system.cpu.iew.exec_branches 15139399 # Number of branches executed -system.cpu.iew.exec_stores 15837508 # Number of stores executed -system.cpu.iew.exec_rate 2.036704 # Inst execution rate -system.cpu.iew.wb_sent 87702246 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87289031 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33442850 # num instructions producing a value -system.cpu.iew.wb_consumers 43872911 # num instructions consuming a value +system.cpu.iew.exec_nop 9539042 # number of nop insts executed +system.cpu.iew.exec_refs 38540674 # number of memory reference insts executed +system.cpu.iew.exec_branches 15139519 # Number of branches executed +system.cpu.iew.exec_stores 15840267 # Number of stores executed +system.cpu.iew.exec_rate 2.036461 # Inst execution rate +system.cpu.iew.wb_sent 87694134 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87280456 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33430607 # num instructions producing a value +system.cpu.iew.wb_consumers 43860363 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.018743 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762266 # average fanout of values written-back +system.cpu.iew.wb_rate 2.018547 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762205 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9533571 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9526459 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369490 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 41381721 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.134775 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.804212 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 368198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 41408913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.133373 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.803824 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18296264 44.21% 44.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7146737 17.27% 61.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3523583 8.51% 70.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2099457 5.07% 75.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2039541 4.93% 80.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1177840 2.85% 82.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1135730 2.74% 85.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 713898 1.73% 87.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5248671 12.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18342699 44.30% 44.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7125223 17.21% 61.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3513214 8.48% 69.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2087650 5.04% 75.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2070192 5.00% 80.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1179714 2.85% 82.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1132729 2.74% 85.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 709577 1.71% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5247915 12.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 41381721 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 41408913 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5248671 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5247915 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132689951 # The number of ROB reads -system.cpu.rob.rob_writes 197200056 # The number of ROB writes -system.cpu.timesIdled 24548 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 409483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132710787 # The number of ROB reads +system.cpu.rob.rob_writes 197183581 # The number of ROB writes +system.cpu.timesIdled 23387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 384415 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.543264 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.543264 # CPI: Total CPI of All Threads -system.cpu.ipc 1.840727 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.840727 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116607964 # number of integer regfile reads -system.cpu.int_regfile_writes 57862089 # number of integer regfile writes -system.cpu.fp_regfile_reads 251339 # number of floating regfile reads -system.cpu.fp_regfile_writes 241385 # number of floating regfile writes -system.cpu.misc_regfile_reads 38087 # number of misc regfile reads +system.cpu.cpi 0.543263 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.543263 # CPI: Total CPI of All Threads +system.cpu.ipc 1.840729 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.840729 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116590843 # number of integer regfile reads +system.cpu.int_regfile_writes 57851456 # number of integer regfile writes +system.cpu.fp_regfile_reads 250950 # number of floating regfile reads +system.cpu.fp_regfile_writes 240941 # number of floating regfile writes +system.cpu.misc_regfile_reads 38077 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 92930 # number of replacements -system.cpu.icache.tagsinuse 1930.212243 # Cycle average of tags in use -system.cpu.icache.total_refs 14026666 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 94978 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.683316 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18067713000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1930.212243 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942486 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942486 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14026666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14026666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14026666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14026666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14026666 # number of overall hits -system.cpu.icache.overall_hits::total 14026666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 99431 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 99431 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 99431 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 99431 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 99431 # number of overall misses -system.cpu.icache.overall_misses::total 99431 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1030437000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1030437000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1030437000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1030437000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1030437000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1030437000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14126097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14126097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14126097 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14126097 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14126097 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14126097 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007039 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007039 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007039 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007039 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007039 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10363.337390 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10363.337390 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10363.337390 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10363.337390 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10363.337390 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10363.337390 # average overall miss latency +system.cpu.icache.replacements 92836 # number of replacements +system.cpu.icache.tagsinuse 1929.378925 # Cycle average of tags in use +system.cpu.icache.total_refs 14026889 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 94884 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.831974 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18060721000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1929.378925 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942080 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942080 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14026889 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14026889 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14026889 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14026889 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14026889 # number of overall hits +system.cpu.icache.overall_hits::total 14026889 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 99264 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 99264 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 99264 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 99264 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 99264 # number of overall misses +system.cpu.icache.overall_misses::total 99264 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1029034500 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10366.643496 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,286 +388,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4452 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4452 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4452 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4452 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4452 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4452 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94979 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 94979 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 94979 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 94979 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 94979 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 94979 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 637690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 637690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 637690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 637690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 637690000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 637690000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006724 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006724 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006724 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6714.010465 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6714.010465 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6714.010465 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6714.010465 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6714.010465 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6714.010465 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4379 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4379 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4379 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4379 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4379 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4379 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94885 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006717 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006717 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006717 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6715.250040 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6715.250040 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6715.250040 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6715.250040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6715.250040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6715.250040 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201568 # number of replacements -system.cpu.dcache.tagsinuse 4075.950137 # Cycle average of tags in use -system.cpu.dcache.total_refs 34352337 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205664 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.031357 # Average number of references to valid blocks. +system.cpu.dcache.replacements 201660 # number of replacements +system.cpu.dcache.tagsinuse 4075.950117 # Cycle average of tags in use +system.cpu.dcache.total_refs 34352002 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205756 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.955044 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 168155000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4075.950137 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4075.950117 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.995105 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.995105 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20774825 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20774825 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13577434 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13577434 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 78 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 78 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34352259 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1287631 # number of overall misses +system.cpu.dcache.overall_misses::total 1287631 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8533517000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8533517000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 45981514500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45981514500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54515031500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54515031500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54515031500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54515031500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21026189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21026189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 78 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 78 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35639645 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35639645 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35639645 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35639645 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011959 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011959 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070890 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.070890 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036122 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036122 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036122 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036122 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33931.077819 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33931.077819 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44365.782673 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44365.782673 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42327.750962 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42327.750962 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42327.750962 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42327.750962 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 103000 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35639566 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35639566 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35639566 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35639566 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011965 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011965 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070897 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.070897 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33918.886584 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33918.886584 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44381.773475 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44381.773475 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42337.464305 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42337.464305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42337.464305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42337.464305 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 96000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6058.823529 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5647.058824 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 166337 # number of writebacks -system.cpu.dcache.writebacks::total 166337 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 189183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 189183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 892539 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 892539 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1081722 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1081722 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1081722 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1081722 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62260 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6766238000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6766238000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6766238000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6766238000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002961 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002961 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005771 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005771 # 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average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 166377 # number of writebacks +system.cpu.dcache.writebacks::total 166377 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 189261 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 189261 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 892614 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 892614 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1081875 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1081875 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1081875 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1081875 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62325 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62325 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 94885 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205756 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 300641 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092164 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.479743 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.245814 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.913193 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.913193 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092020 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.782203 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.564161 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092020 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.782203 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.564161 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35318.764302 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34543.045804 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34718.460543 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38388.543154 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38388.543154 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35318.764302 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37673.567641 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37552.225386 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35318.764302 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37673.567641 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37552.225386 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 34000 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.913102 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.913102 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092164 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.781839 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.564171 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092164 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.781839 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.564171 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35321.326472 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34549.148801 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34723.889866 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38530.564485 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38530.564485 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35321.326472 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37790.576746 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37663.265787 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35321.326472 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37790.576746 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37663.265787 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2833.333333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2636.363636 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 116040 # number of writebacks -system.cpu.l2cache.writebacks::total 116040 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8740 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29910 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 38650 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130961 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130961 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8740 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 160871 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 169611 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8740 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 160871 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 169611 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 281019000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 942134500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1223153500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4629566000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4629566000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 281019000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5571700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5852719500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 281019000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5571700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5852719500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480451 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 116038 # number of writebacks +system.cpu.l2cache.writebacks::total 116038 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8745 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29899 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 38644 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130969 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130969 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 169613 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8745 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160868 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 169613 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 281196000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 941994500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1223190500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4649150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4649150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 281196000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5591145000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5872341000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 281196000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5591145000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5872341000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.479743 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.245814 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.564161 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782203 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.564161 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32153.203661 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31498.980274 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31646.921087 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35350.722734 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35350.722734 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32153.203661 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34634.586097 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34506.721262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32153.203661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34634.586097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34506.721262 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913102 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913102 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.781839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.564171 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.564171 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32155.060034 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31505.886484 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31652.792154 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35498.098787 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35498.098787 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32155.060034 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34756.104384 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34621.998314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32155.060034 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34756.104384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34621.998314 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6fb730a89..bc1c3c499 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024460 # Number of seconds simulated -sim_ticks 24460150500 # Number of ticks simulated -final_tick 24460150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024450 # Number of seconds simulated +sim_ticks 24450292500 # Number of ticks simulated +final_tick 24450292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167024 # Simulator instruction rate (inst/s) -host_op_rate 237012 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57603012 # Simulator tick rate (ticks/s) -host_mem_usage 242500 # Number of bytes of host memory used -host_seconds 424.63 # Real time elapsed on the host -sim_insts 70923824 # Number of instructions simulated -sim_ops 100643071 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8028736 # Number of bytes read from this memory -system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417152 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125449 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84643 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84643 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13367702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 328237392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 341605094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13367702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13367702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 221468466 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 221468466 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 221468466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13367702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 328237392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 563073559 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 166577 # Simulator instruction rate (inst/s) +host_op_rate 236377 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57425524 # Simulator tick rate (ticks/s) +host_mem_usage 242552 # Number of bytes of host memory used +host_seconds 425.77 # Real time elapsed on the host +sim_insts 70924074 # Number of instructions simulated +sim_ops 100643321 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 328512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8029568 # Number of bytes read from this memory +system.physmem.bytes_read::total 8358080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 328512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 328512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417984 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125462 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130595 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84656 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84656 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13435913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 328403760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 341839673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13435913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13435913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 221591787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 221591787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 221591787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13435913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 328403760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 563431460 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +77,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 48920302 # number of cpu cycles simulated +system.cpu.numCycles 48900586 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16960531 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12985874 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 661473 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11570513 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7976664 # Number of BTB hits +system.cpu.BPredUnit.lookups 16947895 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12979317 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 657239 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11568375 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7965689 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1883015 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 115088 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12843999 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87580035 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16960531 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9859679 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21787094 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2782746 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10982319 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 606 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12079139 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 221673 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47647021 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.336366 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1878366 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114401 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12822432 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87522774 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16947895 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9844055 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21770954 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2772902 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11003856 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 471 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12059223 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 218909 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47624951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336628 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25881368 54.32% 54.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2178299 4.57% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2007274 4.21% 63.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2021463 4.24% 67.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1548956 3.25% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1412983 2.97% 73.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 995678 2.09% 75.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1240946 2.60% 78.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10360054 21.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25875265 54.33% 54.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2171829 4.56% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2001256 4.20% 63.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2024856 4.25% 67.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1547627 3.25% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1411228 2.96% 73.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 995461 2.09% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1239299 2.60% 78.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10358130 21.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47647021 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346697 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.790259 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15031484 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9298191 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19969978 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1421734 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1925634 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3462876 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109476 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120212842 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 378015 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1925634 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16795731 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2963104 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 805180 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19544890 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5612482 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117675747 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 47624951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346579 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.789810 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15015037 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9311189 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19956662 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1421851 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1920212 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3461414 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109087 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 120161085 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 377153 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1920212 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16781785 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2961677 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 806772 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19529075 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5625430 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117632333 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12709 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4780104 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 263 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117787272 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541948309 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 541940540 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99158584 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18628688 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37002 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 36987 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13169886 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30082364 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22781735 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3607820 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4315548 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113341575 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51734 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108469975 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 351751 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12575588 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30093615 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14709 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47647021 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.276532 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995144 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 12238 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4786667 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 232 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117758479 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541753123 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541746251 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6872 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99158984 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18599495 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37350 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37333 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13184553 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30073818 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22775187 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3642294 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4290989 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113312109 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51967 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108452712 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 348423 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12547190 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29979206 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14892 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47624951 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.277225 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.996410 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11903537 24.98% 24.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8354851 17.53% 42.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7454693 15.65% 58.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7158692 15.02% 73.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5519097 11.58% 84.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3907609 8.20% 92.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1895733 3.98% 96.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881641 1.85% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571168 1.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11905380 25.00% 25.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8338489 17.51% 42.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7455711 15.66% 58.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7146400 15.01% 73.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5525482 11.60% 84.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3896676 8.18% 92.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1895621 3.98% 96.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 884969 1.86% 98.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 576223 1.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47647021 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47624951 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112989 4.45% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1419251 55.85% 60.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1008989 39.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113237 4.46% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1413224 55.65% 60.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1012935 39.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57363382 52.88% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91507 0.08% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57358153 52.89% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91504 0.08% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 228 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 207 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued @@ -239,158 +239,158 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29217041 26.94% 79.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21797810 20.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29210718 26.93% 79.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21792123 20.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108469975 # Type of FU issued -system.cpu.iq.rate 2.217279 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2541231 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023428 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 267479180 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125995514 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106424512 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 773 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1272 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 111010818 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 388 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2214998 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108452712 # Type of FU issued +system.cpu.iq.rate 2.217820 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2539396 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023415 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 267417480 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125938241 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106420258 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 714 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1140 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 175 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110991749 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 359 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2211393 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2772017 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7458 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29087 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2222758 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2763421 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7106 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29349 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2216160 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1925634 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 929341 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37355 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113473181 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 343640 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30082364 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22781735 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 35157 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2560 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3541 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29087 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 428613 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 264355 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 692968 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107247329 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28841677 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1222646 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1920212 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 926920 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38130 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113444221 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 341894 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30073818 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22775187 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35362 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2649 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29349 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 424803 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 263892 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 688695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107241565 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28837233 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1211147 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 79872 # number of nop insts executed -system.cpu.iew.exec_refs 50315882 # number of memory reference insts executed -system.cpu.iew.exec_branches 14663606 # Number of branches executed -system.cpu.iew.exec_stores 21474205 # Number of stores executed -system.cpu.iew.exec_rate 2.192287 # Inst execution rate -system.cpu.iew.wb_sent 106761196 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106424699 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53424049 # num instructions producing a value -system.cpu.iew.wb_consumers 103788661 # num instructions consuming a value +system.cpu.iew.exec_nop 80145 # number of nop insts executed +system.cpu.iew.exec_refs 50314250 # number of memory reference insts executed +system.cpu.iew.exec_branches 14661458 # Number of branches executed +system.cpu.iew.exec_stores 21477017 # Number of stores executed +system.cpu.iew.exec_rate 2.193053 # Inst execution rate +system.cpu.iew.wb_sent 106757510 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106420433 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53411369 # num instructions producing a value +system.cpu.iew.wb_consumers 103767535 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.175471 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514739 # average fanout of values written-back +system.cpu.iew.wb_rate 2.176261 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514721 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12825262 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37025 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 616891 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45721388 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.201347 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.733819 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12796121 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37075 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612942 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45704740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.202154 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.735561 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16264410 35.57% 35.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11914734 26.06% 61.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3626051 7.93% 69.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2926022 6.40% 75.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880797 4.11% 80.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1911030 4.18% 84.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 689200 1.51% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 582969 1.28% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5926175 12.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16269057 35.60% 35.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11908776 26.06% 61.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3615674 7.91% 69.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2919531 6.39% 75.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1872792 4.10% 80.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1908851 4.18% 84.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 687748 1.50% 85.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 590243 1.29% 87.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5932068 12.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45721388 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929376 # Number of instructions committed -system.cpu.commit.committedOps 100648623 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45704740 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929626 # Number of instructions committed +system.cpu.commit.committedOps 100648873 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869324 # Number of memory references committed -system.cpu.commit.loads 27310347 # Number of loads committed +system.cpu.commit.refs 47869424 # Number of memory references committed +system.cpu.commit.loads 27310397 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13671866 # Number of branches committed +system.cpu.commit.branches 13671916 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91485735 # Number of committed integer instructions. +system.cpu.commit.int_insts 91485935 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5926175 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5932068 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153243799 # The number of ROB reads -system.cpu.rob.rob_writes 228884039 # The number of ROB writes -system.cpu.timesIdled 52429 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1273281 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70923824 # Number of Instructions Simulated -system.cpu.committedOps 100643071 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70923824 # Number of Instructions Simulated -system.cpu.cpi 0.689758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.689758 # CPI: Total CPI of All Threads -system.cpu.ipc 1.449783 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.449783 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516242048 # number of integer regfile reads -system.cpu.int_regfile_writes 104369908 # number of integer regfile writes -system.cpu.fp_regfile_reads 886 # number of floating regfile reads -system.cpu.fp_regfile_writes 750 # number of floating regfile writes -system.cpu.misc_regfile_reads 146091713 # number of misc regfile reads -system.cpu.misc_regfile_writes 38318 # number of misc regfile writes -system.cpu.icache.replacements 30244 # number of replacements -system.cpu.icache.tagsinuse 1815.033473 # Cycle average of tags in use -system.cpu.icache.total_refs 12045499 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 32282 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 373.133604 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 153192367 # The number of ROB reads +system.cpu.rob.rob_writes 228820850 # The number of ROB writes +system.cpu.timesIdled 52344 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1275635 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924074 # Number of Instructions Simulated +system.cpu.committedOps 100643321 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924074 # Number of Instructions Simulated +system.cpu.cpi 0.689478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.689478 # CPI: Total CPI of All Threads +system.cpu.ipc 1.450373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.450373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516213591 # number of integer regfile reads +system.cpu.int_regfile_writes 104366681 # number of integer regfile writes +system.cpu.fp_regfile_reads 794 # number of floating regfile reads +system.cpu.fp_regfile_writes 662 # number of floating regfile writes +system.cpu.misc_regfile_reads 146023696 # number of misc regfile reads +system.cpu.misc_regfile_writes 38418 # number of misc regfile writes +system.cpu.icache.replacements 30034 # number of replacements +system.cpu.icache.tagsinuse 1814.104659 # Cycle average of tags in use +system.cpu.icache.total_refs 12025772 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32074 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 374.938330 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1815.033473 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.886247 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.886247 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12045501 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12045501 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12045501 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12045501 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12045501 # number of overall hits -system.cpu.icache.overall_hits::total 12045501 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33638 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33638 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33638 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33638 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33638 # number of overall misses -system.cpu.icache.overall_misses::total 33638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 406685000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 406685000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 406685000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 406685000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 406685000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 406685000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12079139 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12079139 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12079139 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12079139 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12079139 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12079139 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002785 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002785 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002785 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002785 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002785 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002785 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12090.046971 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12090.046971 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12090.046971 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12090.046971 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1814.104659 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885793 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885793 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12025773 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12025773 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12025773 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12025773 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12025773 # number of overall hits +system.cpu.icache.overall_hits::total 12025773 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33450 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33450 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33450 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33450 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33450 # number of overall misses +system.cpu.icache.overall_misses::total 33450 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 407167500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 407167500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 407167500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 407167500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 407167500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 407167500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12059223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12059223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12059223 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12059223 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12059223 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12059223 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002774 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002774 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002774 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002774 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002774 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002774 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12172.421525 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12172.421525 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12172.421525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12172.421525 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +399,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1313 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1313 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1313 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1313 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1313 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1313 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32325 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 32325 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 32325 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 32325 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 32325 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 32325 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 274223500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 274223500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 274223500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 274223500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 274223500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 274223500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8483.325599 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8483.325599 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1320 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1320 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1320 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1320 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1320 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1320 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32130 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32130 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32130 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32130 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32130 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32130 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275291000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 275291000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275291000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 275291000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275291000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 275291000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002664 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002664 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002664 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8568.036103 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8568.036103 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158501 # number of replacements -system.cpu.dcache.tagsinuse 4071.855185 # Cycle average of tags in use -system.cpu.dcache.total_refs 44605412 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162597 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.331089 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158627 # number of replacements +system.cpu.dcache.tagsinuse 4071.845451 # Cycle average of tags in use +system.cpu.dcache.total_refs 44602467 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162723 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 274.100570 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 272454000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4071.855185 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26278291 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26278291 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18287500 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18287500 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20317 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20317 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19158 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19158 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44565791 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44565791 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44565791 # number of overall hits -system.cpu.dcache.overall_hits::total 44565791 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 106674 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 106674 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1562401 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1562401 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1669075 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1669075 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1669075 # number of overall misses -system.cpu.dcache.overall_misses::total 1669075 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2574319000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2574319000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 63349260500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 63349260500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 629500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 629500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 65923579500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 65923579500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 65923579500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 65923579500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26384965 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26384965 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4071.845451 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994103 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994103 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26277362 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26277362 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18285328 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18285328 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20388 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20388 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19208 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19208 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44562690 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44562690 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44562690 # number of overall hits +system.cpu.dcache.overall_hits::total 44562690 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 106921 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 106921 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1564573 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1564573 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1671494 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1671494 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1671494 # number of overall misses +system.cpu.dcache.overall_misses::total 1671494 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2586655500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2586655500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63403235500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63403235500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 586000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 586000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 65989891000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 65989891000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 65989891000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 65989891000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26384283 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26384283 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20360 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20360 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19158 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19158 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46234866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46234866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46234866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46234866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004043 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078711 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078711 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002112 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002112 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036100 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036100 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036100 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036100 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24132.581510 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24132.581510 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40546.095721 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40546.095721 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14639.534884 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14639.534884 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39497.074427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39497.074427 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20429 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20429 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19208 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19208 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46234184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46234184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46234184 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46234184 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004052 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004052 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078820 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078820 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002007 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002007 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24192.212007 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24192.212007 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40524.306312 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40524.306312 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14292.682927 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14292.682927 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39479.585927 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39479.585927 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 202500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 210000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19090.909091 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128059 # number of writebacks -system.cpu.dcache.writebacks::total 128059 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51068 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51068 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1455366 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1455366 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1506434 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1506434 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1506434 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1506434 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55606 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55606 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107035 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107035 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162641 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162641 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162641 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162641 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 982100000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 982100000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3836030000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3836030000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4818130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4818130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4818130000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4818130000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17661.763119 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17661.763119 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35839.024618 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35839.024618 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 128131 # number of writebacks +system.cpu.dcache.writebacks::total 128131 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51186 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51186 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457528 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1457528 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1508714 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1508714 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1508714 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1508714 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55735 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55735 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107045 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107045 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162780 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162780 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162780 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162780 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 988383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 988383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3842536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3842536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4830919500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4830919500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4830919500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4830919500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003521 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003521 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17733.623396 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17733.623396 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35896.454762 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35896.454762 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 97988 # number of replacements -system.cpu.l2cache.tagsinuse 28616.670846 # Cycle average of tags in use -system.cpu.l2cache.total_refs 87010 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128775 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.675675 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 98022 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3994023000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4157964000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163941000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3994023000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 4157964000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416346 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321544 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.840909 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.840909 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5133 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125462 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130595 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5133 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125462 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130595 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164656500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 758645000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 923301500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1434000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1434000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3246125500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3246125500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164656500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4004770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4169427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164656500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4004770500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4169427000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.160056 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.322251 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807018 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807018 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955972 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955972 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771533 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.669971 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771533 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.669971 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32088.667058 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32536.865762 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32455.800616 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31679.731407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31679.731407 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.160056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771016 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.670430 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.160056 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771016 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.670430 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32078.024547 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32769.426807 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32643.950643 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31173.913043 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31173.913043 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31728.020447 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31728.020447 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32078.024547 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31920.186989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31926.390750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32078.024547 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31920.186989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31926.390750 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index def42a9fe..0d873282b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.996061 # Number of seconds simulated -sim_ticks 996061088500 # Number of ticks simulated -final_tick 996061088500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.996063 # Number of seconds simulated +sim_ticks 996062814500 # Number of ticks simulated +final_tick 996062814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139633 # Simulator instruction rate (inst/s) -host_op_rate 139633 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76428343 # Simulator tick rate (ticks/s) -host_mem_usage 218940 # Number of bytes of host memory used -host_seconds 13032.61 # Real time elapsed on the host +host_inst_rate 142352 # Simulator instruction rate (inst/s) +host_op_rate 142352 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77916645 # Simulator tick rate (ticks/s) +host_mem_usage 219096 # Number of bytes of host memory used +host_seconds 12783.70 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -24,32 +24,32 @@ system.physmem.num_reads::total 2150541 # Nu system.physmem.num_writes::writebacks 1048516 # Number of write requests responded to by this memory system.physmem.num_writes::total 1048516 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 55193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 138123705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138178898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138123466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138178659 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 55193 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 55193 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 67370390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 67370390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 67370390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 67370273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 67370273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 67370273 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 55193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 138123705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 205549288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138123466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 205548932 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444620723 # DTB read hits +system.cpu.dtb.read_hits 444620890 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449517801 # DTB read accesses +system.cpu.dtb.read_accesses 449517968 # DTB read accesses system.cpu.dtb.write_hits 160920434 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 162621738 # DTB write accesses -system.cpu.dtb.data_hits 605541157 # DTB hits +system.cpu.dtb.data_hits 605541324 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612139539 # DTB accesses +system.cpu.dtb.data_accesses 612139706 # DTB accesses system.cpu.itb.fetch_hits 232151959 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1992122178 # number of cpu cycles simulated +system.cpu.numCycles 1992125630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 328832264 # Number of BP lookups @@ -80,9 +80,9 @@ system.cpu.branch_predictor.RASInCorrect 6 # Nu system.cpu.branch_predictor.BTBHitPct 59.382560 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 175107833 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 153724431 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669698374 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 1669698372 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045900991 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 3045900989 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File @@ -93,16 +93,16 @@ system.cpu.execution_unit.predictedNotTakenIncorrect 12122106 system.cpu.execution_unit.mispredicted 133399918 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 81800180 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 61.988781 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139625101 # Number of Instructions Executed. +system.cpu.execution_unit.executions 1139625100 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1749883167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1749884347 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7972682 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 415150633 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576971545 # Number of cycles cpu stages are processed. -system.cpu.activity 79.160383 # Percentage of cycles cpu is active +system.cpu.timesIdled 7972692 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415154081 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576971549 # Number of cycles cpu stages are processed. +system.cpu.activity 79.160246 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -114,34 +114,34 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.094705 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.094707 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.094705 # CPI: Total CPI of All Threads -system.cpu.ipc 0.913488 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.094707 # CPI: Total CPI of All Threads +system.cpu.ipc 0.913487 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.913488 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 801357098 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190765080 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.773697 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1059714238 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932407940 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.804757 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1018188148 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.913487 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 801360547 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190765083 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.773594 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1059717687 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932407943 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.804676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1018191600 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 973934030 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.889272 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1582467246 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 48.889187 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1582470698 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 409654932 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.563745 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 969329070 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022793108 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.341887 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 20.563710 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 969332524 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022793106 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.341797 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 666.783228 # Cycle average of tags in use +system.cpu.icache.tagsinuse 666.783134 # Cycle average of tags in use system.cpu.icache.total_refs 232150871 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 270257.125728 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.783228 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 666.783134 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.325578 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.325578 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 232150871 # number of ReadReq hits @@ -219,39 +219,39 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 55155.995343 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107309 # number of replacements -system.cpu.dcache.tagsinuse 4082.354199 # Cycle average of tags in use -system.cpu.dcache.total_refs 595073835 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111405 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310875 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9107311 # number of replacements +system.cpu.dcache.tagsinuse 4082.354222 # Cycle average of tags in use +system.cpu.dcache.total_refs 595073825 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111407 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.310860 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 12655884000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.354199 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4082.354222 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.996669 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271435 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271435 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157802400 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157802400 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595073835 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595073835 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595073835 # number of overall hits -system.cpu.dcache.overall_hits::total 595073835 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2926102 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2926102 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10250330 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10250330 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10250330 # number of overall misses -system.cpu.dcache.overall_misses::total 10250330 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 166496556500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 166496556500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 130053734500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 130053734500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 296550291000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 296550291000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 296550291000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 296550291000 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 437271433 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271433 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157802392 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157802392 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595073825 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595073825 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595073825 # number of overall hits +system.cpu.dcache.overall_hits::total 595073825 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324230 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324230 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2926110 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2926110 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10250340 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10250340 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10250340 # number of overall misses +system.cpu.dcache.overall_misses::total 10250340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 166497124500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 166497124500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 130098294500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 130098294500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 296595419000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 296595419000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 296595419000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 296595419000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -268,48 +268,48 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016934 system.cpu.dcache.demand_miss_rate::total 0.016934 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016934 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016934 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.301138 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.301138 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44446.070062 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44446.070062 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28930.804277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28930.804277 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 76478500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8150814500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14619 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.372481 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.372481 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44461.176955 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44461.176955 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28935.178638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28935.178638 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 78626000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8150818500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14909 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 208452 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5231.445379 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 39101.637307 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5273.727279 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39101.656496 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389633 # number of writebacks -system.cpu.dcache.writebacks::total 3389633 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3389635 # number of writebacks +system.cpu.dcache.writebacks::total 3389635 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101948 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 101948 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036977 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1036977 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1138925 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1138925 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1138925 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1138925 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036985 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1036985 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1138933 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1138933 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1138933 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1138933 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889125 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1889125 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111405 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111405 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111405 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111405 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938235500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938235500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71711487500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71711487500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212649723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212649723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212649723000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212649723000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9111407 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111407 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111407 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111407 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938792000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938792000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71755618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71755618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212694410500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212694410500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212694410500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212694410500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -318,38 +318,38 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.368800 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.368800 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37960.160127 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37960.160127 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23338.850924 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23338.850924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23338.850924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23338.850924 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.440450 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.440450 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37983.520678 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37983.520678 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2133758 # number of replacements -system.cpu.l2cache.tagsinuse 30551.127244 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8448350 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 30551.128505 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8448354 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2163449 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905038 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 184402684000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14423.839124 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.322166 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16092.965953 # Average occupied blocks per requestor +system.cpu.l2cache.avg_refs 3.905040 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 184403463000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14423.846214 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 34.322158 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16092.960133 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.440181 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001047 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.491118 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.932346 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389633 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389633 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5860989 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5860989 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3389635 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3389635 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1100736 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1100736 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6961723 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6961723 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6961723 # number of overall hits -system.cpu.l2cache.overall_hits::total 6961723 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.data 6961725 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6961725 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6961725 # number of overall hits +system.cpu.l2cache.overall_hits::total 6961725 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1360852 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 1361711 # number of ReadReq misses @@ -362,29 +362,29 @@ system.cpu.l2cache.overall_misses::cpu.inst 859 # system.cpu.l2cache.overall_misses::cpu.data 2149682 # number of overall misses system.cpu.l2cache.overall_misses::total 2150541 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46160000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71425674500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71471834500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41981087000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41981087000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71427566000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71473726000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42035467500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 42035467500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 46160000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 113406761500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 113452921500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 113463033500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 113509193500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 46160000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 113406761500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 113452921500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 113463033500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 113509193500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221839 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222698 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3389633 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3389633 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3389635 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3389635 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889566 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889566 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111405 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112264 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111407 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112266 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111405 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112264 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111407 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112266 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses @@ -397,21 +397,21 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_miss_rate::cpu.data 0.235933 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.236005 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53736.903376 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52485.997375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52486.786477 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53219.435113 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53219.435113 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52487.387313 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52488.175538 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53288.373287 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53288.373287 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52755.133783 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52755.525935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52781.692374 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52755.133783 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52755.525935 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3381000 # number of cycles access was blocked +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52781.692374 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3730000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 111 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 142 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 30459.459459 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 26267.605634 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -429,16 +429,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 system.cpu.l2cache.overall_mshr_misses::cpu.data 2149682 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2150541 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35698000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54780311000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54816009000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32410594000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32410594000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54782223000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54817921000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32465310500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32465310500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35698000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87190905000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 87226603000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87247533500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87283231500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35698000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87190905000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 87226603000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87247533500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87283231500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses @@ -451,16 +451,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.236005 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41557.625146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40254.422230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40255.244321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41086.918601 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41086.918601 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40255.827232 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40256.648437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41156.282723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41156.282723 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 24a60df2f..693f470b9 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.621255 # Number of seconds simulated -sim_ticks 621254733000 # Number of ticks simulated -final_tick 621254733000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.621337 # Number of seconds simulated +sim_ticks 621337354500 # Number of ticks simulated +final_tick 621337354500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 206958 # Simulator instruction rate (inst/s) -host_op_rate 206958 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74061263 # Simulator tick rate (ticks/s) -host_mem_usage 219968 # Number of bytes of host memory used -host_seconds 8388.39 # Real time elapsed on the host +host_inst_rate 185902 # Simulator instruction rate (inst/s) +host_op_rate 185902 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66535120 # Simulator tick rate (ticks/s) +host_mem_usage 220128 # Number of bytes of host memory used +host_seconds 9338.49 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138177216 # Number of bytes read from this memory -system.physmem.bytes_read::total 138239104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67208512 # Number of bytes written to this memory -system.physmem.bytes_written::total 67208512 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2159019 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2159986 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050133 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050133 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 99618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 222416359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 222515977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 99618 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99618 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 108181891 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 108181891 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 108181891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 99618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 222416359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 330697869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 62208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138182080 # Number of bytes read from this memory +system.physmem.bytes_read::total 138244288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67208384 # Number of bytes written to this memory +system.physmem.bytes_written::total 67208384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2159095 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2160067 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050131 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050131 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 100120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 222394612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 222494732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 100120 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100120 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 108167300 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 108167300 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 108167300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 100120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 222394612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 330662032 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 614267388 # DTB read hits -system.cpu.dtb.read_misses 10994218 # DTB read misses +system.cpu.dtb.read_hits 614254083 # DTB read hits +system.cpu.dtb.read_misses 10995703 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625261606 # DTB read accesses -system.cpu.dtb.write_hits 208720588 # DTB write hits -system.cpu.dtb.write_misses 6852950 # DTB write misses +system.cpu.dtb.read_accesses 625249786 # DTB read accesses +system.cpu.dtb.write_hits 208699163 # DTB write hits +system.cpu.dtb.write_misses 6860235 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 215573538 # DTB write accesses -system.cpu.dtb.data_hits 822987976 # DTB hits -system.cpu.dtb.data_misses 17847168 # DTB misses +system.cpu.dtb.write_accesses 215559398 # DTB write accesses +system.cpu.dtb.data_hits 822953246 # DTB hits +system.cpu.dtb.data_misses 17855938 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 840835144 # DTB accesses -system.cpu.itb.fetch_hits 402675877 # ITB hits -system.cpu.itb.fetch_misses 58 # ITB misses +system.cpu.dtb.data_accesses 840809184 # DTB accesses +system.cpu.itb.fetch_hits 402673269 # ITB hits +system.cpu.itb.fetch_misses 61 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 402675935 # ITB accesses +system.cpu.itb.fetch_accesses 402673330 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,145 +67,145 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1242509467 # number of cpu cycles simulated +system.cpu.numCycles 1242674710 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 383372990 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 295235565 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19006052 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 268408458 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 264104025 # Number of BTB hits +system.cpu.BPredUnit.lookups 383387811 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 295251517 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19004234 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 268604084 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 264111879 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25197943 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6076 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 414160425 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3172269212 # Number of instructions fetch has processed -system.cpu.fetch.Branches 383372990 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 289301968 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 579083206 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 137694854 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 132940581 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1360 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 402675877 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10477889 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1238022002 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.562369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.158541 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25192938 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6291 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 414146940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3172273422 # Number of instructions fetch has processed +system.cpu.fetch.Branches 383387811 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 289304817 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 579090604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 137696439 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133107618 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1380 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 402673269 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10484478 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1238186640 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.562032 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.158458 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 658938796 53.23% 53.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43587849 3.52% 56.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22400320 1.81% 58.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 41027424 3.31% 61.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127967453 10.34% 72.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63937343 5.16% 77.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40820174 3.30% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30420264 2.46% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 208922379 16.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 659096036 53.23% 53.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43594264 3.52% 56.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22394894 1.81% 58.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 41029945 3.31% 61.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127979061 10.34% 72.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63938505 5.16% 77.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40814246 3.30% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30412222 2.46% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 208927467 16.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1238022002 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308547 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.553115 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 444879640 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117490931 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 546452553 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17363359 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 111835519 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60534072 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 962 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3092225969 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2145 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 111835519 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 466447238 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 65379308 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540801711 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53552759 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3009893694 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 588891 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2795172 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 47908313 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2251120190 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3888621958 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3887220740 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1401218 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1238186640 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308518 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.552779 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 444874368 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117661314 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 546409633 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17402131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 111839194 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60535765 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 960 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3092199728 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2107 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 111839194 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 466426212 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 65454708 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5539 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 540814331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53646656 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3009948527 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 590628 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2809331 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 47992017 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2251177447 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3888711604 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3887318453 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1393151 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 874917227 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 215 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 214 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112891088 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679356489 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 252372715 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 62271668 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36485662 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2703868851 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 183 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2499086402 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3468008 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 959949757 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 407382923 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 154 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1238022002 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.018612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.960549 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 874974484 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 208 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 207 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112977902 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679363507 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 252361148 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 62396219 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36704407 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2703896552 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2499071963 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3469199 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 959964040 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 407445563 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 151 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1238186640 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.018332 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.960312 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 396920026 32.06% 32.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203237579 16.42% 48.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185771607 15.01% 63.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153281748 12.38% 75.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136530779 11.03% 86.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79975547 6.46% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 62882805 5.08% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14212604 1.15% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5209307 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 396950099 32.06% 32.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203265879 16.42% 48.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185984424 15.02% 63.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153264847 12.38% 75.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 136492690 11.02% 86.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79936535 6.46% 93.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 62863067 5.08% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14221934 1.15% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5207165 0.42% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1238022002 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1238186640 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1901972 10.18% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12247269 65.56% 75.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4530432 24.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1904668 10.20% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12253005 65.59% 75.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4524321 24.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1633606519 65.37% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1633622343 65.37% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 295 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 168 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 36 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 285 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 166 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 37 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.37% # Type of FU issued @@ -228,84 +228,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.37% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 642839630 25.72% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 222639616 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 642829515 25.72% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 222619482 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2499086402 # Type of FU issued -system.cpu.iq.rate 2.011322 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18679673 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007475 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6256352202 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3662566047 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2395383662 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1990285 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1357397 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 872084 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2516787863 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 978212 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57513083 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2499071963 # Type of FU issued +system.cpu.iq.rate 2.011043 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18681994 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007476 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6256498920 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3662616880 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2395384352 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1982839 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1348326 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 869815 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2516779289 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 974668 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57504336 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234760826 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 254713 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 106352 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 91644213 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234767844 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 254077 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 105937 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 91632646 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 271 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 267185 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 220 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 267187 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 111835519 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23640124 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1166146 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2847163562 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17865598 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679356489 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 252372715 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 183 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 265739 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14899 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 106352 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13291147 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8879247 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22170394 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2446896238 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625263073 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 52190164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 111839194 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23661056 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1167024 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2847195647 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17872608 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679363507 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 252361148 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 180 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 266250 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15108 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 105937 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13288388 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8880688 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22169076 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2446901289 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625251329 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 52170674 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 143294528 # number of nop insts executed -system.cpu.iew.exec_refs 840836661 # number of memory reference insts executed -system.cpu.iew.exec_branches 299907540 # Number of branches executed -system.cpu.iew.exec_stores 215573588 # Number of stores executed -system.cpu.iew.exec_rate 1.969318 # Inst execution rate -system.cpu.iew.wb_sent 2424978134 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2396255746 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1371174091 # num instructions producing a value -system.cpu.iew.wb_consumers 1736703047 # num instructions consuming a value +system.cpu.iew.exec_nop 143298915 # number of nop insts executed +system.cpu.iew.exec_refs 840810767 # number of memory reference insts executed +system.cpu.iew.exec_branches 299911480 # Number of branches executed +system.cpu.iew.exec_stores 215559438 # Number of stores executed +system.cpu.iew.exec_rate 1.969060 # Inst execution rate +system.cpu.iew.wb_sent 2424991603 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2396254167 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1371180261 # num instructions producing a value +system.cpu.iew.wb_consumers 1736709964 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.928561 # insts written-back per cycle +system.cpu.iew.wb_rate 1.928304 # insts written-back per cycle system.cpu.iew.wb_fanout 0.789527 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 793041487 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 793091861 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19005172 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1126186483 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.615878 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.496171 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19003362 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1126347446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.615647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.496030 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 601057240 53.37% 53.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181431262 16.11% 69.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90818871 8.06% 77.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53582935 4.76% 82.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36462614 3.24% 85.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28190767 2.50% 88.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22584019 2.01% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22816288 2.03% 92.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89242487 7.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 601147369 53.37% 53.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181479999 16.11% 69.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90892282 8.07% 77.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53587955 4.76% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36442488 3.24% 85.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28128451 2.50% 88.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22594945 2.01% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22821835 2.03% 92.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89252122 7.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1126186483 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1126347446 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89242487 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89252122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3563986409 # The number of ROB reads -system.cpu.rob.rob_writes 5337596119 # The number of ROB writes -system.cpu.timesIdled 386257 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4487465 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3564188111 # The number of ROB reads +system.cpu.rob.rob_writes 5337700893 # The number of ROB writes +system.cpu.timesIdled 386272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4488070 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.715713 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.715713 # CPI: Total CPI of All Threads -system.cpu.ipc 1.397208 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.397208 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3289961910 # number of integer regfile reads -system.cpu.int_regfile_writes 1921843103 # number of integer regfile writes -system.cpu.fp_regfile_reads 52840 # number of floating regfile reads -system.cpu.fp_regfile_writes 576 # number of floating regfile writes +system.cpu.cpi 0.715808 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.715808 # CPI: Total CPI of All Threads +system.cpu.ipc 1.397022 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.397022 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3289961218 # number of integer regfile reads +system.cpu.int_regfile_writes 1921862672 # number of integer regfile writes +system.cpu.fp_regfile_reads 50916 # number of floating regfile reads +system.cpu.fp_regfile_writes 565 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 769.288412 # Cycle average of tags in use -system.cpu.icache.total_refs 402674417 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 967 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 416416.149948 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 773.343215 # Cycle average of tags in use +system.cpu.icache.total_refs 402671818 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 972 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 414271.417695 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 769.288412 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375629 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375629 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 402674417 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 402674417 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 402674417 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 402674417 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 402674417 # number of overall hits -system.cpu.icache.overall_hits::total 402674417 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1460 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1460 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1460 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1460 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1460 # number of overall misses -system.cpu.icache.overall_misses::total 1460 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51984000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51984000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51984000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51984000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51984000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51984000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 402675877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 402675877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 402675877 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 402675877 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 402675877 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 402675877 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 773.343215 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.377609 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.377609 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 402671818 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 402671818 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 402671818 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 402671818 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 402671818 # number of overall hits +system.cpu.icache.overall_hits::total 402671818 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1451 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1451 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1451 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1451 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1451 # number of overall misses +system.cpu.icache.overall_misses::total 1451 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 52415500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52415500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 52415500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52415500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 52415500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52415500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 402673269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 402673269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 402673269 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 402673269 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 402673269 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 402673269 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35605.479452 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35605.479452 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35605.479452 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35605.479452 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35605.479452 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35605.479452 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36123.707788 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36123.707788 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36123.707788 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36123.707788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36123.707788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36123.707788 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,301 +388,301 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 493 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 493 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 493 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 493 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 493 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 493 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 967 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 967 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 967 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 967 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 967 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 967 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36487500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36487500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36487500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36487500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36487500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36487500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 479 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 479 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 479 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 972 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 972 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 972 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 972 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 972 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36902500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36902500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36902500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36902500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36902500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36902500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37732.678387 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37732.678387 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37732.678387 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37732.678387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37732.678387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37732.678387 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37965.534979 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37965.534979 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37965.534979 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37965.534979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37965.534979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37965.534979 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9177386 # number of replacements -system.cpu.dcache.tagsinuse 4086.021231 # Cycle average of tags in use -system.cpu.dcache.total_refs 702056589 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9181482 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.464408 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9177741 # number of replacements +system.cpu.dcache.tagsinuse 4086.022558 # Cycle average of tags in use +system.cpu.dcache.total_refs 702049039 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9181837 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.460630 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5710472000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.021231 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4086.022558 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997564 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 546233301 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 546233301 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155823284 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155823284 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 702056585 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 702056585 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 702056585 # number of overall hits -system.cpu.dcache.overall_hits::total 702056585 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10361176 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10361176 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4905218 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4905218 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 546225954 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 546225954 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155823082 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155823082 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 702049036 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 702049036 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 702049036 # number of overall hits +system.cpu.dcache.overall_hits::total 702049036 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10364055 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10364055 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4905420 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4905420 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15266394 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15266394 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15266394 # number of overall misses -system.cpu.dcache.overall_misses::total 15266394 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 211386484000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 211386484000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 166231514528 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 166231514528 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 71000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 377617998528 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 377617998528 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 377617998528 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 377617998528 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 556594477 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 556594477 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 15269475 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15269475 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15269475 # number of overall misses +system.cpu.dcache.overall_misses::total 15269475 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 211607642000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 211607642000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 166442600009 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 166442600009 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 65000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 65000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 378050242009 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 378050242009 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 378050242009 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 378050242009 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 556590009 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 556590009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 717322979 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 717322979 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 717322979 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 717322979 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018615 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.018615 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030519 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030519 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20401.784894 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20401.784894 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33888.710864 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33888.710864 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24735.245175 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24735.245175 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24735.245175 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24735.245175 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 705051055 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1696782500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 102430 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65119 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6883.247633 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26056.642455 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 717318511 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 717318511 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 717318511 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 717318511 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018621 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.018621 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030520 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030520 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.400000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.400000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021287 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021287 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021287 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021287 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20417.456488 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20417.456488 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33930.346435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33930.346435 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24758.561903 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24758.561903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24758.561903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24758.561903 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 705064541 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1696790500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 102448 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65121 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6882.169891 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26055.965050 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3417165 # number of writebacks -system.cpu.dcache.writebacks::total 3417165 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3063278 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3063278 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3021635 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3021635 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3417249 # number of writebacks +system.cpu.dcache.writebacks::total 3417249 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3065881 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3065881 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3021758 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3021758 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6084913 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6084913 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6084913 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6084913 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7297898 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7297898 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883583 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883583 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 6087639 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6087639 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6087639 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6087639 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7298174 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7298174 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883662 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883662 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9181481 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9181481 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9181481 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9181481 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97194400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 97194400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53824994530 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53824994530 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9181836 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9181836 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9181836 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9181836 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97342451000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 97342451000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53846535513 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53846535513 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 40500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 40500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151019395030 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151019395030 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151019395030 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151019395030 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151188986513 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151188986513 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151188986513 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151188986513 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013112 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013112 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012800 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012800 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012800 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012800 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13318.136332 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13318.136332 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28575.854916 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28575.854916 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.918636 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.918636 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28586.092151 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28586.092151 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 40500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 40500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16448.260910 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16448.260910 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16448.260910 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16448.260910 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16466.095290 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16466.095290 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16466.095290 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16466.095290 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2143567 # number of replacements -system.cpu.l2cache.tagsinuse 30910.999406 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8542221 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2173263 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.930597 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 109501601000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14438.768585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 29.814922 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16442.415898 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440636 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000910 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.501783 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.943329 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5921293 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5921293 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3417165 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3417165 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1101170 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1101170 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7022463 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7022463 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7022463 # number of overall hits -system.cpu.l2cache.overall_hits::total 7022463 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 967 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1376593 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1377560 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 782426 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 782426 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 967 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2159019 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2159986 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 967 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2159019 # number of overall misses -system.cpu.l2cache.overall_misses::total 2159986 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35122000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48976797500 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188629 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188737 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415389 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188640 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188748 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415341 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415341 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235149 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235230 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33157.704240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32715.872085 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32716.069888 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33157.704240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32715.872085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32716.069888 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235229 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33409.979424 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32513.735092 # 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Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 13d5bc965..7bf311873 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.479151 # Number of seconds simulated -sim_ticks 479150606000 # Number of ticks simulated -final_tick 479150606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.479223 # Number of seconds simulated +sim_ticks 479223482000 # Number of ticks simulated +final_tick 479223482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 194711 # Simulator instruction rate (inst/s) -host_op_rate 217215 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60402792 # Simulator tick rate (ticks/s) -host_mem_usage 234724 # Number of bytes of host memory used -host_seconds 7932.59 # Real time elapsed on the host +host_inst_rate 194014 # Simulator instruction rate (inst/s) +host_op_rate 216437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60195599 # Simulator tick rate (ticks/s) +host_mem_usage 234776 # Number of bytes of host memory used +host_seconds 7961.11 # Real time elapsed on the host sim_insts 1544563028 # Number of instructions simulated sim_ops 1723073840 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156296384 # Number of bytes read from this memory -system.physmem.bytes_read::total 156344896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71934976 # Number of bytes written to this memory -system.physmem.bytes_written::total 71934976 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2442131 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2442889 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1123984 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1123984 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 101246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 326194691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 326295937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101246 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101246 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 150130199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 150130199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 150130199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 326194691 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 476426136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 48448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156331072 # Number of bytes read from this memory +system.physmem.bytes_read::total 156379520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71949824 # Number of bytes written to this memory +system.physmem.bytes_written::total 71949824 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2442673 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2443430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1124216 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1124216 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 101097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 326217470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 326318567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 150138352 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 150138352 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 150138352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 326217470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 476456920 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 958301213 # number of cpu cycles simulated +system.cpu.numCycles 958446965 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 302333500 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 248015603 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16105989 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 168718741 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 157776197 # Number of BTB hits +system.cpu.BPredUnit.lookups 302424004 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 248121310 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16111337 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 166375993 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 157791713 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18362417 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 295110918 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2170236667 # Number of instructions fetch has processed -system.cpu.fetch.Branches 302333500 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 176138614 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 431684517 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 85621855 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155290774 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 58 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 285908690 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5538082 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 950817611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.537566 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.220819 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18325977 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 236 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 295072409 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2170601008 # Number of instructions fetch has processed +system.cpu.fetch.Branches 302424004 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 176117690 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 431730569 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 85674794 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155376778 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 285867319 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5539236 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 950955907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.537748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.221191 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 519133170 54.60% 54.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23531871 2.47% 57.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38842821 4.09% 61.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47928811 5.04% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 41274787 4.34% 70.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 47187627 4.96% 75.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39143273 4.12% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18340446 1.93% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175434805 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 519225507 54.60% 54.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23584051 2.48% 57.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38809935 4.08% 61.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47901977 5.04% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 41256448 4.34% 70.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 47147738 4.96% 75.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39135623 4.12% 79.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18358633 1.93% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175535995 18.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 950817611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.315489 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.264671 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327140938 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 132753088 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 402950990 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19241929 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68730666 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46279846 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2359084469 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2481 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68730666 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 349892865 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63780880 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14141 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397813217 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70585842 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2300380626 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 28739 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5556251 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56445912 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2275326533 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10618275091 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10618272387 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2704 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 950955907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.315535 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.264706 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 327119471 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 132830999 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 402990203 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19239879 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 68775355 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46282380 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 697 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2359573845 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2428 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 68775355 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 349888082 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63823546 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14916 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397833782 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70620226 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2300864153 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 28671 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5550118 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 56484879 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2275806889 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10620956453 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10620952653 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3800 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319938 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 569006595 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5461 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5458 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 155601466 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 627528670 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219567806 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 87006993 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68089228 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2199559403 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1526 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2020307102 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5002319 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 472139724 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1101721580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 950817611 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.124810 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.914497 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 569486951 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5312 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5309 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 155780896 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 627644360 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219694213 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 87145300 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68089448 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2199982180 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1528 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2020409598 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4999430 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 472571343 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1103696346 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1357 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 950955907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.124609 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.914480 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 272456432 28.65% 28.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 148972541 15.67% 44.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161045064 16.94% 61.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 117808406 12.39% 73.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124487858 13.09% 86.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 74416152 7.83% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38351621 4.03% 98.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10558999 1.11% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2720538 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 272613444 28.67% 28.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 148967706 15.67% 44.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160979511 16.93% 61.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 117706760 12.38% 73.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124599704 13.10% 86.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 74507798 7.84% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38341084 4.03% 98.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10540920 1.11% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2698980 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 950817611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 950955907 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 866703 3.46% 3.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4868 0.02% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18978969 75.82% 79.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5181359 20.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 849524 3.40% 3.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4750 0.02% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18987433 76.01% 79.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5139841 20.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236552318 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 932322 0.05% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236587791 61.20% 61.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 931138 0.05% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.25% # Type of FU issued @@ -233,90 +233,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.25% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 41 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 64 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 12 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588904292 29.15% 90.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193918099 9.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 588900248 29.15% 90.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193990319 9.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2020307102 # Type of FU issued -system.cpu.iq.rate 2.108217 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25031899 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012390 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5021465735 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2671886632 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1961215820 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 298 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 520 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2045338849 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63654285 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2020409598 # Type of FU issued +system.cpu.iq.rate 2.108004 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24981548 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012365 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5021755668 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2672741554 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1961287360 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 736 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 160 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2045390937 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 209 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63645440 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 141601900 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 294123 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189203 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 44720760 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 141717590 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 292895 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189897 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 44847167 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1137177 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 1141778 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68730666 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28026748 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1485770 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2199569564 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5556141 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 627528670 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219567806 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1463 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 343326 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56332 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189203 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8602483 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10215552 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18818035 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1990553449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574287819 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29753653 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 68775355 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28059003 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1485687 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2199992043 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5558489 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 627644360 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219694213 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 343629 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56102 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189897 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8602375 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10226115 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18828490 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1990642810 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574277068 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29766788 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8635 # number of nop insts executed -system.cpu.iew.exec_refs 765252053 # number of memory reference insts executed -system.cpu.iew.exec_branches 238421113 # Number of branches executed -system.cpu.iew.exec_stores 190964234 # Number of stores executed -system.cpu.iew.exec_rate 2.077169 # Inst execution rate -system.cpu.iew.wb_sent 1970075771 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1961215932 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296581898 # num instructions producing a value -system.cpu.iew.wb_consumers 2068899277 # num instructions consuming a value +system.cpu.iew.exec_nop 8335 # number of nop insts executed +system.cpu.iew.exec_refs 765299887 # number of memory reference insts executed +system.cpu.iew.exec_branches 238409980 # Number of branches executed +system.cpu.iew.exec_stores 191022819 # Number of stores executed +system.cpu.iew.exec_rate 2.076946 # Inst execution rate +system.cpu.iew.wb_sent 1970153008 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1961287520 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296694675 # num instructions producing a value +system.cpu.iew.wb_consumers 2069023421 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.046555 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626701 # average fanout of values written-back +system.cpu.iew.wb_rate 2.046318 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626718 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 476570852 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 476993558 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 171 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16105557 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882086946 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.953406 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727739 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16110924 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 882180553 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.953199 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727625 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 391458685 44.38% 44.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194911052 22.10% 66.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73858259 8.37% 74.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35176751 3.99% 78.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19156374 2.17% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30712442 3.48% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19230333 2.18% 86.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11318069 1.28% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106264981 12.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 391561558 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 194873977 22.09% 66.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73868669 8.37% 74.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35208101 3.99% 78.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19136047 2.17% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30738627 3.48% 84.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19218397 2.18% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11310881 1.28% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106264296 12.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882086946 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 882180553 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563046 # Number of instructions committed system.cpu.commit.committedOps 1723073858 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -327,70 +327,70 @@ system.cpu.commit.branches 213462364 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941845 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106264981 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106264296 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2975466076 # The number of ROB reads -system.cpu.rob.rob_writes 4468185114 # The number of ROB writes -system.cpu.timesIdled 802459 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7483602 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2975983074 # The number of ROB reads +system.cpu.rob.rob_writes 4469074827 # The number of ROB writes +system.cpu.timesIdled 802305 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7491058 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563028 # Number of Instructions Simulated system.cpu.committedOps 1723073840 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563028 # Number of Instructions Simulated -system.cpu.cpi 0.620435 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.620435 # CPI: Total CPI of All Threads -system.cpu.ipc 1.611772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.611772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9971004084 # number of integer regfile reads -system.cpu.int_regfile_writes 1941069131 # number of integer regfile writes -system.cpu.fp_regfile_reads 114 # number of floating regfile reads -system.cpu.fp_regfile_writes 123 # number of floating regfile writes -system.cpu.misc_regfile_reads 2910834876 # number of misc regfile reads +system.cpu.cpi 0.620530 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.620530 # CPI: Total CPI of All Threads +system.cpu.ipc 1.611527 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.611527 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9971495260 # number of integer regfile reads +system.cpu.int_regfile_writes 1941105565 # number of integer regfile writes +system.cpu.fp_regfile_reads 174 # number of floating regfile reads +system.cpu.fp_regfile_writes 178 # number of floating regfile writes +system.cpu.misc_regfile_reads 2911260843 # number of misc regfile reads system.cpu.misc_regfile_writes 126 # number of misc regfile writes -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 634.471646 # Cycle average of tags in use -system.cpu.icache.total_refs 285907562 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 789 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 362366.998733 # Average number of references to valid blocks. +system.cpu.icache.replacements 26 # number of replacements +system.cpu.icache.tagsinuse 632.958434 # Cycle average of tags in use +system.cpu.icache.total_refs 285866178 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 790 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 361855.921519 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 634.471646 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.309801 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.309801 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 285907562 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 285907562 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 285907562 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 285907562 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 285907562 # number of overall hits -system.cpu.icache.overall_hits::total 285907562 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1128 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1128 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1128 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1128 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1128 # number of overall misses -system.cpu.icache.overall_misses::total 1128 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40115500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40115500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40115500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40115500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40115500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40115500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 285908690 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 285908690 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 285908690 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 285908690 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 285908690 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 285908690 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 632.958434 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.309062 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.309062 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 285866178 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 285866178 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 285866178 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 285866178 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 285866178 # number of overall hits +system.cpu.icache.overall_hits::total 285866178 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses +system.cpu.icache.overall_misses::total 1141 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40467500 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28839000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28839000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36554.499366 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36554.499366 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36554.499366 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36554.499366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36554.499366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36554.499366 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36505.063291 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36505.063291 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36505.063291 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36505.063291 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36505.063291 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36505.063291 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 258868265000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 196333546730 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 196333546730 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 118500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 118500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 454885493493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 454885493493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 454885493493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 454885493493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 505250585 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 505250585 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 455201811730 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 455201811730 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 455201811730 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 455201811730 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 505245364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 505245364 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 87 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 87 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 89 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 89 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 677836632 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 677836632 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 677836632 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 677836632 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021351 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021351 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 677831411 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 677831411 # 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miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023573 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23979.909548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23979.909548 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37794.735220 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37794.735220 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033708 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033708 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023576 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023576 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023576 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023576 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23993.859729 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23993.859729 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37819.107373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37819.107373 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 39500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 39500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28468.211402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28468.211402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28468.211402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28468.211402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2516165984 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 147500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 424894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5921.867534 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16388.888889 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28485.144620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28485.144620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28485.144620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28485.144620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2522668245 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 141500 # 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number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3474615 # number of writebacks +system.cpu.dcache.writebacks::total 3474615 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3059553 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3059553 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3297512 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3297512 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6356757 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6356757 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6356757 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6356757 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91432769312 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215694149312 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215694149312 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215694149312 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215694149312 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015295 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015295 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 6357065 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6357065 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6357065 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22416.861982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22416.861982 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014197 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014197 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014197 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014197 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16100.450941 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16100.450941 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48332.672803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48332.672803 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438667 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.438667 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.959494 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.253831 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.253889 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.959494 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.253831 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.253889 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36239.445910 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35999.343322 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35999.456177 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39295.413239 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39295.413239 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36239.445910 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37120.369803 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37120.096524 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36239.445910 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37120.369803 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37120.096524 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 30034731 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2976 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 3559 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7834.757392 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8439.092723 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1123984 # number of writebacks -system.cpu.l2cache.writebacks::total 1123984 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1124216 # number of writebacks +system.cpu.l2cache.writebacks::total 1124216 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits @@ -658,50 +658,50 @@ system.cpu.l2cache.demand_mshr_hits::total 8 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611343 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1612101 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830788 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 830788 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2442131 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2442889 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2442131 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2442889 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25025500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 52778176000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52803201500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29830819408 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29830819408 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25025500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82608995408 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82634020908 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25025500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82608995408 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82634020908 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208507 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253808 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.253866 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253808 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.253866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33015.171504 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32754.153523 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32754.276252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35906.656581 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35906.656581 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33015.171504 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33826.602835 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33826.351057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33015.171504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33826.602835 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33826.351057 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 757 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611893 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1612650 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830780 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 830780 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2442673 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2443430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2442673 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2443430 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25045000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 52994170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53019215500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 30019129886 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 30019129886 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25045000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 83013300386 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 83038345386 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25045000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 83013300386 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 83038345386 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208541 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208618 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438667 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438667 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253830 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253888 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253830 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253888 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33084.544254 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32876.977876 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32877.075311 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36133.669426 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36133.669426 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33084.544254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33984.614554 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33984.335703 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33084.544254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33984.614554 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33984.335703 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index de241166d..181c5df24 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962054 # Number of seconds simulated -sim_ticks 1962054431000 # Number of ticks simulated -final_tick 1962054431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962058 # Number of seconds simulated +sim_ticks 1962057812000 # Number of ticks simulated +final_tick 1962057812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2014980 # Simulator instruction rate (inst/s) -host_op_rate 2014979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66592137800 # Simulator tick rate (ticks/s) -host_mem_usage 297124 # Number of bytes of host memory used -host_seconds 29.46 # Real time elapsed on the host -sim_insts 59368818 # Number of instructions simulated -sim_ops 59368818 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 834816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24594240 # Number of bytes read from this memory +host_inst_rate 1235183 # Simulator instruction rate (inst/s) +host_op_rate 1235183 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40819911602 # Simulator tick rate (ticks/s) +host_mem_usage 297060 # Number of bytes of host memory used +host_seconds 48.07 # Real time elapsed on the host +sim_insts 59370518 # Number of instructions simulated +sim_ops 59370518 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 834432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24593280 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 572928 # Number of bytes read from this memory -system.physmem.bytes_read::total 28681856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 834816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 29056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7716416 # Number of bytes written to this memory -system.physmem.bytes_written::total 7716416 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384285 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 29312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 572992 # Number of bytes read from this memory +system.physmem.bytes_read::total 28680832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 834432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 29312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7715456 # Number of bytes written to this memory +system.physmem.bytes_written::total 7715456 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384270 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448154 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120569 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120569 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12534943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 292004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14618277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14809 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3932825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3932825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3932825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12534943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 292004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18551102 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 341254 # number of replacements -system.l2c.tagsinuse 65290.172220 # Cycle average of tags in use -system.l2c.total_refs 2492312 # Total number of references to valid blocks. -system.l2c.sampled_refs 406269 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.134635 # Average number of references to valid blocks. +system.physmem.num_reads::cpu1.inst 458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8953 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448138 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120554 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120554 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12534432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 292036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14617730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3932329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3932329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3932329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12534432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 292036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18550059 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 341238 # number of replacements +system.l2c.tagsinuse 65290.171288 # Cycle average of tags in use +system.l2c.total_refs 2492514 # Total number of references to valid blocks. +system.l2c.sampled_refs 406253 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.135374 # Average number of references to valid blocks. system.l2c.warmup_cycle 7854344000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55481.040218 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4824.761707 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4855.330442 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 116.015324 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 13.024529 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.846573 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073620 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 55481.148199 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4824.640956 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4855.323185 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 116.032373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 13.026576 # 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average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.950765 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40003.180886 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40002.307071 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.904973 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.440686 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.660793 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.471373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40014.462247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.568602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.471373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40014.462247 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -345,14 +345,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41698 # number of replacements -system.iocache.tagsinuse 0.566768 # Cycle average of tags in use +system.iocache.tagsinuse 0.566822 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1754521474000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.566768 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035423 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035423 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 0.566822 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035426 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035426 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -363,12 +363,12 @@ system.iocache.overall_misses::tsunami.ide 41730 # system.iocache.overall_misses::total 41730 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21239998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21239998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7628774806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7628774806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7650014804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7650014804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7650014804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7650014804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11448106806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11448106806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11469346804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11469346804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11469346804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11469346804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -387,17 +387,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119325.831461 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183595.851126 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183595.851126 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183321.706302 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183321.706302 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7551000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275512.774499 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275512.774499 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274846.556530 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274846.556530 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199371000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7072 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24657 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1067.731900 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8085.776858 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -413,12 +413,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41730 system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11983000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11983000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5467915000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5467915000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5479898000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5479898000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5479898000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5479898000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287247000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9287247000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9299230000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9299230000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9299230000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9299230000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -429,12 +429,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131592.101463 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131592.101463 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223509.024836 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223509.024836 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8658373 # DTB read hits +system.cpu0.dtb.read_hits 8658368 # DTB read hits system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.read_acv 174 # DTB read access violations system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.write_hits 6036768 # DTB write hits +system.cpu0.dtb.write_hits 6036843 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses system.cpu0.dtb.write_acv 115 # DTB write access violations system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.data_hits 14695141 # DTB hits +system.cpu0.dtb.data_hits 14695211 # DTB hits system.cpu0.dtb.data_misses 8485 # DTB misses system.cpu0.dtb.data_acv 289 # DTB access violations system.cpu0.dtb.data_accesses 719860 # DTB accesses -system.cpu0.itb.fetch_hits 3948342 # ITB hits +system.cpu0.itb.fetch_hits 3948323 # ITB hits system.cpu0.itb.fetch_misses 3841 # ITB misses system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_accesses 3952183 # ITB accesses +system.cpu0.itb.fetch_accesses 3952164 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +480,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3924108862 # number of cpu cycles simulated +system.cpu0.numCycles 3924115624 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54115388 # Number of instructions committed -system.cpu0.committedOps 54115388 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50086021 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 302769 # Number of float alu accesses -system.cpu0.num_func_calls 1426994 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6243543 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50086021 # number of integer instructions -system.cpu0.num_fp_insts 302769 # number of float instructions -system.cpu0.num_int_register_reads 68608752 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37121526 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 149232 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 152287 # number of times the floating registers were written -system.cpu0.num_mem_refs 14741011 # number of memory refs -system.cpu0.num_load_insts 8689642 # Number of load instructions -system.cpu0.num_store_insts 6051369 # Number of store instructions -system.cpu0.num_idle_cycles 3676810844.998126 # Number of idle cycles -system.cpu0.num_busy_cycles 247298017.001874 # Number of busy cycles +system.cpu0.committedInsts 54116505 # Number of instructions committed +system.cpu0.committedOps 54116505 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50087098 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 302903 # Number of float alu accesses +system.cpu0.num_func_calls 1426970 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6243728 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50087098 # number of integer instructions +system.cpu0.num_fp_insts 302903 # number of float instructions +system.cpu0.num_int_register_reads 68610814 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37122288 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 149298 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 152355 # number of times the floating registers were written +system.cpu0.num_mem_refs 14741096 # number of memory refs +system.cpu0.num_load_insts 8689646 # Number of load instructions +system.cpu0.num_store_insts 6051450 # Number of store instructions +system.cpu0.num_idle_cycles 3676817171.998126 # Number of idle cycles +system.cpu0.num_busy_cycles 247298452.001874 # Number of busy cycles system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6365 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202758 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72603 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 134 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202757 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72604 40.61% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104051 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178773 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71234 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 134 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 104050 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 178770 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71235 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71230 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144583 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900684456500 96.87% 96.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 103099000 0.01% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 795217500 0.04% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 71229 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144580 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900688314000 96.87% 96.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 102511500 0.01% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 795126500 0.04% 96.92% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60465248000 3.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962053593000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60465450000 3.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962056974000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684568 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808752 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684565 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808749 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed @@ -565,33 +565,33 @@ system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3870 2.06% 2.11% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3872 2.06% 2.11% # number of callpals executed system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 171949 91.52% 93.66% # number of callpals executed +system.cpu0.kern.callpal::swpipl 171948 91.52% 93.66% # number of callpals executed system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed -system.cpu0.kern.callpal::rti 4706 2.50% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4705 2.50% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.callpal::total 187881 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7232 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 7233 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1235 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1229 -system.cpu0.kern.mode_good::user 1230 +system.cpu0.kern.mode_good::kernel 1234 +system.cpu0.kern.mode_good::user 1235 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.169939 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170607 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.290593 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958392751000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3660835000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.291568 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958395542000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3661425000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3871 # number of times the context was actually changed +system.cpu0.kern.swap_context 3873 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -623,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 914730 # number of replacements -system.cpu0.icache.tagsinuse 508.781983 # Cycle average of tags in use -system.cpu0.icache.total_refs 53208794 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915241 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.136375 # Average number of references to valid blocks. +system.cpu0.icache.replacements 914851 # number of replacements +system.cpu0.icache.tagsinuse 508.781994 # Cycle average of tags in use +system.cpu0.icache.total_refs 53209789 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915362 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.129777 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.781983 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 508.781994 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53208794 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53208794 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53208794 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53208794 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53208794 # number of overall hits -system.cpu0.icache.overall_hits::total 53208794 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915369 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915369 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915369 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915369 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915369 # number of overall misses -system.cpu0.icache.overall_misses::total 915369 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13645389000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13645389000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13645389000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13645389000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13645389000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13645389000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54124163 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54124163 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54124163 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54124163 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54124163 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54124163 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016912 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016912 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016912 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016912 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016912 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016912 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.981775 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.981775 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14906.981775 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14906.981775 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 53209789 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53209789 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53209789 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53209789 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53209789 # number of overall hits +system.cpu0.icache.overall_hits::total 53209789 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915491 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915491 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915491 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915491 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915491 # number of overall misses +system.cpu0.icache.overall_misses::total 915491 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13646549000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13646549000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13646549000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13646549000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13646549000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13646549000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54125280 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54125280 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54125280 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54125280 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54125280 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54125280 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016914 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016914 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016914 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016914 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016914 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016914 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.262323 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.262323 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14906.262323 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14906.262323 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,112 +676,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915369 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915369 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915369 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915369 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915369 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915369 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10898588000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10898588000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10898588000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10898588000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10898588000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10898588000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016912 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016912 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016912 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11906.223610 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915491 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915491 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915491 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915491 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915491 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915491 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10899382500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10899382500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10899382500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10899382500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10899382500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10899382500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016914 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016914 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.504806 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1337806 # number of replacements -system.cpu0.dcache.tagsinuse 506.531092 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13370025 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338318 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.990170 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1337819 # number of replacements +system.cpu0.dcache.tagsinuse 506.532892 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13370103 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1338331 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.990132 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 101834000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.531092 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989319 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989319 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7444474 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7444474 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5554839 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5554839 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175825 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 175825 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191178 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191178 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12999313 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12999313 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12999313 # number of overall hits -system.cpu0.dcache.overall_hits::total 12999313 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1037616 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1037616 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 289306 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 289306 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16762 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16762 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 448 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 448 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1326922 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326922 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326922 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326922 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113316000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26113316000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963970000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8963970000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238512000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 238512000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4951000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4951000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 35077286000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 35077286000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 35077286000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 35077286000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482090 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8482090 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844145 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5844145 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192587 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 192587 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191626 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191626 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14326235 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14326235 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14326235 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14326235 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122330 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122330 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049504 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049504 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087036 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087036 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002338 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002338 # miss rate for StoreCondReq accesses +system.cpu0.dcache.occ_blocks::cpu0.data 506.532892 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.989322 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.989322 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7444463 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7444463 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5554933 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5554933 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175817 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 175817 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191182 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191182 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12999396 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12999396 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12999396 # number of overall hits +system.cpu0.dcache.overall_hits::total 12999396 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1037635 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1037635 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 289296 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 289296 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16772 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16772 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 445 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 445 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326931 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326931 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326931 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326931 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113637000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 26113637000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963228000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8963228000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238633000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 238633000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4867000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4867000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 35076865000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 35076865000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 35076865000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 35076865000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482098 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8482098 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5844229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192589 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 192589 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191627 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191627 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14326327 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14326327 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14326327 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14326327 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122332 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122332 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049501 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087087 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087087 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002322 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002322 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092622 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.092622 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092622 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.092622 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.647392 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.647392 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30984.390230 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30984.390230 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14229.328242 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14229.328242 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11051.339286 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11051.339286 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26435.077570 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26435.077570 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.495926 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.495926 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30982.896411 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30982.896411 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14228.058669 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14228.058669 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10937.078652 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10937.078652 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26434.580999 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26434.580999 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -790,62 +790,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 785164 # number of writebacks -system.cpu0.dcache.writebacks::total 785164 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037616 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1037616 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289306 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 289306 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16762 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16762 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 448 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 448 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326922 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1326922 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326922 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1326922 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000405022 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000405022 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8096051001 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8096051001 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188226000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188226000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3606001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3606001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096456023 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31096456023 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096456023 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31096456023 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1463096000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1463096000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2089087000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2089087000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3552183000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3552183000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122330 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122330 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049504 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049504 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002338 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.writebacks::writebacks 785166 # number of writebacks +system.cpu0.dcache.writebacks::total 785166 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037635 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1037635 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289296 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 289296 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16772 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16772 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 445 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 445 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326931 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326931 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326931 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326931 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000669022 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000669022 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8095339001 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8095339001 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3531001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3531001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096008023 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31096008023 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096008023 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31096008023 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461823000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461823000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2088243000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2088243000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3550066000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3550066000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122332 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122332 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049501 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049501 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002322 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.092622 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.092622 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.586697 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.586697 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27984.386777 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27984.386777 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11229.328242 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11229.328242 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8049.109375 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8049.109375 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.435232 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.435232 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27982.892957 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27982.892957 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11228.058669 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11228.058669 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7934.833708 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7934.833708 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -857,22 +857,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1027490 # DTB read hits +system.cpu1.dtb.read_hits 1027530 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.read_acv 36 # DTB read access violations system.cpu1.dtb.read_accesses 205838 # DTB read accesses -system.cpu1.dtb.write_hits 663174 # DTB write hits +system.cpu1.dtb.write_hits 663193 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses system.cpu1.dtb.write_acv 48 # DTB write access violations system.cpu1.dtb.write_accesses 97040 # DTB write accesses -system.cpu1.dtb.data_hits 1690664 # DTB hits +system.cpu1.dtb.data_hits 1690723 # DTB hits system.cpu1.dtb.data_misses 3106 # DTB misses system.cpu1.dtb.data_acv 84 # DTB access violations system.cpu1.dtb.data_accesses 302878 # DTB accesses -system.cpu1.itb.fetch_hits 1394882 # ITB hits +system.cpu1.itb.fetch_hits 1394871 # ITB hits system.cpu1.itb.fetch_misses 1246 # ITB misses system.cpu1.itb.fetch_acv 41 # ITB acv -system.cpu1.itb.fetch_accesses 1396128 # ITB accesses +system.cpu1.itb.fetch_accesses 1396117 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -885,51 +885,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923836450 # number of cpu cycles simulated +system.cpu1.numCycles 3923836552 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5253430 # Number of instructions committed -system.cpu1.committedOps 5253430 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4920456 # Number of integer alu accesses +system.cpu1.committedInsts 5254013 # Number of instructions committed +system.cpu1.committedOps 5254013 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4921025 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses -system.cpu1.num_func_calls 157592 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 506756 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4920456 # number of integer instructions +system.cpu1.num_func_calls 157600 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 506865 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4921025 # number of integer instructions system.cpu1.num_fp_insts 25430 # number of float instructions -system.cpu1.num_int_register_reads 6826440 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3699681 # number of times the integer registers were written +system.cpu1.num_int_register_reads 6827399 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3700117 # number of times the integer registers were written system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written -system.cpu1.num_mem_refs 1700289 # number of memory refs -system.cpu1.num_load_insts 1033544 # Number of load instructions -system.cpu1.num_store_insts 666745 # Number of store instructions -system.cpu1.num_idle_cycles 3903109824.944130 # Number of idle cycles -system.cpu1.num_busy_cycles 20726625.055870 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005282 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994718 # Percentage of idle cycles +system.cpu1.num_mem_refs 1700348 # number of memory refs +system.cpu1.num_load_insts 1033584 # Number of load instructions +system.cpu1.num_store_insts 666764 # Number of store instructions +system.cpu1.num_idle_cycles 3903107404.303190 # Number of idle cycles +system.cpu1.num_busy_cycles 20729147.696810 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005283 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994717 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 35943 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 35942 # number of hwrei instructions executed system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17500 60.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28707 # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17499 60.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28706 # number of times we switched to this ipl system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1920768070500 97.90% 97.90% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 725778000 0.04% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 67189500 0.00% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 40357157000 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961918195000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1920766593500 97.90% 97.90% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 726074500 0.04% 97.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 67017000 0.00% 97.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 40358561000 2.06% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961918246000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.516800 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.705159 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.516830 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.705184 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed @@ -959,7 +959,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24055 81.82% 83.15% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24054 81.82% 83.15% # number of callpals executed system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 90.52% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.01% 90.53% # number of callpals executed @@ -969,66 +969,66 @@ system.cpu1.kern.callpal::rti 2587 8.80% 99.34% # nu system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29400 # number of callpals executed +system.cpu1.kern.callpal::total 29399 # number of callpals executed system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches -system.cpu1.kern.mode_switch::user 516 # number of protection mode switches +system.cpu1.kern.mode_switch::user 515 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 532 -system.cpu1.kern.mode_good::user 516 +system.cpu1.kern.mode_good::kernel 531 +system.cpu1.kern.mode_good::user 515 system.cpu1.kern.mode_good::idle 16 -system.cpu1.kern.mode_switch_good::kernel 0.605233 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.604096 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.007711 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.306628 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4074736000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1594048000 0.08% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1955463610000 99.71% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 0.306140 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4075179000 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1593973000 0.08% 0.29% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1955466537000 99.71% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 366 # number of times the context was actually changed -system.cpu1.icache.replacements 86665 # number of replacements -system.cpu1.icache.tagsinuse 419.761966 # Cycle average of tags in use -system.cpu1.icache.total_refs 5169415 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 87177 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.297923 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1958459766000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.761966 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819848 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819848 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5169415 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5169415 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5169415 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5169415 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5169415 # number of overall hits -system.cpu1.icache.overall_hits::total 5169415 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 87205 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87205 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 87205 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87205 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 87205 # number of overall misses -system.cpu1.icache.overall_misses::total 87205 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1314538500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1314538500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1314538500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1314538500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1314538500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1314538500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5256620 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5256620 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5256620 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5256620 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5256620 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5256620 # number of overall (read+write) accesses +system.cpu1.icache.replacements 86678 # number of replacements +system.cpu1.icache.tagsinuse 419.761864 # Cycle average of tags in use +system.cpu1.icache.total_refs 5169985 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 87190 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.295619 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1958463060000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 419.761864 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.819847 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.819847 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5169985 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5169985 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5169985 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5169985 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5169985 # number of overall hits +system.cpu1.icache.overall_hits::total 5169985 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 87218 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 87218 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 87218 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 87218 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 87218 # number of overall misses +system.cpu1.icache.overall_misses::total 87218 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1315004000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1315004000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1315004000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1315004000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1315004000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1315004000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5257203 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5257203 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5257203 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5257203 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5257203 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5257203 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016590 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016590 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.016590 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016590 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.016590 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15074.118457 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15074.118457 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15074.118457 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15074.118457 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15074.118457 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15074.118457 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15077.208833 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15077.208833 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15077.208833 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15077.208833 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1037,112 +1037,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87205 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 87205 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 87205 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 87205 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 87205 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 87205 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1052891500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1052891500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1052891500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1052891500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1052891500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1052891500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87218 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 87218 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 87218 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 87218 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 87218 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 87218 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1053316500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1053316500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1053316500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1053316500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1053316500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1053316500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016590 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12073.751505 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12076.824738 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 53525 # number of replacements -system.cpu1.dcache.tagsinuse 416.811918 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1627176 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 53933 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.170322 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1941569697000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 416.811918 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.814086 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.814086 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 982724 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 982724 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 626457 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 626457 # number of WriteReq hits +system.cpu1.dcache.replacements 53530 # number of replacements +system.cpu1.dcache.tagsinuse 416.811223 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1627239 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 53938 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 30.168694 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1941569871000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 416.811223 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.814084 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.814084 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 982758 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 982758 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 626472 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 626472 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11310 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 11310 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11708 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 11708 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1609181 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1609181 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1609181 # number of overall hits -system.cpu1.dcache.overall_hits::total 1609181 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 35620 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 35620 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 22610 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 22610 # number of WriteReq misses +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11707 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 11707 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1609230 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1609230 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1609230 # number of overall hits +system.cpu1.dcache.overall_hits::total 1609230 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 35626 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 35626 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 22614 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 22614 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1003 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 1003 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 543 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 543 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 58230 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 58230 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 58230 # number of overall misses -system.cpu1.dcache.overall_misses::total 58230 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484449000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 484449000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 694363000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 694363000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 12193000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 12193000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7082000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 7082000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1178812000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 1178812000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 1178812000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 1178812000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1018344 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1018344 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 649067 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 649067 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 544 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 544 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 58240 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 58240 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 58240 # number of overall misses +system.cpu1.dcache.overall_misses::total 58240 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484494000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 484494000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 694414000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 694414000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 12192000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 12192000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7087000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 7087000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 1178908000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 1178908000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 1178908000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 1178908000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1018384 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1018384 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 649086 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 649086 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12313 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 12313 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12251 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 12251 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1667411 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1667411 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1667411 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1667411 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034978 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.034978 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034835 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034835 # miss rate for WriteReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 1667470 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1667470 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1667470 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1667470 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034983 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.034983 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034840 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034840 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081459 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081459 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044323 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044323 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034922 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034922 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034922 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034922 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13600.477260 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13600.477260 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30710.437859 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30710.437859 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12156.530409 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12156.530409 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13042.357274 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13042.357274 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20244.066632 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20244.066632 # average overall miss latency +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044405 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044405 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034927 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034927 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034927 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034927 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13599.449840 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13599.449840 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30707.260989 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30707.260989 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12155.533400 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12155.533400 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13027.573529 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13027.573529 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20242.239011 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20242.239011 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1151,62 +1151,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 35190 # number of writebacks -system.cpu1.dcache.writebacks::total 35190 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35620 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 35620 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22610 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 22610 # number of WriteReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 35195 # number of writebacks +system.cpu1.dcache.writebacks::total 35195 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35626 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 35626 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22614 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 22614 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1003 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1003 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 543 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 543 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 58230 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 58230 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 58230 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 58230 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377581004 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377581004 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626529004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626529004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9184000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9184000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5453000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5453000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004110008 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1004110008 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004110008 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1004110008 # number of overall MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 544 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 544 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 58240 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 58240 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 58240 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 58240 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377607005 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377607005 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626568004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626568004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9183000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9183000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5455000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5455000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004175009 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1004175009 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004175009 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1004175009 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20565000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20565000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534607500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534607500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555172500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555172500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034978 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034978 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034835 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534647000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534647000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555212000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555212000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034983 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034983 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034840 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034840 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081459 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044323 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044323 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034922 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034922 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10600.252779 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10600.252779 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27710.261123 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27710.261123 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9156.530409 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9156.530409 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10042.357274 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10042.357274 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044405 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044405 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034927 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034927 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10599.197356 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10599.197356 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27707.084284 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27707.084284 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9155.533400 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9155.533400 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10027.573529 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10027.573529 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 9ccbe5ddb..c82eab488 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.921792 # Number of seconds simulated -sim_ticks 1921792488000 # Number of ticks simulated -final_tick 1921792488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920895 # Number of seconds simulated +sim_ticks 1920895294000 # Number of ticks simulated +final_tick 1920895294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1964765 # Simulator instruction rate (inst/s) -host_op_rate 1964764 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67191639126 # Simulator tick rate (ticks/s) -host_mem_usage 295072 # Number of bytes of host memory used -host_seconds 28.60 # Real time elapsed on the host -sim_insts 56195476 # Number of instructions simulated -sim_ops 56195476 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory +host_inst_rate 1271848 # Simulator instruction rate (inst/s) +host_op_rate 1271848 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43474553061 # Simulator tick rate (ticks/s) +host_mem_usage 295012 # Number of bytes of host memory used +host_seconds 44.18 # Real time elapsed on the host +sim_insts 56195754 # Number of instructions simulated +sim_ops 56195754 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859968 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28361728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7403520 # Number of bytes written to this memory -system.physmem.bytes_written::total 7403520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28362816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404288 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388437 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443152 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115680 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115680 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12935191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1380145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14757955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3852403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3852403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3852403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12935191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1380145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18610359 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 336240 # number of replacements -system.l2c.tagsinuse 65308.066862 # Cycle average of tags in use -system.l2c.total_refs 2448422 # Total number of references to valid blocks. -system.l2c.sampled_refs 401402 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.099676 # Average number of references to valid blocks. +system.physmem.num_reads::total 443169 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115692 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115692 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12941865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1380789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14765415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3854603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3854603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3854603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 336257 # number of replacements +system.l2c.tagsinuse 65308.063316 # Cycle average of tags in use +system.l2c.total_refs 2448454 # Total number of references to valid blocks. +system.l2c.sampled_refs 401419 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.099497 # Average number of references to valid blocks. system.l2c.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55651.693971 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4767.859045 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4888.513847 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.849177 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.072752 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.074593 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.996522 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 916493 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 814973 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1731466 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835196 # number of Writeback hits -system.l2c.Writeback_hits::total 835196 # number of Writeback hits +system.l2c.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 814985 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1731448 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835257 # number of Writeback hits +system.l2c.Writeback_hits::total 835257 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187534 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187534 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 916493 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1002507 # number of demand (read+write) hits -system.l2c.demand_hits::total 1919000 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 916493 # number of overall hits -system.l2c.overall_hits::cpu.data 1002507 # number of overall hits -system.l2c.overall_hits::total 1919000 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 271963 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285254 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 116845 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116845 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 13291 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 388808 # number of demand (read+write) misses -system.l2c.demand_misses::total 402099 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 13291 # number of overall misses -system.l2c.overall_misses::cpu.data 388808 # number of overall misses -system.l2c.overall_misses::total 402099 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 691744000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 14147302000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14839046000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6076563000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6076563000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 691744000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20223865000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20915609000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 691744000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20223865000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20915609000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 929784 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1086936 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2016720 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835196 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835196 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304379 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304379 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 929784 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1391315 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2321099 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 929784 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1391315 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2321099 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014295 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.250211 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141445 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.777778 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.777778 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383880 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383880 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014295 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.279454 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173236 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014295 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.279454 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173236 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52046.046197 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.215849 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52020.465971 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.331850 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52005.331850 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52046.046197 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52015.043415 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52016.068182 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52046.046197 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52015.043415 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52016.068182 # average overall miss latency +system.l2c.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187565 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 916463 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1002550 # number of demand (read+write) hits +system.l2c.demand_hits::total 1919013 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 916463 # number of overall hits +system.l2c.overall_hits::cpu.data 1002550 # number of overall hits +system.l2c.overall_hits::total 1919013 # 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number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2321129 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173242 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173242 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 19076.923077 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.485149 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52005.485149 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52015.410976 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52015.410976 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,66 +141,66 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 74168 # number of writebacks -system.l2c.writebacks::total 74168 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 271963 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 388808 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 402099 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 388808 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 402099 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532249000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 10883746000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11415995000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 620000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 620000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4674423000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4674423000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 532249000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15558169000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16090418000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 532249000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15558169000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16090418000 # number of overall MSHR miss cycles +system.l2c.writebacks::writebacks 74180 # number of writebacks +system.l2c.writebacks::total 74180 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 271966 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 116861 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 116861 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 388827 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 402116 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 388827 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 402116 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 531734000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10884019000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11415753000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4675081000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4675081000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 531734000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15559100000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16090834000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 531734000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1893145000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1893145000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 3224695000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3224695000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250211 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.141445 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.777778 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.777778 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383880 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383880 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.279454 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173236 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.279454 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173236 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.820480 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.215849 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.455454 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.331850 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.331850 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.820480 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.043415 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40016.060721 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.820480 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.043415 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40016.060721 # average overall mshr miss latency +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.355427 # Cycle average of tags in use +system.iocache.tagsinuse 1.347775 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.355427 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084714 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084714 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 1.347775 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084236 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084236 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -227,12 +227,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7634106806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7634106806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7654779804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7654779804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7654779804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7654779804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11448538806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11448538806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11469211804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11469211804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11469211804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11469211804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -251,17 +251,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183724.172266 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183724.172266 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183457.874272 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183457.874272 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7454000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275523.171111 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275523.171111 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274876.256537 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274876.256537 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199147000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7097 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24626 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1050.302945 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8086.859417 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -277,12 +277,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5473252000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5473252000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5484928000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5484928000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5484928000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5484928000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287684000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9287684000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9299360000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9299360000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9299360000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9299360000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -293,12 +293,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131720.542934 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131720.542934 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223519.541779 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223519.541779 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066933 # DTB read hits +system.cpu.dtb.read_hits 9066995 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6357519 # DTB write hits +system.cpu.dtb.write_hits 6357563 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15424452 # DTB hits +system.cpu.dtb.data_hits 15424558 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4975863 # ITB hits +system.cpu.itb.fetch_hits 4975749 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980869 # ITB accesses +system.cpu.itb.fetch_accesses 4980755 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +344,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3843584976 # number of cpu cycles simulated +system.cpu.numCycles 3841790588 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195476 # Number of instructions committed -system.cpu.committedOps 56195476 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066692 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483822 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469666 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066692 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71339619 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530592 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15477059 # number of memory refs -system.cpu.num_load_insts 9103780 # Number of load instructions -system.cpu.num_store_insts 6373279 # Number of store instructions -system.cpu.num_idle_cycles 3588655153.998133 # Number of idle cycles -system.cpu.num_busy_cycles 254929822.001867 # Number of busy cycles -system.cpu.not_idle_fraction 0.066326 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933674 # Percentage of idle cycles +system.cpu.committedInsts 56195754 # Number of instructions committed +system.cpu.committedOps 56195754 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52066962 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1483816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469707 # number of instructions that are conditional controls +system.cpu.num_int_insts 52066962 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71340235 # number of times the integer registers were read +system.cpu.num_int_register_writes 38530699 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15477180 # number of memory refs +system.cpu.num_load_insts 9103852 # Number of load instructions +system.cpu.num_store_insts 6373328 # Number of store instructions +system.cpu.num_idle_cycles 3586858626.998133 # Number of idle cycles +system.cpu.num_busy_cycles 254931961.001867 # Number of busy cycles +system.cpu.not_idle_fraction 0.066358 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933642 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212119 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74932 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212106 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1937 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106298 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183298 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73565 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1937 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73565 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149198 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1861046523500 96.84% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 104284500 0.01% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 779455000 0.04% 96.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 59861392000 3.11% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1921791655000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981757 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106288 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183284 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860148981000 96.84% 96.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 104328000 0.01% 96.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 779009000 0.04% 96.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 59862143000 3.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920894461000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692064 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.813964 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692101 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.813988 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.16% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 176067 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6838 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 176055 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5162 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193021 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.callpal::total 193009 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323285 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323231 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080591 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46687559000 2.43% 2.43% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5260775000 0.27% 2.70% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869843314000 97.30% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.kern.mode_ticks::kernel 46683787000 2.43% 2.43% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5260006000 0.27% 2.70% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868950661000 97.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 929133 # number of replacements -system.cpu.icache.tagsinuse 508.706285 # Cycle average of tags in use -system.cpu.icache.total_refs 55277511 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929644 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.460945 # Average number of references to valid blocks. +system.cpu.icache.replacements 929101 # number of replacements +system.cpu.icache.tagsinuse 508.704776 # Cycle average of tags in use +system.cpu.icache.total_refs 55277821 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 929612 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.463326 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.706285 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993567 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993567 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55277511 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277511 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277511 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277511 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277511 # number of overall hits -system.cpu.icache.overall_hits::total 55277511 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929804 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929804 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929804 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929804 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929804 # number of overall misses -system.cpu.icache.overall_misses::total 929804 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13857748000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13857748000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13857748000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13857748000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13857748000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13857748000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56207315 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56207315 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56207315 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56207315 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56207315 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56207315 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 508.704776 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993564 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993564 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55277821 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55277821 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55277821 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55277821 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55277821 # number of overall hits +system.cpu.icache.overall_hits::total 55277821 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929772 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929772 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929772 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929772 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929772 # number of overall misses +system.cpu.icache.overall_misses::total 929772 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13856924500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13856924500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13856924500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13856924500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13856924500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13856924500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56207593 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56207593 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56207593 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56207593 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56207593 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56207593 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016542 # 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number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,54 +641,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835196 # number of writebacks -system.cpu.dcache.writebacks::total 835196 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069663 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069663 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304397 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304397 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 835257 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374121 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374121 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374121 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23451491000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23451491000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8326628000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8326628000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195902000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195902000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31778119000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31778119000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31778119000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31778119000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1421708000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1421708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011005000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011005000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3432713000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3432713000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120376 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120376 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049432 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049432 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086236 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086236 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.723640 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.723640 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.795179 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.795179 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.168297 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.168297 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3432514000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3432514000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049439 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049439 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086234 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086234 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091340 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091340 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091340 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091340 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.878962 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.878962 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.367721 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.367721 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.515660 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.515660 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23126.143185 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23126.143185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23126.143185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23126.143185 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index a84f458bf..ef29d389c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.207291 # Nu sim_ticks 1207290627000 # Number of ticks simulated final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1000042 # Simulator instruction rate (inst/s) -host_op_rate 1274494 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19638848032 # Simulator tick rate (ticks/s) -host_mem_usage 383956 # Number of bytes of host memory used -host_seconds 61.47 # Real time elapsed on the host +host_inst_rate 965295 # Simulator instruction rate (inst/s) +host_op_rate 1230212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18956490102 # Simulator tick rate (ticks/s) +host_mem_usage 382720 # Number of bytes of host memory used +host_seconds 63.69 # Real time elapsed on the host sim_insts 61477134 # Number of instructions simulated sim_ops 78349023 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -89,20 +89,20 @@ system.physmem.bw_total::cpu1.inst 267624 # To system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 69267 # number of replacements -system.l2c.tagsinuse 52917.687187 # Cycle average of tags in use +system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use system.l2c.total_refs 1645693 # Total number of references to valid blocks. system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40124.661939 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3720.854168 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4213.259552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2800.295642 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2055.865658 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -189,40 +189,40 @@ system.l2c.overall_misses::cpu1.data 75979 # nu system.l2c.overall_misses::total 161841 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 298918500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 409688500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 298939500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 409670500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 263122000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 189491500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1161637500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 30055000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 27347000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 57402000 # number of UpgradeReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 263172000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 189494500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1161693500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 30053000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 27343000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 57396000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6038000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 9730000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3494564965 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3764669994 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7259234959 # number of ReadExReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6036000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 9728000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3494513965 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3764719994 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7259233959 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 298918500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3904253465 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 298939500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3904184465 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 52500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 263122000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3954161494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8420872459 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 263172000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3954214494 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8420927459 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 298918500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3904253465 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 298939500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3904184465 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 52500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 263122000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3954161494 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8420872459 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 263172000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3954214494 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8420927459 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 4115 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 1843 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 408051 # number of ReadReq accesses(hits+misses) @@ -299,40 +299,40 @@ system.l2c.overall_miss_rate::cpu1.data 0.278223 # mi system.l2c.overall_miss_rate::total 0.108804 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52040.128830 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52030.543561 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52043.784819 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52028.257557 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52175.689074 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52072.410003 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52072.686928 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6389.243197 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7630.301339 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6925.916988 # average UpgradeReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52185.603807 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52073.234405 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52075.197239 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6388.818027 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7629.185268 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6925.193050 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6488.576450 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12449.484536 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 9231.499051 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.872323 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52041.332513 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52025.219547 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 199056017497 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses @@ -472,40 +472,40 @@ system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40030.226060 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # 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Number of load instructions system.cpu0.num_store_insts 5990651 # Number of store instructions -system.cpu0.num_idle_cycles 2267023722.330122 # Number of idle cycles -system.cpu0.num_busy_cycles 147557531.669878 # Number of busy cycles +system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles +system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -613,12 +613,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 408647 # system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses system.cpu0.icache.overall_misses::total 408647 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096214000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6096214000 # 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number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses @@ -631,12 +631,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.044180 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.044180 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14918.044180 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14918.044180 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -651,12 +651,12 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869428500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869428500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869428500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4869428500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869428500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4869428500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles @@ -667,24 +667,24 @@ system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11915.977604 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 330734 # number of replacements -system.cpu0.dcache.tagsinuse 459.649704 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 459.649704 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits @@ -711,18 +711,18 @@ system.cpu0.dcache.demand_misses::cpu0.data 369775 # system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses system.cpu0.dcache.overall_misses::total 369775 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443053000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3443053000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918745500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4918745500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100903000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 100903000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74598000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 74598000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8361798500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8361798500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8361798500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8361798500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443058000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3443058000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918727500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4918727500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100897000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100897000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74611000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 74611000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8361785500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8361785500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8361785500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8361785500 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) @@ -747,18 +747,18 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.600119 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.600119 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34707.000325 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34707.000325 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.697051 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.697051 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9950.380152 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9950.380152 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22613.206680 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22613.206680 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9952.114179 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9952.114179 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,26 +781,26 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758299641 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758299641 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493384071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493384071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72902006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72902006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52119015 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52119015 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251683712 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7251683712 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251683712 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7251683712 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559859000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559859000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253198500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253198500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813057500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses @@ -813,20 +813,20 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12094.993887 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12094.993887 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.621364 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.621364 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.909491 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.909491 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6959.409133 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6959.409133 # average StoreCondReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -894,8 +894,8 @@ system.cpu1.num_fp_register_writes 2260 # nu system.cpu1.num_mem_refs 14689113 # number of memory refs system.cpu1.num_load_insts 8640454 # Number of load instructions system.cpu1.num_store_insts 6048659 # Number of store instructions -system.cpu1.num_idle_cycles 1863361909.381196 # Number of idle cycles -system.cpu1.num_busy_cycles 549721128.618804 # Number of busy cycles +system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles +system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -921,12 +921,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 455583 # system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses system.cpu1.icache.overall_misses::total 455583 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728267000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6728267000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6728267000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6728267000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6728267000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6728267000 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses @@ -939,12 +939,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.476875 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.476875 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14768.476875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14768.476875 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -959,12 +959,12 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360614000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360614000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360614000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5360614000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360614000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5360614000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles @@ -975,24 +975,24 @@ system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.492604 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 292605 # number of replacements -system.cpu1.dcache.tagsinuse 473.034253 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 473.034237 # Cycle average of tags in use system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 473.034253 # Average occupied blocks per requestor +system.cpu1.dcache.occ_blocks::cpu1.data 473.034237 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits @@ -1019,18 +1019,18 @@ system.cpu1.dcache.demand_misses::cpu1.data 321159 # system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses system.cpu1.dcache.overall_misses::total 321159 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374183000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2374183000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137653000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5137653000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106350500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 106350500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87844000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 87844000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 7511836000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7511836000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 7511836000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7511836000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374362000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2374362000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137708000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5137708000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106370500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 106370500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87843000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 87843000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7512070000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7512070000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7512070000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7512070000 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses) @@ -1055,18 +1055,18 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13885.085503 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13885.085503 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.018299 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.018299 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9563.033900 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9563.033900 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.411987 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.411987 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23389.772667 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23389.772667 # average overall miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9564.832299 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9564.832299 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.312760 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.312760 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1089,24 +1089,24 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860610613 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860610613 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686894192 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686894192 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72963005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72963005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57623011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57623011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547504805 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6547504805 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547504805 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6547504805 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686172000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686172000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932194000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932194000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618366000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses @@ -1119,18 +1119,18 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10881.527435 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10881.527435 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.381445 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.381445 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6560.831310 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6560.831310 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.245382 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.245382 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1152,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574301885796 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 574301885796 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574301885796 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 574301885796 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 5fafbec2b..1b5c0ec90 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196043 # Number of seconds simulated -sim_ticks 5196043137000 # Number of ticks simulated -final_tick 5196043137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196023 # Number of seconds simulated +sim_ticks 5196022575000 # Number of ticks simulated +final_tick 5196022575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 682761 # Simulator instruction rate (inst/s) -host_op_rate 1316197 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27664981075 # Simulator tick rate (ticks/s) -host_mem_usage 397336 # Number of bytes of host memory used -host_seconds 187.82 # Real time elapsed on the host -sim_insts 128236332 # Number of instructions simulated -sim_ops 247208442 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2881344 # Number of bytes read from this memory +host_inst_rate 1315892 # Simulator instruction rate (inst/s) +host_op_rate 2536713 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53344387183 # Simulator tick rate (ticks/s) +host_mem_usage 354072 # Number of bytes of host memory used +host_seconds 97.41 # Real time elapsed on the host +sim_insts 128174734 # Number of instructions simulated +sim_ops 247089109 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2880320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 824320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8950528 # Number of bytes read from this memory -system.physmem.bytes_read::total 12656512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 824320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 824320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8081152 # Number of bytes written to this memory -system.physmem.bytes_written::total 8081152 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45021 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 824192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8956288 # Number of bytes read from this memory +system.physmem.bytes_read::total 12661120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8085888 # Number of bytes written to this memory +system.physmem.bytes_written::total 8085888 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 45005 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12880 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139852 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197758 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126268 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126268 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 554527 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12878 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139942 # Number of read requests responded to by this memory +system.physmem.num_reads::total 197830 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126342 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126342 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 554332 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1722566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2435798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158644 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158644 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1555251 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1555251 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1555251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 554527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1723682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2436695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1556169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1556169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1556169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 554332 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1722566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3991049 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 86291 # number of replacements -system.l2c.tagsinuse 64759.780052 # Cycle average of tags in use -system.l2c.total_refs 3494113 # Total number of references to valid blocks. -system.l2c.sampled_refs 150981 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.142733 # Average number of references to valid blocks. +system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 86330 # number of replacements +system.l2c.tagsinuse 64759.737076 # Cycle average of tags in use +system.l2c.total_refs 3491284 # Total number of references to valid blocks. +system.l2c.sampled_refs 151054 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.112821 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50071.847750 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.141309 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3396.359734 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11291.431260 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.764036 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051824 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.172294 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.988156 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6458 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 2811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 779608 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1280721 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2069598 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1543757 # number of Writeback hits -system.l2c.Writeback_hits::total 1543757 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 305 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 200867 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 200867 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6458 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 2811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 779608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1481588 # number of demand (read+write) hits -system.l2c.demand_hits::total 2270465 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6458 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 2811 # number of overall hits -system.l2c.overall_hits::cpu.inst 779608 # number of overall hits -system.l2c.overall_hits::cpu.data 1481588 # number of overall hits -system.l2c.overall_hits::total 2270465 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.988155 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2068208 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1543462 # number of Writeback hits +system.l2c.Writeback_hits::total 1543462 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 302 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 200678 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 778172 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1481001 # number of demand (read+write) hits +system.l2c.demand_hits::total 2268886 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 6719 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 2994 # number of overall hits +system.l2c.overall_hits::cpu.inst 778172 # number of overall hits +system.l2c.overall_hits::cpu.data 1481001 # number of overall hits +system.l2c.overall_hits::total 2268886 # number of overall hits system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12881 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 28319 # number of ReadReq misses -system.l2c.ReadReq_misses::total 41205 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1371 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1371 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 112462 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 112462 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 28353 # number of ReadReq misses +system.l2c.ReadReq_misses::total 41237 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1338 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 112514 # number of ReadExReq misses system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12881 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 140781 # number of demand (read+write) misses -system.l2c.demand_misses::total 153667 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 12879 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 140867 # number of demand (read+write) misses +system.l2c.demand_misses::total 153751 # number of demand (read+write) misses system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu.inst 12881 # number of overall misses -system.l2c.overall_misses::cpu.data 140781 # number of overall misses -system.l2c.overall_misses::total 153667 # number of overall misses +system.l2c.overall_misses::cpu.inst 12879 # number of overall misses +system.l2c.overall_misses::cpu.data 140867 # number of overall misses +system.l2c.overall_misses::total 153751 # number of overall misses system.l2c.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 670242000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1486972500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2157474500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 34071000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 34071000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 5850445000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5850445000 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 670242000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7337417500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8007919500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8011639500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 670242000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7337417500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8007919500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 6458 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 2816 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 792489 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1309040 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2110803 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1543757 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1543757 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1676 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1676 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 313329 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313329 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 6458 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 2816 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 792489 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1622369 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2424132 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 6458 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 2816 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 792489 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1622369 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2424132 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001776 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016254 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.021633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.019521 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.818019 # 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number of overall miss cycles +system.l2c.overall_miss_latency::total 8011639500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 6719 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 2999 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 791051 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 313192 # 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number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 88423590000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021633 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.019521 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818019 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.818019 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.358926 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.358926 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016254 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40032.683798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.786292 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40359.203980 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40283.734500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40283.734500 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40021.500596 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40021.500596 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -251,14 +251,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47503 # number of replacements -system.iocache.tagsinuse 0.108785 # Cycle average of tags in use +system.iocache.tagsinuse 0.108744 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.108785 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006799 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006799 # Average percentage of cache occupancy +system.iocache.occ_blocks::pc.south_bridge.ide 0.108744 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006796 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006796 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses system.iocache.ReadReq_misses::total 838 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -267,14 +267,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128838932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 128838932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 7147789160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7147789160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 7276628092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7276628092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 7276628092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7276628092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129993932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 129993932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10714208160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10714208160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10844202092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10844202092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10844202092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10844202092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -291,19 +291,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153745.742243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 153745.742243 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 152992.062500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 152992.062500 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 153005.342781 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 153005.342781 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 372008 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155124.023866 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155124.023866 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229328.085616 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229328.085616 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228020.566298 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228020.566298 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 89624012 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 38 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10977 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9789.684211 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8164.709119 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -317,14 +317,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 85232000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 85232000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4718093984 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4718093984 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4803325984 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4803325984 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86387000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86387000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8284511992 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8284511992 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8370898992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8370898992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -333,14 +333,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101708.830549 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 101708.830549 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 100986.600685 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 100986.600685 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103087.112172 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 103087.112172 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177322.602568 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177322.602568 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -354,75 +354,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10392086274 # number of cpu cycles simulated +system.cpu.numCycles 10392045150 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128236332 # Number of instructions committed -system.cpu.committedOps 247208442 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231946757 # Number of integer alu accesses +system.cpu.committedInsts 128174734 # Number of instructions committed +system.cpu.committedOps 247089109 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231827885 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23151326 # number of instructions that are conditional controls -system.cpu.num_int_insts 231946757 # number of integer instructions +system.cpu.num_conditional_control_insts 23138722 # number of instructions that are conditional controls +system.cpu.num_int_insts 231827885 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566912178 # number of times the integer registers were read -system.cpu.num_int_register_writes 293147449 # number of times the integer registers were written +system.cpu.num_int_register_reads 566609561 # number of times the integer registers were read +system.cpu.num_int_register_writes 292994515 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22230275 # number of memory refs -system.cpu.num_load_insts 13869948 # Number of load instructions -system.cpu.num_store_insts 8360327 # Number of store instructions -system.cpu.num_idle_cycles 9776409858.670118 # Number of idle cycles -system.cpu.num_busy_cycles 615676415.329882 # Number of busy cycles -system.cpu.not_idle_fraction 0.059245 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.940755 # Percentage of idle cycles +system.cpu.num_mem_refs 22210252 # number of memory refs +system.cpu.num_load_insts 13855140 # Number of load instructions +system.cpu.num_store_insts 8355112 # Number of store instructions +system.cpu.num_idle_cycles 9776628704.958118 # Number of idle cycles +system.cpu.num_busy_cycles 615416445.041882 # Number of busy cycles +system.cpu.not_idle_fraction 0.059220 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940780 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 791983 # number of replacements -system.cpu.icache.tagsinuse 510.339207 # Cycle average of tags in use -system.cpu.icache.total_refs 144447737 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 792495 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.269588 # Average number of references to valid blocks. +system.cpu.icache.replacements 790545 # number of replacements +system.cpu.icache.tagsinuse 510.338891 # Cycle average of tags in use +system.cpu.icache.total_refs 144363546 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791057 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.494493 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.339207 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.338891 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144447737 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144447737 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144447737 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144447737 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144447737 # number of overall hits -system.cpu.icache.overall_hits::total 144447737 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792502 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792502 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792502 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792502 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792502 # number of overall misses -system.cpu.icache.overall_misses::total 792502 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11813272500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11813272500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11813272500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11813272500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11813272500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11813272500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145240239 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145240239 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145240239 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145240239 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145240239 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145240239 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005456 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005456 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005456 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005456 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005456 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005456 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14906.299921 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14906.299921 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14906.299921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14906.299921 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 144363546 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144363546 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144363546 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144363546 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144363546 # number of overall hits +system.cpu.icache.overall_hits::total 144363546 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791064 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791064 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791064 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791064 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791064 # number of overall misses +system.cpu.icache.overall_misses::total 791064 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11792673000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11792673000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11792673000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11792673000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11792673000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11792673000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145154610 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145154610 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145154610 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145154610 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145154610 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145154610 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005450 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005450 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005450 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005450 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005450 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005450 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14907.356421 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14907.356421 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14907.356421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14907.356421 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,80 +431,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792502 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 792502 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 792502 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 792502 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 792502 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 792502 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9434751000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9434751000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9434751000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9434751000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9434751000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9434751000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005456 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005456 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005456 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11905.018536 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11905.018536 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791064 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791064 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791064 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791064 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791064 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791064 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9418462000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9418462000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9418462000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9418462000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9418462000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9418462000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005450 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005450 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005450 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11906.068283 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11906.068283 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3538 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.068811 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7893 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3550 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.223380 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5169410055000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.068811 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191801 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191801 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7916 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7916 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3550 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.065778 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7809 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3562 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.192308 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5171078849000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.065778 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191611 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191611 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7809 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7809 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7918 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7918 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7918 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7918 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4398 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4398 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4398 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4398 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4398 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4398 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51351000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51351000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51351000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 51351000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51351000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 51351000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12314 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12314 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7811 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7811 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7811 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7811 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4415 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4415 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4415 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4415 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4415 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4415 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 53239000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 53239000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 53239000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 53239000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 53239000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 53239000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12316 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12316 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12316 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12316 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.357154 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.357154 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.357096 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.357096 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.357096 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.357096 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11675.989086 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11675.989086 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11675.989086 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11675.989086 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361175 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361175 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361116 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.361116 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361116 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.361116 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12058.663647 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12058.663647 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12058.663647 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,78 +513,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 656 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 656 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4398 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4398 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4398 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4398 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4398 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4398 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38157000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38157000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38157000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38157000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38157000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38157000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.357154 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.357154 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.357096 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.357096 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8675.989086 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 830 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 830 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4415 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4415 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4415 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4415 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4415 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4415 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39994000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39994000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39994000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39994000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39994000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39994000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361175 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361175 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361116 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361116 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9058.663647 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7615 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.050606 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13416 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7630 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.758322 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5165509990000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.050606 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315663 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315663 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13416 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13416 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13416 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13416 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13416 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13416 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8830 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8830 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8830 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8830 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8830 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8830 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 114790500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 114790500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 114790500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 114790500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 114790500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 114790500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22246 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22246 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22246 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22246 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22246 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22246 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.396925 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.396925 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.396925 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.396925 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.396925 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.396925 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13000.056625 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13000.056625 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13000.056625 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13000.056625 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7810 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.052392 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12921 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7826 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.651035 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5166488673000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052392 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315774 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315774 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12921 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12921 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12921 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12921 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12921 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12921 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9010 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9010 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9010 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9010 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9010 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9010 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 118862500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 118862500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 118862500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 118862500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 118862500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 118862500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21931 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21931 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21931 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21931 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21931 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21931 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.410834 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.410834 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.410834 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.410834 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.410834 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.410834 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13192.286349 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13192.286349 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13192.286349 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,90 +593,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3005 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3005 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8830 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8830 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8830 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8830 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8830 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8830 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88300000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88300000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88300000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88300000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88300000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88300000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.396925 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.396925 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.396925 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10000 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3142 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3142 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9010 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9010 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9010 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9010 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9010 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9010 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 91832000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 91832000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 91832000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 91832000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 91832000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 91832000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.410834 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.410834 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.410834 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10192.230855 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1622589 # number of replacements -system.cpu.dcache.tagsinuse 511.997330 # Cycle average of tags in use -system.cpu.dcache.total_refs 20023565 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1623101 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.336611 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1622132 # number of replacements +system.cpu.dcache.tagsinuse 511.997396 # Cycle average of tags in use +system.cpu.dcache.total_refs 20004026 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622644 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.328044 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997330 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997396 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11986605 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11986605 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8034775 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8034775 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20021380 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20021380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20021380 # number of overall hits -system.cpu.dcache.overall_hits::total 20021380 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1309816 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1309816 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315519 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315519 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1625335 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1625335 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1625335 # number of overall misses -system.cpu.dcache.overall_misses::total 1625335 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19889195500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19889195500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9348149500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9348149500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29237345000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29237345000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29237345000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29237345000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13296421 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13296421 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21646715 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21646715 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21646715 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21646715 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098509 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098509 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037785 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037785 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075085 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075085 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075085 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075085 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15184.724801 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15184.724801 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29627.849670 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29627.849670 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17988.503908 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17988.503908 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11972131 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11972131 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8029723 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8029723 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20001854 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20001854 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20001854 # number of overall hits +system.cpu.dcache.overall_hits::total 20001854 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1309489 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1309489 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315369 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315369 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624858 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624858 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624858 # number of overall misses +system.cpu.dcache.overall_misses::total 1624858 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19885711500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19885711500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9346101000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9346101000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29231812500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29231812500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29231812500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29231812500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13281620 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13281620 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8345092 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8345092 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21626712 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21626712 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21626712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21626712 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098594 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098594 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037791 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037791 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.075132 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075132 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075132 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075132 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15185.856086 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15185.856086 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29635.446096 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29635.446096 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17990.379775 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17990.379775 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,46 +685,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1540096 # number of writebacks -system.cpu.dcache.writebacks::total 1540096 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309816 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1309816 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315519 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315519 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1625335 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1625335 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625335 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625335 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15959698500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15959698500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401590001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401590001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24361288501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24361288501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24361288501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24361288501 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1539490 # number of writebacks +system.cpu.dcache.writebacks::total 1539490 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309489 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1309489 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315369 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315369 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1624858 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1624858 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1624858 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1624858 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15957199501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15957199501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8399992000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8399992000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24357191501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24357191501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24357191501 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24357191501 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 93628676500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 93628676500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467826500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467826500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096503000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096503000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098509 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098509 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037785 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037785 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075085 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075085 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12184.687391 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12184.687391 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26627.841750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26627.841750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467841500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467841500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096518000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096518000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098594 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098594 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037791 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037791 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075132 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.075132 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075132 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.075132 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12185.821722 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12185.821722 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26635.439755 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26635.439755 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14990.350850 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14990.350850 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14990.350850 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14990.350850 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 076c105ad..9e326e98d 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.019665 # Number of seconds simulated -sim_ticks 19665440 # Number of ticks simulated -final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.006104 # Number of seconds simulated +sim_ticks 6103915 # Number of ticks simulated +final_tick 6103915 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 178903 # Simulator tick rate (ticks/s) -host_mem_usage 378856 # Number of bytes of host memory used -host_seconds 109.92 # Real time elapsed on the host +host_tick_rate 78453 # Simulator tick rate (ticks/s) +host_mem_usage 374396 # Number of bytes of host memory used +host_seconds 77.80 # Real time elapsed on the host system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 99534 # number of read accesses completed -system.cpu0.num_writes 53920 # number of write accesses completed +system.cpu0.num_reads 99027 # number of read accesses completed +system.cpu0.num_writes 53493 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99604 # number of read accesses completed -system.cpu1.num_writes 53779 # number of write accesses completed +system.cpu1.num_reads 98254 # number of read accesses completed +system.cpu1.num_writes 52787 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99103 # number of read accesses completed -system.cpu2.num_writes 53314 # number of write accesses completed +system.cpu2.num_reads 99047 # number of read accesses completed +system.cpu2.num_writes 53306 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99223 # number of read accesses completed -system.cpu3.num_writes 53188 # number of write accesses completed +system.cpu3.num_reads 98414 # number of read accesses completed +system.cpu3.num_writes 53420 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53373 # number of write accesses completed +system.cpu4.num_writes 53741 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99316 # number of read accesses completed -system.cpu5.num_writes 53693 # number of write accesses completed +system.cpu5.num_reads 98111 # number of read accesses completed +system.cpu5.num_writes 53002 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99832 # number of read accesses completed -system.cpu6.num_writes 53341 # number of write accesses completed +system.cpu6.num_reads 99154 # number of read accesses completed +system.cpu6.num_writes 52587 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99257 # number of read accesses completed -system.cpu7.num_writes 53656 # number of write accesses completed +system.cpu7.num_reads 99215 # number of read accesses completed +system.cpu7.num_writes 53364 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 1fe48d0c8..0a33e618b 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,640 +1,634 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000224 # Number of seconds simulated -sim_ticks 223713460 # Number of ticks simulated -final_tick 223713460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000247 # Number of seconds simulated +sim_ticks 246648467 # Number of ticks simulated +final_tick 246648467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1721618 # Simulator tick rate (ticks/s) -host_mem_usage 347508 # Number of bytes of host memory used -host_seconds 129.94 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 81065 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82807 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 84800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 80115 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 83878 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 83050 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 84723 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 83101 # Number of bytes read from this memory -system.physmem.bytes_read::total 663539 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 423360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5290 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5393 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5404 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5324 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5344 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5398 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5445 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5412 # Number of bytes written to this memory -system.physmem.bytes_written::total 466370 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11135 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11176 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11041 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11139 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11029 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88727 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6615 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5290 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5393 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5404 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5324 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5344 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5398 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5445 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5412 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49625 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 362360852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 370147599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 379056316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 358114349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 374934973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 371233810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 378712126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 371461780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2966021803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1892420778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 23646320 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 24106730 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 24155900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 23798300 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 23887700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 24129080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 24339170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 24191660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2084675638 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1892420778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 386007172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 394254329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 403212216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 381912648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 398822673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 395362890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 403051296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 395653440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5050697441 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 13635 # number of replacements -system.l2c.tagsinuse 790.382632 # Cycle average of tags in use -system.l2c.total_refs 148986 # Total number of references to valid blocks. -system.l2c.sampled_refs 14447 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.312591 # Average number of references to valid blocks. +host_tick_rate 1526116 # Simulator tick rate (ticks/s) +host_mem_usage 347672 # Number of bytes of host memory used +host_seconds 161.62 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 85584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 85024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 83876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80921 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79699 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 87892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 84658 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 85643 # Number of bytes read from this memory +system.physmem.bytes_read::total 673297 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 432320 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5346 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5458 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5415 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5191 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5426 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5272 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5284 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5390 # Number of bytes written to this memory +system.physmem.bytes_written::total 475102 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11251 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11158 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10988 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88405 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6755 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5346 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5458 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5415 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5191 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5272 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5284 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5390 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49537 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 346987764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 344717326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 340062929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 328082315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 323127895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 356345211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 343233433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 347226971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2729783843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1752777973 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 21674572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 22128660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 21954323 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 21046147 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 21998920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 21374550 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 21423202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 21852964 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1926231311 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1752777973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 368662336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 366845986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 362017251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 349128462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 345126816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 377719761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 364656635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 369079934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4656015154 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 13761 # number of replacements +system.l2c.tagsinuse 783.393170 # Cycle average of tags in use +system.l2c.total_refs 148641 # Total number of references to valid blocks. +system.l2c.sampled_refs 14595 # Sample count of references to valid blocks. +system.l2c.avg_refs 10.184378 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 735.582494 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 6.455373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 6.652747 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 6.865494 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 6.639169 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.152690 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.266868 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 7.044725 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 6.723074 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.718342 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.006304 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.006497 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.006705 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.006484 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.006985 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.007097 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.006880 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.006566 # 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number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 366 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 372 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 359 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 320 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2793 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1921 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1802 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1826 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1884 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1935 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1883 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1847 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15016 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12657 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12416 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12424 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12523 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12437 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12615 # number of demand (read+write) hits -system.l2c.demand_hits::total 100313 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12657 # number of overall hits -system.l2c.overall_hits::cpu1 12416 # number of overall hits -system.l2c.overall_hits::cpu2 12424 # number of overall hits -system.l2c.overall_hits::cpu3 12574 # number of overall hits -system.l2c.overall_hits::cpu4 12523 # number of overall hits -system.l2c.overall_hits::cpu5 12437 # number of overall hits -system.l2c.overall_hits::cpu6 12667 # number of overall hits -system.l2c.overall_hits::cpu7 12615 # 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number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1917 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1898 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15600 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4348 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4389 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4257 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4320 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4350 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4337 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4234 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4290 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34525 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5080 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5135 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5056 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5129 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5105 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5036 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5046 # number of demand (read+write) misses -system.l2c.demand_misses::total 40631 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5080 # number of overall misses -system.l2c.overall_misses::cpu1 5135 # number of overall misses -system.l2c.overall_misses::cpu2 5044 # number of overall misses -system.l2c.overall_misses::cpu3 5056 # number of overall misses -system.l2c.overall_misses::cpu4 5129 # number of overall misses -system.l2c.overall_misses::cpu5 5105 # number of overall misses -system.l2c.overall_misses::cpu6 5036 # number of overall misses -system.l2c.overall_misses::cpu7 5046 # number of overall misses -system.l2c.overall_misses::total 40631 # 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number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 51434616 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 55447032 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 51075446 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 51050152 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 422536610 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 217343370 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 219324999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 212745239 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 215838098 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 217293309 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 216702467 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 211504918 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 214216755 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1724969155 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 253525671 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 256420181 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 251585151 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 252158550 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 255947766 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 254683944 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 251418591 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 251636922 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2027376776 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 253525671 # 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number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2276 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2218 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18393 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6269 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6191 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6083 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6238 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6234 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6272 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6117 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6137 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 49541 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17737 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17551 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17468 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17652 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17542 # number of demand (read+write) accesses +system.l2c.occ_blocks::writebacks 713.127960 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 9.028795 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 9.232836 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 8.886797 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 8.220590 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 8.019568 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 9.223605 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 8.901601 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 8.751418 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.696414 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.008817 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.009016 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.008679 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.008028 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007832 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.009007 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.008693 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.008546 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.765032 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10550 # 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number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 329 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 315 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2713 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1919 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1876 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1912 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1869 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1927 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1872 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1860 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1792 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15027 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12469 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12512 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12514 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12700 # 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number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2221 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2217 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17792 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6318 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6062 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6256 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6098 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6213 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6254 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6254 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6215 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 49670 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17644 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17486 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17622 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17663 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17400 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17853 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu6 17703 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17661 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 140944 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17737 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17551 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17468 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17652 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17542 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu7 17644 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 141015 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17644 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17486 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17622 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17663 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17400 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17853 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu6 17703 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17661 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 140944 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.063830 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.065669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.069126 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.064607 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.068226 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.068146 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.069221 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.065602 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.066803 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.842968 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.853486 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.856229 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.851128 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.839965 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.843697 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.842267 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.855726 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.848149 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.693572 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.708932 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.699819 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.692530 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.697786 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.691486 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.692169 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.699039 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.696898 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.286407 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.292576 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.288757 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.286784 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.290562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.291016 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.284472 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.285714 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.288278 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.286407 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.292576 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.288757 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.286784 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.290562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.291016 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.284472 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.285714 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.288278 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 49429.372951 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 49725.445040 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 49351.857687 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 49348.440217 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 49620.612323 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 49455.048177 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 49767.672070 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 49497.575397 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 49526.305437 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 26392.335722 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 27313.714581 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 27448.613852 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 27559.738909 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 26774.917231 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 27613.063745 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 26643.425143 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 26896.813488 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 27085.680128 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 49986.975621 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 49971.519481 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 49975.390886 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 49962.522685 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 49952.484828 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 49965.982707 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 49953.924894 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 49933.975524 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 49962.900941 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 49906.628150 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 49935.770399 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 49878.102895 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 49873.130934 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 49902.079548 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 49889.117336 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 49924.263503 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 49868.593341 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 49897.289656 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 49906.628150 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 49935.770399 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 49878.102895 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 49873.130934 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 49902.079548 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 49889.117336 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 49924.263503 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 49868.593341 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 49897.289656 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 96627 # number of cycles access was blocked +system.l2c.overall_accesses::cpu7 17644 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 141015 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.068515 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.068978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.067218 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.063467 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.061947 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.069834 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.068827 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.068510 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.067174 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.835566 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.842034 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.847985 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.843034 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.844707 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.856886 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.851869 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.857916 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.847516 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.696265 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.690531 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.694373 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.693506 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.689844 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.700672 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.702590 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.711665 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.697463 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.293301 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.284456 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.289865 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.280983 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.286149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.290819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.292719 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.295058 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.289182 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.293301 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.284456 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.289865 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.280983 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.286149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.290819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.292719 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.295058 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.289182 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 86231.025773 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 85145.951777 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 94192.870419 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 92374.168937 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 90191.591631 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 86165.683951 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 91335.139594 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 91126.856960 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 89536.778846 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28982.305141 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 27889.094602 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 27838.458963 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27944.695607 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28436.838426 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28519.504188 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 27655.694503 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 27104.189274 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28042.781352 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55761.905888 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 56112.594840 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54720.659530 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55017.502956 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55707.019832 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 56195.756047 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54662.565316 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55564.234682 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55466.256473 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 60330.801932 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 60712.169682 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 60624.490603 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 60542.345356 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 60506.740309 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 60871.341872 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 60239.174450 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 60912.973300 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 60592.834498 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 60330.801932 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 60712.169682 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 60624.490603 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 60542.345356 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 60506.740309 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 60871.341872 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 60239.174450 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 60912.973300 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 60592.834498 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 751039 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 19 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 217 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5085.631579 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 3461.009217 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6616 # number of writebacks -system.l2c.writebacks::total 6616 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 23 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 19 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6755 # number of writebacks +system.l2c.writebacks::total 6755 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 14 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 16 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 143 # 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number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 11 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 10 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 15 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 85 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 24 # number of demand (read+write) MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 14 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 17 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 12 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 14 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 11 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 5 # 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number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 34 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 31 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 234 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 27 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 33 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 32 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 34 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 30 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 27 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 39 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 242 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 714 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 736 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 763 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 713 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 757 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 749 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 785 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 732 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5949 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1952 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1933 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2006 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1960 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1920 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2007 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1916 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1894 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15588 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4342 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4376 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4248 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4311 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4338 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4326 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4224 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4275 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34440 # 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number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 200450676 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 200970482 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 203729262 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 203009268 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 200330127 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 200249838 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1615440522 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 202250474 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 204450395 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 200450676 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 200970482 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 203729262 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 203009268 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 200330127 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 200249838 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1615440522 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 400927744 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 396406972 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 396807484 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 398767759 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 400808423 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 395927220 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 398767355 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 395367613 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3183780570 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 211603917 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 215684252 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 216163665 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 212923402 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 213723846 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 215924115 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 217803639 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 216444289 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1720271125 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 612531661 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 612091224 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 612971149 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 611691161 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 614532269 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 611851335 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 616570994 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 611811902 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4904051695 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.062260 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064789 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.067018 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.062588 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.066299 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.066460 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.067754 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063520 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.065085 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.842105 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.853045 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.855802 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.850694 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.839528 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.843277 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.841828 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853922 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.847496 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.692614 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.706832 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.698340 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.691087 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695861 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689732 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.690535 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696594 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.695182 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.286561 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.286561 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40006.658263 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40006.705163 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40008.418087 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40006.774194 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40005.966975 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40004.977303 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40006.179618 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 40006.371585 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.505631 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.579918 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39979.845835 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.600199 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.580612 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40000.623958 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39980.647733 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40000.517745 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.543823 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39995.438542 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40001.317365 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39992.106947 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 40001.001177 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40001.311065 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 39982.652144 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40001.280629 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 39991.779356 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.853567 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39995.407085 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu2 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 29 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 34 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 31 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 234 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 763 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 774 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 751 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 717 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 677 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 785 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 768 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 758 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5993 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1807 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1871 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1852 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1911 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1931 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1910 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1892 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1902 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15076 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4385 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4177 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4327 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4217 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4272 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4373 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4383 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4418 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34552 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5148 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 4951 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5078 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 4934 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 4949 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5151 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5176 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40545 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5148 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 4951 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5078 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 4934 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 4949 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5151 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5176 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40545 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 58870730 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 58585309 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 63480686 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 59975234 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 54977009 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 60150971 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 63201488 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 61933736 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 481175163 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 75210107 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78015248 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 77004240 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 79811462 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 80566647 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 79563303 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78963808 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 79283534 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 628418349 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 200402415 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 192724360 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 193590833 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189833874 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 195179728 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 201870094 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 195807052 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 201165400 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1570573756 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 259273145 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 251309669 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 257071519 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 249809108 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 250156737 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 262021065 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 259008540 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 263099136 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2051748919 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 259273145 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 251309669 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 257071519 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 249809108 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 250156737 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 262021065 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 259008540 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 263099136 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2051748919 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 422219130 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 432042675 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 419593939 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 421722054 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 422767760 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 422714984 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 423711086 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 417921325 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3382692953 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 236377012 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 240741589 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 239322336 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229099860 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 239042372 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 232239121 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 232671200 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 242872940 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1892366430 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 658596142 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 672784264 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 658916275 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 650821914 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 661810132 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 654954105 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 656382286 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 660794265 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5275059383 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.067367 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.067752 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.066074 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061997 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060517 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.067678 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.067080 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.066323 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.065608 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.834642 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.842034 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.847985 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.842593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.844707 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.856886 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.851869 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.857916 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.847347 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.694049 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689047 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.691656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.691538 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687591 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.699232 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.700831 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.710861 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.695631 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.291771 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.283141 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.288163 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.279341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284425 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.288915 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.290968 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.293358 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.287523 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.291771 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.283141 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.288163 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.279341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284425 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.288915 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.290968 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.293358 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.287523 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 77156.920052 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 75691.613695 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 84528.210386 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 83647.467225 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 81206.807976 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 76625.440764 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 82293.604167 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 81706.775726 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 80289.531620 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41621.531267 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41697.086050 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41578.963283 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41764.239665 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41722.758674 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41656.179581 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41735.627907 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41684.297581 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41683.360905 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45701.805017 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 46139.420637 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44740.197134 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 45016.332464 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45688.138577 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 46162.838783 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44674.207620 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45533.137166 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 45455.364552 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 50363.858780 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 50759.375682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 50624.560654 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 50630.139441 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 50546.926046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 50798.965684 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 50283.156669 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 50830.590417 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 50604.240202 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 50363.858780 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 50759.375682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 50624.560654 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 50630.139441 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 50546.926046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 50798.965684 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 50283.156669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 50830.590417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 50604.240202 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -663,114 +657,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 99016 # number of read accesses completed -system.cpu0.num_writes 53340 # number of write accesses completed +system.cpu0.num_reads 98266 # number of read accesses completed +system.cpu0.num_writes 53265 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 21906 # number of replacements -system.cpu0.l1c.tagsinuse 396.590239 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13140 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22312 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.588921 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 21972 # number of replacements +system.cpu0.l1c.tagsinuse 389.500163 # Cycle average of tags in use +system.cpu0.l1c.total_refs 12866 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22378 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.574940 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 396.590239 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.774590 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.774590 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8561 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8561 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1051 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1051 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9612 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9612 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9612 # number of overall hits -system.cpu0.l1c.overall_hits::total 9612 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35875 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35875 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23186 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23186 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 59061 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 59061 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 59061 # number of overall misses -system.cpu0.l1c.overall_misses::total 59061 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 894906998 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 894906998 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 820039819 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 820039819 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1714946817 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1714946817 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1714946817 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1714946817 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44436 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44436 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24237 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24237 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68673 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68673 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68673 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68673 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807341 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807341 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956637 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956637 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860032 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860032 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860032 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860032 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 24945.142801 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 24945.142801 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 35367.886613 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 35367.886613 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 29036.874029 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 29036.874029 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 29036.874029 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 29036.874029 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 154642800 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 389.500163 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.760743 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.760743 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8421 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8421 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1069 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1069 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9490 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9490 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9490 # number of overall hits +system.cpu0.l1c.overall_hits::total 9490 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35688 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35688 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23099 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23099 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 58787 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 58787 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 58787 # number of overall misses +system.cpu0.l1c.overall_misses::total 58787 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1012085750 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1012085750 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 897172564 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 897172564 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1909258314 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1909258314 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1909258314 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1909258314 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44109 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44109 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24168 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24168 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68277 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68277 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68277 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68277 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809087 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.809087 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955768 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955768 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861007 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861007 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861007 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861007 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 28359.273425 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 28359.273425 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38840.320533 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 38840.320533 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 32477.559903 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 32477.559903 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 32477.559903 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 32477.559903 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 171686674 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 53124 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 52409 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 2910.978089 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3275.900590 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9551 # number of writebacks -system.cpu0.l1c.writebacks::total 9551 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35875 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35875 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23186 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23186 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 59061 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 59061 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 59061 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 59061 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 858892486 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 858892486 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 796764078 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 796764078 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1655656564 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1655656564 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1655656564 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1655656564 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 681029068 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 681029068 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 670499371 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 670499371 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1351528439 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1351528439 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807341 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807341 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956637 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956637 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860032 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860032 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860032 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860032 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 23941.253965 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 23941.253965 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34364.016130 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34364.016130 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28032.992398 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28032.992398 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28032.992398 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28032.992398 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9624 # number of writebacks +system.cpu0.l1c.writebacks::total 9624 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35688 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35688 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23099 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23099 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 58787 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 58787 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 58787 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 58787 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 976260004 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 976260004 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 873984178 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 873984178 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1850244182 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1850244182 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1850244182 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1850244182 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 721713598 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 721713598 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 736436829 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 736436829 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1458150427 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1458150427 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809087 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809087 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955768 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955768 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861007 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861007 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861007 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861007 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 27355.413696 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 27355.413696 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37836.450842 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37836.450842 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 31473.696259 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 31473.696259 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 31473.696259 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 31473.696259 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -778,114 +772,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99689 # number of read accesses completed -system.cpu1.num_writes 53832 # number of write accesses completed +system.cpu1.num_reads 99239 # number of read accesses completed +system.cpu1.num_writes 53491 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21971 # number of replacements -system.cpu1.l1c.tagsinuse 397.434568 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13255 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22377 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.592349 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21775 # number of replacements +system.cpu1.l1c.tagsinuse 388.085808 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13330 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22170 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.601263 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 397.434568 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.776239 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.776239 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8630 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8630 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1103 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1103 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9733 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9733 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9733 # number of overall hits -system.cpu1.l1c.overall_hits::total 9733 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36139 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36139 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23155 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23155 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 59294 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 59294 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 59294 # number of overall misses -system.cpu1.l1c.overall_misses::total 59294 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 902705787 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 902705787 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 819450505 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 819450505 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1722156292 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1722156292 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1722156292 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1722156292 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44769 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44769 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24258 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24258 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 69027 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 69027 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 69027 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 69027 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807233 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807233 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954530 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954530 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.858997 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.858997 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.858997 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.858997 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 24978.715155 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 24978.715155 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 35389.786439 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 35389.786439 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 29044.360171 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 29044.360171 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 29044.360171 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 29044.360171 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 155390130 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 388.085808 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.757980 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.757980 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8854 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8854 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1044 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1044 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9898 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9898 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9898 # number of overall hits +system.cpu1.l1c.overall_hits::total 9898 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35763 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35763 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22917 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22917 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58680 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58680 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58680 # number of overall misses +system.cpu1.l1c.overall_misses::total 58680 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1015131417 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1015131417 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 886463982 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 886463982 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1901595399 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1901595399 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1901595399 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1901595399 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44617 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44617 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23961 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23961 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68578 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68578 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68578 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68578 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.801555 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.801555 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956429 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.956429 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.855668 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.855668 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.855668 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.855668 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 28384.962587 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 28384.962587 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38681.502029 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 38681.502029 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 32406.192894 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 32406.192894 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 32406.192894 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 32406.192894 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 173063141 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 53247 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 53052 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 2918.288918 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3262.141691 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9603 # number of writebacks -system.cpu1.l1c.writebacks::total 9603 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36139 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36139 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23155 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23155 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 59294 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 59294 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 59294 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 59294 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 866427236 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 866427236 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 796207895 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 796207895 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1662635131 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1662635131 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1662635131 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1662635131 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 674093801 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 674093801 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 675943433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 675943433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1350037234 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1350037234 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807233 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807233 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954530 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954530 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858997 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.858997 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858997 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.858997 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23974.853648 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23974.853648 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34386.002807 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34386.002807 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28040.529075 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28040.529075 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28040.529075 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28040.529075 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9480 # number of writebacks +system.cpu1.l1c.writebacks::total 9480 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22917 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22917 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58680 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58680 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58680 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58680 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 979228369 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 979228369 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 863458324 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 863458324 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1842686693 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1842686693 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1842686693 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1842686693 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 740677115 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 740677115 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 739780589 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 739780589 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1480457704 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1480457704 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.801555 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.801555 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956429 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956429 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.855668 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.855668 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.855668 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.855668 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 27381.046584 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 27381.046584 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37677.633373 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37677.633373 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 31402.295382 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 31402.295382 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 31402.295382 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 31402.295382 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -893,114 +887,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99864 # number of read accesses completed -system.cpu2.num_writes 53679 # number of write accesses completed +system.cpu2.num_reads 98639 # number of read accesses completed +system.cpu2.num_writes 53360 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22117 # number of replacements -system.cpu2.l1c.tagsinuse 397.846327 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13470 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22518 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.598188 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 21788 # number of replacements +system.cpu2.l1c.tagsinuse 389.777022 # Cycle average of tags in use +system.cpu2.l1c.total_refs 12892 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22192 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.580930 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 397.846327 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.777044 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.777044 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8720 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8720 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1090 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1090 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9810 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9810 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9810 # number of overall hits -system.cpu2.l1c.overall_hits::total 9810 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36026 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36026 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23186 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23186 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59212 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59212 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59212 # number of overall misses -system.cpu2.l1c.overall_misses::total 59212 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 899117648 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 899117648 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 813653609 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 813653609 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1712771257 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1712771257 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1712771257 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1712771257 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44746 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44746 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24276 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24276 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 69022 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 69022 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 69022 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 69022 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805122 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805122 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955100 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955100 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.857871 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.857871 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.857871 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.857871 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 24957.465386 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 24957.465386 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 35092.452730 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 35092.452730 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 28926.083513 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 28926.083513 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 28926.083513 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 28926.083513 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 153072251 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 389.777022 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.761283 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.761283 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8419 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8419 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1037 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1037 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9456 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9456 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9456 # number of overall hits +system.cpu2.l1c.overall_hits::total 9456 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 35792 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 35792 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22886 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22886 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 58678 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 58678 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 58678 # number of overall misses +system.cpu2.l1c.overall_misses::total 58678 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1023256428 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1023256428 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 895299843 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 895299843 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1918556271 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1918556271 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1918556271 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1918556271 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44211 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44211 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 23923 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 23923 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68134 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68134 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68134 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68134 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.809572 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.809572 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.956653 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.956653 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.861215 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.861215 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.861215 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.861215 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 28588.970384 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 28588.970384 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 39119.979158 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 39119.979158 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 32696.347370 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 32696.347370 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 32696.347370 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 32696.347370 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 172516137 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 52648 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 52707 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 2907.465640 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3273.116227 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9600 # number of writebacks -system.cpu2.l1c.writebacks::total 9600 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36026 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36026 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23186 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23186 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59212 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59212 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59212 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59212 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 862954550 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 862954550 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 790376865 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 790376865 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1653331415 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1653331415 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1653331415 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1653331415 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 676110998 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 676110998 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 681557695 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 681557695 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1357668693 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1357668693 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805122 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805122 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955100 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955100 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857871 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.857871 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857871 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.857871 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 23953.659857 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 23953.659857 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34088.538989 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34088.538989 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9481 # number of writebacks +system.cpu2.l1c.writebacks::total 9481 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22886 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22886 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 58678 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 58678 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 58678 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 58678 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 987321254 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 987321254 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 872322294 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 872322294 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1859643548 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1859643548 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1859643548 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1859643548 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 722326579 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 722326579 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 745926521 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 745926521 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1468253100 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1468253100 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.809572 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.809572 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.956653 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.956653 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.861215 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.861215 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861215 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.861215 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 27584.970217 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 27584.970217 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 38115.978939 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 38115.978939 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 31692.347183 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 31692.347183 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 31692.347183 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 31692.347183 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1008,114 +1002,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98954 # number of read accesses completed -system.cpu3.num_writes 53519 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 53214 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 21866 # number of replacements -system.cpu3.l1c.tagsinuse 395.683419 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13218 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22277 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.593347 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 22201 # number of replacements +system.cpu3.l1c.tagsinuse 390.202631 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13426 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22601 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.594045 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 395.683419 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.772819 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.772819 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8562 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8562 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1098 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9660 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9660 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9660 # number of overall hits -system.cpu3.l1c.overall_hits::total 9660 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35996 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35996 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23029 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23029 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59025 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59025 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59025 # number of overall misses -system.cpu3.l1c.overall_misses::total 59025 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 899058428 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 899058428 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 817455350 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 817455350 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1716513778 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1716513778 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1716513778 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1716513778 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44558 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44558 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24127 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24127 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68685 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68685 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68685 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68685 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807846 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807846 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954491 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954491 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859358 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859358 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859358 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859358 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 24976.620402 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 24976.620402 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 35496.780147 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 35496.780147 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 29081.131351 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 29081.131351 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 29081.131351 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 29081.131351 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 155038956 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 390.202631 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.762115 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.762115 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8779 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8779 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1080 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1080 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9859 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9859 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9859 # number of overall hits +system.cpu3.l1c.overall_hits::total 9859 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36255 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36255 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22971 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22971 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 59226 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 59226 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 59226 # number of overall misses +system.cpu3.l1c.overall_misses::total 59226 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1029467396 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1029467396 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 892890764 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 892890764 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1922358160 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1922358160 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1922358160 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1922358160 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45034 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45034 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24051 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24051 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 69085 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 69085 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 69085 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 69085 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805058 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805058 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955095 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955095 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.857292 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.857292 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.857292 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.857292 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 28395.184002 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 28395.184002 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38870.348004 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 38870.348004 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 32458.011009 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 32458.011009 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 32458.011009 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 32458.011009 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 173404945 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 53124 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 53526 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 2918.435283 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3239.639521 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9442 # number of writebacks -system.cpu3.l1c.writebacks::total 9442 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35996 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35996 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23029 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23029 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59025 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59025 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59025 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59025 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 862924447 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 862924447 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 794336234 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 794336234 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1657260681 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1657260681 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1657260681 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1657260681 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 680106792 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 680106792 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 674669668 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 674669668 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1354776460 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1354776460 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807846 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807846 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954491 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954491 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859358 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859358 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859358 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859358 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23972.787171 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23972.787171 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34492.866994 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34492.866994 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28077.266938 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28077.266938 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9609 # number of writebacks +system.cpu3.l1c.writebacks::total 9609 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36255 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36255 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22971 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22971 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 59226 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 59226 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 59226 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 59226 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 993072387 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 993072387 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 869829882 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 869829882 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1862902269 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1862902269 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1862902269 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1862902269 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 723358193 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 723358193 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 722023340 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 722023340 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1445381533 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1445381533 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805058 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805058 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955095 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955095 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857292 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.857292 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857292 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.857292 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 27391.322218 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 27391.322218 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37866.435157 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37866.435157 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 31454.129420 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 31454.129420 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 31454.129420 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 31454.129420 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1123,114 +1117,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99591 # number of read accesses completed -system.cpu4.num_writes 53646 # number of write accesses completed +system.cpu4.num_reads 98672 # number of read accesses completed +system.cpu4.num_writes 53449 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22293 # number of replacements -system.cpu4.l1c.tagsinuse 397.816545 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13327 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22684 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.587507 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 21899 # number of replacements +system.cpu4.l1c.tagsinuse 389.567143 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13162 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22307 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.590039 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 397.816545 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.776985 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.776985 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8743 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8743 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1036 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1036 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9779 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9779 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9779 # number of overall hits -system.cpu4.l1c.overall_hits::total 9779 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 35998 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 35998 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23232 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23232 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59230 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59230 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59230 # number of overall misses -system.cpu4.l1c.overall_misses::total 59230 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 899681935 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 899681935 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 816003996 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 816003996 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1715685931 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1715685931 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1715685931 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1715685931 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44741 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44741 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24268 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24268 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69009 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69009 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69009 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69009 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804586 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804586 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.957310 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.957310 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858294 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858294 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858294 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858294 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 24992.553336 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 24992.553336 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 35124.138946 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 35124.138946 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 28966.502296 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 28966.502296 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 28966.502296 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 28966.502296 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 154355931 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 389.567143 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.760873 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.760873 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8516 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8516 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1086 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1086 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9602 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9602 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9602 # number of overall hits +system.cpu4.l1c.overall_hits::total 9602 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 35797 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 35797 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23063 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23063 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 58860 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 58860 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 58860 # number of overall misses +system.cpu4.l1c.overall_misses::total 58860 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1014475710 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1014475710 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 905483061 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 905483061 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1919958771 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1919958771 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1919958771 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1919958771 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44313 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44313 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24149 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24149 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68462 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68462 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68462 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68462 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807822 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807822 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955029 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.955029 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859747 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859747 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859747 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859747 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 28339.685169 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 28339.685169 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 39261.286953 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 39261.286953 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 32619.075280 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 32619.075280 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 32619.075280 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 32619.075280 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 173090211 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 53171 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 52926 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 2903.009742 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3270.419284 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9702 # number of writebacks -system.cpu4.l1c.writebacks::total 9702 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35998 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 35998 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23232 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23232 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59230 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59230 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59230 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59230 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 863541936 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 863541936 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 792684079 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 792684079 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1656226015 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1656226015 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1656226015 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1656226015 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 681350371 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 681350371 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 669996228 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 669996228 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1351346599 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1351346599 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804586 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804586 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.957310 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.957310 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858294 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858294 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858294 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858294 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 23988.608700 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 23988.608700 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34120.354640 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34120.354640 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 27962.620547 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 27962.620547 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 27962.620547 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 27962.620547 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9537 # number of writebacks +system.cpu4.l1c.writebacks::total 9537 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35797 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 35797 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23063 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23063 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 58860 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 58860 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 58860 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 58860 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 978543547 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 978543547 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 882330817 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 882330817 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1860874364 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1860874364 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1860874364 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1860874364 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 726225983 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 726225983 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 739406150 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 739406150 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1465632133 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1465632133 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807822 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807822 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955029 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955029 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859747 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859747 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859747 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859747 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 27335.909350 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 27335.909350 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 38257.417378 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 38257.417378 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 31615.262725 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 31615.262725 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 31615.262725 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 31615.262725 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1238,114 +1232,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99523 # number of read accesses completed -system.cpu5.num_writes 53948 # number of write accesses completed +system.cpu5.num_reads 98938 # number of read accesses completed +system.cpu5.num_writes 52979 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22088 # number of replacements -system.cpu5.l1c.tagsinuse 397.555659 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13442 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22486 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.597794 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22003 # number of replacements +system.cpu5.l1c.tagsinuse 389.145531 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13186 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22409 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.588424 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 397.555659 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.776476 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.776476 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8700 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8700 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1066 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1066 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9766 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9766 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9766 # number of overall hits -system.cpu5.l1c.overall_hits::total 9766 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36016 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36016 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23333 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23333 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59349 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59349 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59349 # number of overall misses -system.cpu5.l1c.overall_misses::total 59349 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 899040098 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 899040098 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 826704780 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 826704780 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1725744878 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1725744878 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1725744878 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1725744878 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44716 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44716 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24399 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24399 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69115 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69115 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69115 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69115 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805439 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.805439 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956310 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.956310 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858699 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858699 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858699 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858699 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 24962.241726 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 24962.241726 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 35430.711010 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 35430.711010 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 29077.909956 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 29077.909956 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 29077.909956 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 29077.909956 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 155795508 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 389.145531 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.760050 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.760050 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1030 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1030 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9667 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9667 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9667 # number of overall hits +system.cpu5.l1c.overall_hits::total 9667 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36114 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36114 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22950 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22950 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59064 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59064 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59064 # number of overall misses +system.cpu5.l1c.overall_misses::total 59064 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1023713867 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1023713867 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 899864913 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 899864913 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1923578780 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1923578780 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1923578780 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1923578780 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44751 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44751 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 23980 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 23980 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68731 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68731 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68731 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68731 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806999 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806999 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.957048 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.957048 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859350 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859350 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859350 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859350 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 28346.731655 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 28346.731655 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 39209.800131 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 39209.800131 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 32567.702492 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 32567.702492 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 32567.702492 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 32567.702492 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 172870705 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 53352 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 53593 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 2920.143725 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3225.620977 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9610 # number of writebacks -system.cpu5.l1c.writebacks::total 9610 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36016 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36016 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23333 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23333 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59349 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59349 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59349 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59349 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 862885041 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 862885041 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 803284460 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 803284460 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1666169501 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1666169501 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1666169501 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1666169501 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 674425818 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 674425818 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 675374924 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 675374924 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1349800742 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1349800742 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805439 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805439 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956310 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956310 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858699 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858699 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858699 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858699 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 23958.380747 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 23958.380747 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 34426.968671 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 34426.968671 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28074.095621 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28074.095621 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28074.095621 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28074.095621 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9578 # number of writebacks +system.cpu5.l1c.writebacks::total 9578 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36114 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36114 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22950 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22950 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59064 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59064 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59064 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59064 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 987460421 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 987460421 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 876826122 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 876826122 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1864286543 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1864286543 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1864286543 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1864286543 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 726267830 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 726267830 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 727074165 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 727074165 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1453341995 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1453341995 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806999 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806999 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.957048 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.957048 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859350 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859350 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859350 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859350 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 27342.870383 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 27342.870383 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 38205.931242 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 38205.931242 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 31563.838260 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 31563.838260 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 31563.838260 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 31563.838260 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1353,114 +1347,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 53510 # number of write accesses completed +system.cpu6.num_reads 98714 # number of read accesses completed +system.cpu6.num_writes 53264 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 22177 # number of replacements -system.cpu6.l1c.tagsinuse 397.660479 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13364 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22573 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.592035 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 21950 # number of replacements +system.cpu6.l1c.tagsinuse 389.196991 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13256 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22357 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.592924 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 397.660479 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.776681 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.776681 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8760 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8760 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1035 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1035 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9795 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9795 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9795 # number of overall hits -system.cpu6.l1c.overall_hits::total 9795 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36279 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36279 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23033 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23033 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 59312 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 59312 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 59312 # number of overall misses -system.cpu6.l1c.overall_misses::total 59312 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 908517794 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 908517794 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 809582336 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 809582336 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1718100130 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1718100130 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1718100130 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1718100130 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45039 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45039 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24068 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24068 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 69107 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 69107 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 69107 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 69107 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805502 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805502 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956997 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.956997 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858263 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858263 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858263 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858263 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 25042.525814 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 25042.525814 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 35148.801111 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 35148.801111 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 28967.158922 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 28967.158922 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 28967.158922 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 28967.158922 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 154185284 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 389.196991 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.760150 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.760150 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8708 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8708 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1082 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1082 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9790 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9790 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9790 # number of overall hits +system.cpu6.l1c.overall_hits::total 9790 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35839 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35839 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23075 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23075 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58914 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58914 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58914 # number of overall misses +system.cpu6.l1c.overall_misses::total 58914 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1020128042 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1020128042 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 903798683 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 903798683 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1923926725 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1923926725 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1923926725 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1923926725 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44547 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44547 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24157 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24157 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68704 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68704 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68704 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68704 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804521 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.804521 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955210 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.955210 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.857505 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.857505 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.857505 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.857505 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 28464.188231 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 28464.188231 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 39167.873586 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 39167.873586 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 32656.528584 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 32656.528584 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 32656.528584 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 32656.528584 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 174295545 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 52977 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 53485 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 2910.419314 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3258.774329 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9564 # number of writebacks -system.cpu6.l1c.writebacks::total 9564 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36279 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36279 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23033 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 59312 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 59312 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 59312 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 59312 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 872097671 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 872097671 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 786461211 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 786461211 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1658558882 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1658558882 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1658558882 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1658558882 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 680107967 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 680107967 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 681972539 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 681972539 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1362080506 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1362080506 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805502 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805502 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956997 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956997 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858263 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858263 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858263 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858263 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24038.635878 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24038.635878 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34144.975079 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34144.975079 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 27963.293802 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 27963.293802 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 27963.293802 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 27963.293802 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9548 # number of writebacks +system.cpu6.l1c.writebacks::total 9548 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35839 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35839 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23075 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23075 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58914 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58914 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 984150696 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 984150696 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 880635396 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 880635396 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1864786092 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1864786092 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1864786092 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1864786092 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 725723754 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 725723754 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 729548625 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 729548625 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1455272379 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1455272379 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804521 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804521 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955210 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955210 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857505 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.857505 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857505 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.857505 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 27460.328023 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 27460.328023 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 38164.047497 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 38164.047497 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 31652.681739 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 31652.681739 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 31652.681739 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 31652.681739 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1468,114 +1462,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99201 # number of read accesses completed -system.cpu7.num_writes 53497 # number of write accesses completed +system.cpu7.num_reads 98633 # number of read accesses completed +system.cpu7.num_writes 53420 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22218 # number of replacements -system.cpu7.l1c.tagsinuse 396.828031 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13271 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22622 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.586641 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 21845 # number of replacements +system.cpu7.l1c.tagsinuse 390.265182 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13266 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22252 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.596171 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 396.828031 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.775055 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.775055 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8703 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8703 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1096 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1096 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9799 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9799 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9799 # number of overall hits -system.cpu7.l1c.overall_hits::total 9799 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36453 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36453 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 22910 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 22910 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59363 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59363 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59363 # number of overall misses -system.cpu7.l1c.overall_misses::total 59363 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 908883238 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 908883238 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 808946616 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 808946616 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1717829854 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1717829854 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1717829854 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1717829854 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45156 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45156 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24006 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24006 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69162 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69162 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69162 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69162 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807268 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807268 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954345 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954345 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858318 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858318 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858318 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858318 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 24933.016158 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 24933.016158 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 35309.760629 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 35309.760629 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 28937.719691 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 28937.719691 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 28937.719691 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 28937.719691 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 153732048 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 390.265182 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.762237 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.762237 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8641 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8641 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1118 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1118 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9759 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9759 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9759 # number of overall hits +system.cpu7.l1c.overall_hits::total 9759 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35823 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35823 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 22965 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 22965 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 58788 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 58788 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 58788 # number of overall misses +system.cpu7.l1c.overall_misses::total 58788 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1021778024 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1021778024 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 908326044 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 908326044 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1930104068 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1930104068 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1930104068 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1930104068 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44464 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44464 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24083 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24083 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68547 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68547 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68547 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68547 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805663 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805663 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953577 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953577 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857631 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857631 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857631 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857631 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 28522.960779 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 28522.960779 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 39552.625474 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 39552.625474 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 32831.599442 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 32831.599442 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 32831.599442 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 32831.599442 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 173409503 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 53029 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 52851 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 2899.018424 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3281.101644 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9581 # number of writebacks -system.cpu7.l1c.writebacks::total 9581 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36453 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36453 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22910 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22910 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59363 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59363 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59363 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59363 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 872289420 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 872289420 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 785947981 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 785947981 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1658237401 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1658237401 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1658237401 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1658237401 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 674384984 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 674384984 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 681937361 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 681937361 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1356322345 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1356322345 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807268 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807268 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954345 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954345 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858318 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858318 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858318 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858318 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23929.153156 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23929.153156 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34305.891794 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34305.891794 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 27933.854438 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 27933.854438 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9467 # number of writebacks +system.cpu7.l1c.writebacks::total 9467 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35823 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35823 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22965 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 58788 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 58788 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 58788 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 58788 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 985813733 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 985813733 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 885270188 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 885270188 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1871083921 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1871083921 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1871083921 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1871083921 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 719750432 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 719750432 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 746183664 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 746183664 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1465934096 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1465934096 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805663 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805663 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953577 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953577 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857631 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857631 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857631 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857631 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 27519.016637 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 27519.016637 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 38548.669192 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 38548.669192 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 31827.650558 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 31827.650558 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 31827.650558 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 31827.650558 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |