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authorNilay Vaish <nilay@cs.wisc.edu>2012-10-16 14:47:31 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2012-10-16 14:47:31 -0500
commitde3b3ed1403c7ff5be49951bfc32abfea42af6ec (patch)
tree342c62a3453e954f281a588218d250f95096dfb2 /tests
parentb6b5cde1321f1bd710463db8650b4485720e21bd (diff)
downloadgem5-de3b3ed1403c7ff5be49951bfc32abfea42af6ec.tar.xz
regressions: update stats for eio tests
Diffstat (limited to 'tests')
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt120
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt1198
2 files changed, 659 insertions, 659 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index c39a44a4e..9caac7258 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000730 # Number of seconds simulated
-sim_ticks 729729000 # Number of ticks simulated
-final_tick 729729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000727 # Number of seconds simulated
+sim_ticks 727072000 # Number of ticks simulated
+final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1176795 # Simulator instruction rate (inst/s)
-host_op_rate 1176746 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1717342738 # Simulator tick rate (ticks/s)
-host_mem_usage 221204 # Number of bytes of host memory used
-host_seconds 0.43 # Real time elapsed on the host
+host_inst_rate 1240024 # Simulator instruction rate (inst/s)
+host_op_rate 1239964 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1802997891 # Simulator tick rate (ticks/s)
+host_mem_usage 256648 # Number of bytes of host memory used
+host_seconds 0.40 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 25792 # Nu
system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 35344628 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 39817521 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 75162149 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 35344628 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 35344628 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 35344628 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 39817521 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 75162149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 35473791 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 39963030 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 75436821 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 35473791 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 35473791 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 35473791 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 39963030 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 75436821 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 1459458 # number of cpu cycles simulated
+system.cpu.numCycles 1454144 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 500001 # Number of instructions committed
@@ -79,18 +79,18 @@ system.cpu.num_mem_refs 180793 # nu
system.cpu.num_load_insts 124443 # Number of load instructions
system.cpu.num_store_insts 56350 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1459458 # Number of busy cycles
+system.cpu.num_busy_cycles 1454144 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 264.795716 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 265.013024 # Cycle average of tags in use
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 264.795716 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.129295 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.129295 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.129401 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
@@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 403 # n
system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.icache.overall_misses::total 403 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 22568000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 22568000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 22568000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 22568000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 22568000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 22568000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 22165000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 22165000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 22165000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 22165000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 22165000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 22165000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses
@@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000806
system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 286.968386 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 286.968386 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.070061 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.070061 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
@@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 454 # n
system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
system.cpu.dcache.overall_misses::total 454 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 17640000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 17640000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 7784000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 7784000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 25424000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 25424000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 25424000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 25424000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
@@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002511
system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 481.117902 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 481.542013 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 264.802343 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 216.315558 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.008081 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.006601 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.014683 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.014695 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 8620acfdf..80f4c7ad2 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000731 # Number of seconds simulated
-sim_ticks 731328000 # Number of ticks simulated
-final_tick 731328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000729 # Number of seconds simulated
+sim_ticks 728599000 # Number of ticks simulated
+final_tick 728599000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1393062 # Simulator instruction rate (inst/s)
-host_op_rate 1393035 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 509417209 # Simulator tick rate (ticks/s)
-host_mem_usage 231840 # Number of bytes of host memory used
-host_seconds 1.44 # Real time elapsed on the host
-sim_insts 1999829 # Number of instructions simulated
-sim_ops 1999829 # Number of ops (including micro ops) simulated
+host_inst_rate 1327611 # Simulator instruction rate (inst/s)
+host_op_rate 1327594 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 483660925 # Simulator tick rate (ticks/s)
+host_mem_usage 267288 # Number of bytes of host memory used
+host_seconds 1.51 # Real time elapsed on the host
+sim_insts 1999897 # Number of instructions simulated
+sim_ops 1999897 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
@@ -34,29 +34,29 @@ system.physmem.num_reads::cpu2.data 454 # Nu
system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 35267349 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39730463 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35267349 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 39730463 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 35267349 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 39730463 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 35267349 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 39730463 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 299991249 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 141069397 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 39730463 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 39730463 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 39730463 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 39730463 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 299991249 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 35399445 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 39879275 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 35399445 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 39879275 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 35399445 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 39879275 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 35399445 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 39879275 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 301114879 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 35399445 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 35399445 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 35399445 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 35399445 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 141597779 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 35399445 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 39879275 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 35399445 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 39879275 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 35399445 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 39879275 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 35399445 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 39879275 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 301114879 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
@@ -90,7 +90,7 @@ system.cpu0.itb.data_misses 0 # DT
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu0.numCycles 1462656 # number of cpu cycles simulated
+system.cpu0.numCycles 1457198 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 500001 # Number of instructions committed
@@ -109,18 +109,18 @@ system.cpu0.num_mem_refs 180793 # nu
system.cpu0.num_load_insts 124443 # Number of load instructions
system.cpu0.num_store_insts 56350 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 1462656 # Number of busy cycles
+system.cpu0.num_busy_cycles 1457198 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 152 # number of replacements
-system.cpu0.icache.tagsinuse 216.308996 # Cycle average of tags in use
+system.cpu0.icache.tagsinuse 216.402080 # Cycle average of tags in use
system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 216.308996 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.422479 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.422479 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::cpu0.inst 216.402080 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.422660 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.422660 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
@@ -133,12 +133,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 463 #
system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23730000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 23730000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 23730000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 23730000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 23730000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 23730000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23115500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 23115500 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 23115500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 23115500 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 23115500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 23115500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
@@ -151,12 +151,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926
system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51252.699784 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 51252.699784 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51252.699784 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 51252.699784 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51252.699784 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 51252.699784 # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49925.485961 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 49925.485961 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49925.485961 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 49925.485961 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49925.485961 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 49925.485961 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -171,34 +171,34 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 463
system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22341000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 22341000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22341000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 22341000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22341000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 22341000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22189500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 22189500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22189500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 22189500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22189500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 22189500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48252.699784 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48252.699784 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48252.699784 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 48252.699784 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48252.699784 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 48252.699784 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47925.485961 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47925.485961 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47925.485961 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 47925.485961 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47925.485961 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 47925.485961 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 61 # number of replacements
-system.cpu0.dcache.tagsinuse 273.374896 # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse 273.541050 # Cycle average of tags in use
system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 273.374896 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.533935 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.533935 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::cpu0.data 273.541050 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.534260 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.534260 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
@@ -215,14 +215,14 @@ system.cpu0.dcache.demand_misses::cpu0.data 463 #
system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
system.cpu0.dcache.overall_misses::total 463 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17838000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 17838000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7843000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 7843000 # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 25681000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 25681000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 25681000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 25681000 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17473000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 17473000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7671500 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 7671500 # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 25144500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 25144500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 25144500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 25144500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
@@ -239,14 +239,14 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561
system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 55055.555556 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 55055.555556 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 56424.460432 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 56424.460432 # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 55466.522678 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 55466.522678 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 55466.522678 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 55466.522678 # average overall miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53929.012346 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 53929.012346 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55190.647482 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 55190.647482 # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54307.775378 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 54307.775378 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54307.775378 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 54307.775378 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -265,14 +265,14 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 463
system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16866000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16866000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7426000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7426000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24292000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 24292000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24292000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 24292000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16825000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16825000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7393500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7393500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24218500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 24218500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24218500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 24218500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses
@@ -281,35 +281,35 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 52055.555556 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 52055.555556 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53424.460432 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53424.460432 # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52466.522678 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52466.522678 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52466.522678 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52466.522678 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51929.012346 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 51929.012346 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53190.647482 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53190.647482 # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52307.775378 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52307.775378 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52307.775378 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52307.775378 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 124435 # DTB read hits
+system.cpu1.dtb.read_hits 124427 # DTB read hits
system.cpu1.dtb.read_misses 8 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_accesses 124443 # DTB read accesses
+system.cpu1.dtb.read_accesses 124435 # DTB read accesses
system.cpu1.dtb.write_hits 56339 # DTB write hits
system.cpu1.dtb.write_misses 10 # DTB write misses
system.cpu1.dtb.write_acv 0 # DTB write access violations
system.cpu1.dtb.write_accesses 56349 # DTB write accesses
-system.cpu1.dtb.data_hits 180774 # DTB hits
+system.cpu1.dtb.data_hits 180766 # DTB hits
system.cpu1.dtb.data_misses 18 # DTB misses
system.cpu1.dtb.data_acv 0 # DTB access violations
-system.cpu1.dtb.data_accesses 180792 # DTB accesses
-system.cpu1.itb.fetch_hits 500012 # ITB hits
+system.cpu1.dtb.data_accesses 180784 # DTB accesses
+system.cpu1.itb.fetch_hits 499991 # ITB hits
system.cpu1.itb.fetch_misses 13 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 500025 # ITB accesses
+system.cpu1.itb.fetch_accesses 500004 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
@@ -323,73 +323,73 @@ system.cpu1.itb.data_misses 0 # DT
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.workload.num_syscalls 18 # Number of system calls
-system.cpu1.numCycles 1462656 # number of cpu cycles simulated
+system.cpu1.numCycles 1457198 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 499993 # Number of instructions committed
-system.cpu1.committedOps 499993 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 474681 # Number of integer alu accesses
+system.cpu1.committedInsts 499972 # Number of instructions committed
+system.cpu1.committedOps 499972 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 474661 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu1.num_func_calls 14357 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 474681 # number of integer instructions
+system.cpu1.num_conditional_control_insts 38176 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 474661 # number of integer instructions
system.cpu1.num_fp_insts 32 # number of float instructions
-system.cpu1.num_int_register_reads 654273 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 371536 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 654248 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 371519 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu1.num_mem_refs 180792 # number of memory refs
-system.cpu1.num_load_insts 124443 # Number of load instructions
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system.cpu2.dtb.fetch_misses 0 # ITB misses
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system.cpu2.dtb.read_misses 8 # DTB read misses
system.cpu2.dtb.read_acv 0 # DTB read access violations
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system.cpu2.dtb.write_hits 56339 # DTB write hits
system.cpu2.dtb.write_misses 10 # DTB write misses
system.cpu2.dtb.write_acv 0 # DTB write access violations
system.cpu2.dtb.write_accesses 56349 # DTB write accesses
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system.cpu2.dtb.data_misses 18 # DTB misses
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system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
@@ -556,73 +556,73 @@ system.cpu2.itb.data_misses 0 # DT
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
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system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -637,42 +637,42 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 463
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@@ -681,22 +681,22 @@ system.cpu2.dcache.demand_misses::cpu2.data 463 #
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@@ -705,14 +705,14 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561
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system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -731,14 +731,14 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 463
system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16863000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16863000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7430000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7430000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24293000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 24293000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24293000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 24293000 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16832500 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16832500 # number of ReadReq MSHR miss cycles
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+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7398500 # number of WriteReq MSHR miss cycles
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+system.cpu2.dcache.demand_mshr_miss_latency::total 24231000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24231000 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 24231000 # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses
@@ -747,35 +747,35 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561
system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 52046.296296 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 52046.296296 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53453.237410 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53453.237410 # average WriteReq mshr miss latency
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-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52468.682505 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52468.682505 # average overall mshr miss latency
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+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 51952.160494 # average ReadReq mshr miss latency
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system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
system.cpu3.dtb.fetch_acv 0 # ITB acv
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
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system.cpu3.dtb.read_misses 8 # DTB read misses
system.cpu3.dtb.read_acv 0 # DTB read access violations
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system.cpu3.dtb.write_misses 10 # DTB write misses
system.cpu3.dtb.write_acv 0 # DTB write access violations
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system.cpu3.dtb.data_misses 18 # DTB misses
system.cpu3.dtb.data_acv 0 # DTB access violations
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system.cpu3.itb.fetch_misses 13 # ITB misses
system.cpu3.itb.fetch_acv 0 # ITB acv
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+system.cpu3.itb.fetch_accesses 499991 # ITB accesses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.read_acv 0 # DTB read access violations
@@ -789,73 +789,73 @@ system.cpu3.itb.data_misses 0 # DT
system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_accesses 0 # DTB accesses
system.cpu3.workload.num_syscalls 18 # Number of system calls
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system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 499855 # Number of instructions committed
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system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
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system.cpu3.num_fp_insts 32 # number of float instructions
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+system.cpu3.num_int_register_reads 654231 # number of times the integer registers were read
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system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
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system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0 # Percentage of idle cycles
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system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -870,42 +870,42 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 463
system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses
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system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
@@ -914,38 +914,38 @@ system.cpu3.dcache.demand_misses::cpu3.data 463 #
system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
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@@ -964,56 +964,56 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data 463
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@@ -1245,38 +1245,38 @@ system.l2c.overall_mshr_misses::cpu2.data 454 # n
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------